7.3.1 Soft Start-Up

Soft-start circuitry is integrated into the device to avoid a high inrush current during start-up. After the device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps with each step taking 341 μs. This ensures that the output voltage rises slowly to reduce the input current. Additionally, during the start up process, the current limit of the switch is set to half of the normal current limit specification. During this period, the input current is kept below 360 mA (typical). See the start-up waveform of a typical example.

7.3.2 Shutdown

The TPS61158 enters shutdown mode when the CTRL voltage is logic low for more than 3.5 ms. During shutdown, the input supply current for the device is less than 1 μA (maximum). Although the internal FET does not switch in shutdown mode, there is still a DC current path between the input and the LEDs through the inductor and the power diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown. In the typical application with two or more LEDs, the forward voltage is large enough to reverse bias the diode and keep leakage current low.

7.3.3 Current Program

The FB voltage is regulated by a low 0.2-V reference voltage. The LED current is programmed externally using a current-sense resistor RFB in series with the LED string. The value of the RFB is calculated using Equation 1:

Equation 1.

where

• R_FB = current sense resistor at FB pin
• V_FB = 200 mV (regulated voltage of FB pin)
• I_LED = full-scale output current of LEDs
• The output current tolerance depends on the FB voltage accuracy and the current sensor resistor accuracy.

7.3.4 Undervoltage Lockout

An undervoltage lockout prevents operation of the device at input voltages below typical 2.2 V. When the input voltage is below the undervoltage threshold, the device is shut down, and the internal switch FET is turned off. If the input voltage rises by undervoltage lockout hysteresis, the device restarts.

7.3.5 Open LED Protection

Open LED protection circuitry prevents device damage as the result of white LED disconnection. The TPS61158 monitors the voltages at the VOUT pin and FB pin. The circuitry turns off the switch FET and shuts down the device completely if both of the following two conditions are met: 1) the VOUT voltage reaches OVP threshold (28.2 V typical); and 2) FB voltage is lower than half of its regulation voltage. This means the LED string is open or the FB pin is short to ground. As a result, the output voltage falls to the level of the input supply. The device remains in shutdown mode until it is enabled by pulling down the CTRL pin logic low for at least 3.5 ms and then pulling it high.

7.3.6 Thermal Shutdown

An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15°C.

7.4.1 LED Brightness Dimming Mode Selection

The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The dimming mode for the TPS61158 is selected each time the device is enabled. The default dimming mode is PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by the device every time the device starts from the shutdown mode.

1. Pull CTRL pin high to enable the TPS61158 and to start the 1-wire detection window.
2. After the EasyScale detection delay (t_{es_delay}, 100 μs) expires, drive CTRL low for more than the EasyScale detection time (t_{es_detect}, 450 μs).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window (t_{es_win}, 3.5 ms) expires. EasyScale detection window starts from the first CTRL pin low-to-high transition.

The device immediately enters the 1 wire mode once the above 3 conditions are met. The EasyScale communication can start before the detection window expires. Once the dimming mode is programmed, it can not be changed without another start up. This means the device needs to be shutdown by pulling the CTRL low for 3.5 ms and restarts. See Figure 8 for a graphical explanation.

Figure 8. Dimming Mode Detection and Soft Start

7.4.1.1 PWM Brightness Dimming

When the CTRL pin is constantly high, the FB voltage is regulated to 200 mV typically. However, the CTRL pin allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The relationship between the duty cycle and FB voltage is given by Equation 2.

Equation 2. V_FB = Duty × 200 mV

where

• Duty = duty cycle of the PWM signal
• 200 mV = internal reference voltage

As shown in Figure 9, the device chops up the internal 200-mV reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, the TPS61158 regulation voltage is independent of the PWM logic voltage level which often has large variations.

For optimum performance, use the PWM dimming frequency in the range of 20 kHz to 100 kHz. Since the CTRL pin is logic only pin, adding an external RC filter applied to the pin does not work.

The minimum dimming duty cycle the device can support is 1% within the PWM dimming frequency range 20 kHz to 100 kHz.

Figure 9. Block Diagram of Programmable FB Voltage Using PWM Signal

7.4.1.1.1 Digital 1-Wire Brightness Dimming

The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save the processor power and battery life as it does not require a PWM signal all the time, and the processor can enter idle mode if available.

The TPS61158 adopts the EasyScale™ protocol for the digital dimming, which can program the FB voltage to any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo logarithmic curve for the brightness step. See the Table 1 for the FB pin voltage steps. The default step is full scale when the device is first enabled (V_FB = 200 mV). The programmed reference voltage is stored in an internal register. A power reset clears the register value and reset it to default.

7.4.1.1.2 Easyscale: 1-Wire Digital Dimming

EasyScale is a simple but flexible one-pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 10 and Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 58 hex. The data byte consists of five bits for information, two address bits ("00"), and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.1 kBit/sec and up to 100 kBit/sec.

Table 1. Selectable FB Voltage

	FB VOLTAGE (mV)	D4	D3	D2	D1	D0
0	0	0	0	0	0	0
1	5	0	0	0	0	1
2	8	0	0	0	1	0
3	11	0	0	0	1	1
4	14	0	0	1	0	0
5	17	0	0	1	0	1
6	20	0	0	1	1	0
7	23	0	0	1	1	1
8	26	0	1	0	0	0
9	29	0	1	0	0	1
10	32	0	1	0	1	0
11	35	0	1	0	1	1
12	38	0	1	1	0	0
13	44	0	1	1	0	1
14	50	0	1	1	1	0
15	56	0	1	1	1	1
16	62	1	0	0	0	0
17	68	1	0	0	0	1
18	74	1	0	0	1	0
19	80	1	0	0	1	1
20	86	1	0	1	0	0
21	92	1	0	1	0	1
22	98	1	0	1	1	0
23	104	1	0	1	1	1
24	116	1	1	0	0	0
25	128	1	1	0	0	1
26	140	1	1	0	1	0
27	152	1	1	0	1	1
28	164	1	1	1	0	0
29	176	1	1	1	0	1
30	188	1	1	1	1	0
31	200	1	1	1	1	1

Figure 10. EasyScale Protocol Overview

Table 2. EasyScale Bit Description

BYTE	BIT NUMBER	NAME	TRANSMISSION DIRECTION	DESCRIPTION
Device Address Byte 72 hex	7	DA7	IN	0 (MSB device address)
	6	DA6		1
	5	DA5		0
	4	DA4		1
	3	DA3		1
	2	DA2		0
	1	DA1		0
	0	DA0		0 (LSB device address)
Data byte	7 (MSB)	RFA	IN	Request for acknowledge. If high, acknowledge is applied by device.
	6	A1		0 (Address bit A1)
	5	A0		0 (Address bit A0)
	4	D4		Data bit D4
	3	D3		Data bit D3
	2	D2		Data bit D2
	1	D1		Data bit D1
	0 (LSB)	D0		Data bit D0
		ACK	OUT	Acknowledge condition active 0, this condition will only be applied to case RFA bit is set. Open drain output, line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested!

Figure 11. EasyScale Timing, Without Acknowledge (RFA = 0)

Figure 12. EasyScale Timing, With Acknowledge (RFA = 1)

Figure 13. EasyScale— Bit Coding

All bits are transmitted MSB first and LSB last. Figure 11 shows the protocol without acknowledge request (Bit RFA = 0), Figure 12 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least t_start (3.5μs) before the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is needed prior to the device address byte. The transmission of each byte is closed with an End of Stream condition for at least t_EOS (3.5μs).

The bit detection is based on a Logic Detection scheme, where the criterion is the relation between t_LOW and t_HIGH (refer to Figure 13). It can be simplified to:

• Low Bit (Logic 0): t_LOW ≥ 2 x t_HIGH
• High Bit (Logic 1): t_HIGH ≥ 2 x t_LOW

The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between t_HIGH and t_LOW, the logic 0 or 1 is detected.

The acknowledge condition is only applied if:

• Acknowledge is requested by setting RFA bit to 1.
• The transmitted device address matches with the device address of the device.
• Device address byte and data byte are received correctly.

If above conditions are met, after t_valACK (3.5 μs) delay from the moment when the last falling edge of the protocol is detected, an internal ACKN-MOSFET is turned on to pull the CTRL pin low for the time t_ACKN (900 μs maximum), then the Acknowledge condition is valid. During the t_valACK delay, the master controller keeps the line low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge condition. If it reads back a logic 0, it means the device has received the command correctly. The CTRL pin can be used again by the master when the acknowledge condition ends after t_ACKN time.

Note that the acknowledge condition can only be requested in case the master device has an open drain output. For a push-pull output stage, the use a series resistor in the CTRL line to limit the current to 500 μA is recommended to for such cases as:

• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.