SLVSDA7E February   2017  – August 2019 TPS61178

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Under-voltage Lockout
      2. 8.3.2  Enable and Disable
      3. 8.3.3  Startup
      4. 8.3.4  Load Disconnect Gate Driver
      5. 8.3.5  Adjustable Peak Current Limit
      6. 8.3.6  Output Short Protection (with load disconnected FET)
      7. 8.3.7  Adjustable Switching Frequency
      8. 8.3.8  External Clock Synchronization (TPS611781)
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Start-up with the Output Pre-Biased
      12. 8.3.12 Bootstrap Voltage (BST)
      13. 8.3.13 Over-voltage Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
      2. 8.4.2 Auto PFM Mode (TPS61178)
      3. 8.4.3 Forced PWM Mode (TPS611781)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Switching Frequency
      3. 9.2.3 Setting the Current Limit
      4. 9.2.4 Setting the Output Voltage
        1. 9.2.4.1 Selecting the Inductor
        2. 9.2.4.2 Selecting the Output Capacitors
        3. 9.2.4.3 Selecting the Input Capacitors
        4. 9.2.4.4 Loop Stability and Compensation
          1. 9.2.4.4.1 Small Signal Model
          2. 9.2.4.4.2 Loop Compensation Design Steps
          3. 9.2.4.4.3 Selecting the Disconnect FET
          4. 9.2.4.4.4 Selecting the Bootstrap Capacitor
          5. 9.2.4.4.5 VCC Capacitor
      5. 9.2.5 TPS61178 Application Waveform
    3. 9.3 System Examples
      1. 9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
      2. 9.3.2 TPS61178 Without Load Disconnect Function
      3. 9.3.3 TPS611781 External Clock Synchronization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Selecting the Disconnect FET

The TPS61178x provides a gate driver to control an external FET to disconnect the output from the input at shutdown or output short conditions, shown in Figure 25.

TPS61178 LoadDisconnectFETconnection_SLVSDA7.gifFigure 25. Load Disconnect FET Connection

The VDS, IDS and safe operation area (SOA) should be taken into consideration when selecting the FET:

  • The drain-to-source voltage rating should be higher than the output max. voltage, VDS_DIS_MAX = VOUT,
  • The drain-to-source RMS current rating is the maximum output current. I DS_DIS_RMS = IOUT,
  • The SOA should be considered when the output short occurs, and there is heat caused by the short protection response time and surge current, SOA > QSHORT.
  • Equation 32. TPS61178 Eq_Qshort_SLVSDA7.gif

    where

    • VDS_DIS_Max is the maximum drain-source voltage
    • IDS_DIS is the drain-source RMS current
    • ISHORT is the short current
    • TSHORT is the response time before the short protection triggered
    • QSHORT is the heat produced for the output short

For instance: VOUT = 16 V, ISHORT = 20 A , TSHORT = 30 µs.

SOA ≥ 4.8 mJ, VDS_DIS_MAX ≥ 16 V.

The CSD25404Q3 –20 V P-Channel NexFET™ Power FET is used for this design example.

An additional capacitor between the gate and source of the external FET is required to slow the turn-on speed.

Equation 33. TPS61178 tps61178-equation-33.gif

where

  • TON_PFET is the on time of external FET
  • VTH_PFET is the gate threshold of external FET
  • CGS_PFET is the total gate capacitance of connected between gate and source external FET. (including the self-gate-source capacitance of the FET)
  • IDIS_PFET is the discharge current inside of TPS61178x, it is 55 µA typically

Given 1.5 V threshold, CGS_PFET is 10 nF, the TON_PFET is around 300 µs.Please be aware that the maximum turn-on time should not exceed 3 ms, and the maximum capacitance CGS_PFET should be < 100 nF. Otherwise, the TPS61178x could not startup normally if the disconnect FET could not be turn on within the 3 ms.

The gate resistor depends on the gate-source voltage of the external FET,

Equation 34. TPS61178 tps61178-equation-34.gif
Equation 35. TPS61178 tps61178-equation-35.gif

Given the 5-V VGATE, the RGATE = 100 kΩ