SLVSC25B July 2013 – June 2017 TPS61197
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage range(2) | Pin VIN | –0.3 | 33 | V |
Pin FAULT | –0.3 | VIN | ||
Pin ISNS, IFB | –0.3 | 3.3 | ||
Pin EN, PWM, VDD, GDRV, IDRV | –0.3 | 20 | ||
Pin GDRV 10-ns transient | –2 | 20 | ||
All other pins | –0.3 | 7 | ||
Continuous power dissipation | See Thermal Information | |||
Operating junction temperature range | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine model | 200 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Input voltage range | 8 | 30 | V |
VOUT | Output voltage range | VIN | 300 | V |
L1 | Inductor | 4.7 | 470 | µH |
CIN | Input capacitor | 10 | µF | |
COUT | Output capacitor | 1 | 220 | µF |
fSW | Boost regulator switching frequency | 50 | 800 | kHz |
fDIM | PWM dimming frequency | 0.09 | 22 | kHz |
TA | Operating ambient temperature | –40 | 85 | °C |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS61197 | UNITS | |
---|---|---|---|
D (SOIC) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 85.8 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 44.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 43.3 | °C/W |
RψJT | Junction-to-top characterization parameter | 13.5 | °C/W |
RψJB | Junction-to-board characterization parameter | 42.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VIN | Input voltage range | 8 | 30 | V | ||
VVIN_UVLO | Undervoltage lockout threshold | VIN falling | 6.5 | 7 | V | |
VVIN_HYS | VIN UVLO hysteresis | 300 | mV | |||
IQ_VIN | Operating quiescent current into VIN | Device enabled, no switching, VIN = 30 V | 2 | mA | ||
ISD | Shutdown current | VIN = 12 V VIN = 30 V |
25 50 |
µA | ||
VDD | Regulation voltage for internal circuit | 0 mA < IDD < 15 mA | 6.6 | 7 | 7.4 | V |
EN and PWM | ||||||
VH | Logic high input on EN, PWM | VIN = 8 V to 30 V | 1.6 | V | ||
VL | Logic low input on EN, PWM | VIN = 8 V to 30 V | 0.75 | V | ||
RPD | Pulldown resistance on EN, PWM | 400 | 800 | 1600 | kΩ | |
UVLO | ||||||
VUVLOTH | Threshold voltage at UVLO pin | 1.204 | 1.229 | 1.253 | V | |
IUVLO | UVLO input bias current | VUVLO = VUVLOTH – 50 mV | –0.1 | 0.1 | µA | |
VUVLO = VUVLOTH + 50 mV | –4.4 | -3.9 | –3.3 | |||
SOFT START | ||||||
ISS | Soft start charging current | PWM dimming on, VREF< 2 V | 200 | µA | ||
CURRENT REGULATION | ||||||
VIFB_REG | IFB pin regulation voltage | TJ = 25°C to 85°C | 293 | 300 | 307 | mV |
VIFB_SCP | IFB short to ground protection threshold | 200 | mV | |||
VIFB_OVP | IFB over voltage protection threshold | 1 | 1.1 | 1.2 | V | |
IIFB_LEAK | IFB pin leakage current | VIFB = 300 mV | –100 | 100 | nA | |
BOOST REFERENCE VOLTAGE | ||||||
VREF | Reference voltage range for boost controller | 0 | 3.5 | V | ||
IREF_LEAK | Leakage current at REF | TJ = –40°C to 85°C | –25 | 25 | nA | |
OSCILLATOR | ||||||
VFSW | FSW pin reference voltage | 1.8 | V | |||
ERROR AMPLIFIER | ||||||
ISINK | Comp pin sink current | VOVP = VREF + 200 mV, VCOMP = 1V | 20 | µA | ||
ISOURCE | Comp pin source current | VOVP = VREF – 200 mV, VCOMP = 1V | 20 | µA | ||
GmEA | Error amplifier transconductance | 90 | 120 | 150 | µS | |
REA | Error amplifier output resistance | 20 | MΩ | |||
GATE DRIVER | ||||||
RGDRV_SRC | Gate driver impedance when sourcing | VGDRV = 7 V, IGDRV = –20 mA | 5 | 10 | Ω | |
RGDRV_SNK | Gate driver impedance when sinking | VDD = 7 V, IGDRV = 20 mA | 2 | 5 | Ω | |
IGDRV_SRC | Gate driver source current | VDD = 7 V, VGDRV = 5 V | 200 | mA | ||
IGDRV_SNK | Gate driver sink current | VDD = 7 V, VGDRV = 2 V | 400 | mA | ||
VPWM_OCP | Overcurrent detection threshold during PWM | VIN = 8 V to 30 V, TJ = 25°C to 125°C | 376 | 400 | 424 | mV |
VPFM_OCP | Overcurrent detection threshold during PFM | 180 | mV | |||
OVP | ||||||
VOVPTH | Overvoltage protection threshold | 2.98 | 3.04 | 3.1 | V | |
IOVP_LEAK | Leakage current at OVP pin | –100 | 0 | 100 | nA | |
FAULT INDICATOR | ||||||
IFLT_H | Leakage current at high impedance | VFLT = 24 V | 1 | nA | ||
IFLT_L | Sink current at low output | VFLT = 1 V | 2 | 5 | mA | |
THERMAL SHUTDOWN | ||||||
TSTDN | Thermal shutdown threshold | 150 | °C | |||
THYS | Thermal shutdown threshold hysteresis | 15 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ƒSW | Switching frequency | R = 200 kΩ | 187 | 200 | 213 | kHz |
D(max) | Maximum duty cycle | fSW = 200 kHz | 90% | 94% | 98% | |
ton(min) | Minimum pulse width | 300 | ns | |||
ƒEA | Error amplifier crossover frequency | 1000 | kHz |
See Figure 18 | ||
---|---|---|
TITLE | TEST CONDITIONS | FIGURE |
Dimming Linearity | 24 LEDs (VOUT = 80 V), VIN = 24 V | Figure 1 |
Dimming Linearity at Small Dimming Duty Cycle | 24 LEDs (VOUT = 80 V), VIN = 24 V | Figure 2 |
DC Load Efficiency | fSW = 130 kHz | Figure 3 |
Switching Frequency Setting | VIN = 24 V | Figure 4 |
Boost Switching Waveform | VIN = 24 V, VOUT = 80 V, IOUT = 300 mA | Figure 5 |
Dimming Waveform (2% Dimming) | VIN = 24 V, VOUT = 80 V, IOUT = 300 mA, 100-Hz dimming frequency | Figure 6 |
Startup Waveform (1% Dimming) | 100-Hz dimming frequency, 1% dimming duty cycle | Figure 7 |
Startup Waveform (100% Dimming) | 100-Hz dimming frequency, 100% dimming duty cycle | Figure 8 |
Shutdown Waveform (1% Dimming) | 100-Hz dimming frequency, 1% dimming duty cycle | Figure 9 |
Shutdown Waveform (100% Dimming) | 100-Hz dimming frequenc, 100% dimming duty cycle | Figure 10 |
LED Open Protection (1% Dimming) | 100-Hz dimming frequenc, 1% dimming duty cycle | Figure 11 |
LED Open Protection (100% Dimming) | 100-Hz dimming frequenc, 100% Dimming Duty Cycle | Figure 12 |
LED String Short Protection (1% Dimming) | 100-Hz dimming frequency, 1% dimming duty cycle | Figure 13 |
LED String Short Protection (100% Dimming) | 100-Hz dimming frequency, 1% dimming duty cycle | Figure 14 |