SLVSAF7C September   2010  – April 2019 TPS61251

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Soft Start
      3. 9.3.3 Enable
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power Good
      6. 9.3.6 Input Overvoltage Protection
      7. 9.3.7 Load Disconnect and Reverse Current Protection
      8. 9.3.8 Thermal Regulation
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
      2. 9.4.2 Snooze Mode
      3. 9.4.3 100% Duty-Cycle Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Output Voltage Setting
        3. 10.2.2.3 Average Input Current Limit
        4. 10.2.2.4 Maximum Output Current
        5. 10.2.2.5 Inductor Selection
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
        8. 10.2.2.8 Checking Loop Stability
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Development Support
      1. 13.2.1 Custom Design With WEBENCH® Tools
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.3 100% Duty-Cycle Mode

If VIN > VOUT the TPS61251 device offers the lowest possible input-to-output voltage difference while still maintaining current limit operation with the use of the 100% duty-cycle mode. In this mode, the PMOS switch is constantly turned on. During this operation the output voltage follows the input voltage and will not fall below the programmed value if the input voltage decreases below VOUT. The output voltage drop during 100% mode depends on the load current and input voltage, and the resulting output voltage is calculated using Equation 3.

Equation 3. TPS61251 eq3_vout100_lvsaf7.gif

where

  • DCR is the DC resistance of the inductor
  • rDS(on) is the typical on-resistance of the PMOS switch