SLVSET0D May 2020 – October 2021 TPS61378-Q1
PRODUCTION DATA
The TPS61378-Q1 features down mode operation when input voltage is close to or higher than output voltage. In down mode, output voltage is regulated at target value, even when VIN > VO. The TPS61378-Q1 high-side and low-side FETs are switching devices that always work in boost operation, where the isolation FET always works as a linear device.
For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378-Q1 enters down mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz. Exiting down mode requires VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.
In normal operation, the isolation FET is fully on.
When down mode is triggered and VIN is less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above VO pin voltage. An isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage drop.
When down mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin has an approximated 3 V (typical) above the VIN pin voltage. As VIN keeps rising, the OUT pin continues rising with 3 V on top of VIN. In addition, an isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of the OUT pin and VO pin.
Refer to Figure 8-1.
Take care during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the device operates in down mode and the isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).