SLVSET0E May   2020  – October 2024 TPS61378-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
      3. 7.3.3  Enable and Soft Start
      4. 7.3.4  Shut Down
      5. 7.3.5  Switching Frequency Setting
      6. 7.3.6  Spread Spectrum Frequency Modulation
      7. 7.3.7  Adjustable Peak Current Limit
      8. 7.3.8  Bootstrap
      9. 7.3.9  Load Disconnect
      10. 7.3.10 MODE/SYNC Configuration
      11. 7.3.11 Overvoltage Protection (OVP)
      12. 7.3.12 Output Short Protection/Hiccup
      13. 7.3.13 Power-Good Indicator
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced PWM Mode
      2. 7.4.2 Auto PFM Mode
      3. 7.4.3 External Clock Synchronization
      4. 7.4.4 Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming the Output Voltage
        2. 8.2.2.2 Setting the Switching Frequency
        3. 8.2.2.3 Setting the Current Limit
        4. 8.2.2.4 Selecting the Inductor
        5. 8.2.2.5 Selecting the Output Capacitors
        6. 8.2.2.6 Selecting the Input Capacitors
        7. 8.2.2.7 Loop Stability and Compensation
          1. 8.2.2.7.1 Small Signal Model
          2. 8.2.2.7.2 Loop Compensation Design Steps
          3. 8.2.2.7.3 Selecting the Bootstrap Capacitor
          4. 8.2.2.7.4 VCC Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
    6. 11.6 Electrostatic Discharge Caution
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.2.7.2 Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with the given inductor and output capacitance.

  1. Set the Crossover Frequency, ƒC.

    The first step is to set the loop crossover frequency, ƒC. The higher the crossover frequency, the faster the loop response is. It is generally accepted that the loop gain crosses over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then, calculate the loop compensation network values of RC, CC, and CP by the following equations.

  2. Set the Compensation Resistor, RC.

    By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~ = RC, so RC × GEA sets the compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ results in the total loop gain, T(s) = KPS(s) × HEA(s), being zero at ƒC.

    Therefore, to approximate a single-pole rolloff up to fP2, rearrange Equation 20 to solve for RC so that the compensation gain, KEA, at fC is the negative of the gain, KPS. Read at frequency fC for the power stage bode plot or more simply:

    Equation 24. TPS61378-Q1

    where

    • KEA is gain of the error amplifier network
    • KPS is the gain of the power stage
    • GEA is the transconductance of the amplifier, the typical value of GEA = 70 µA / V
  3. Set the Compensation Zero capacitor, CC.

    Place the compensation zero at the power stage ROUT ,COUT pole’s position to get:

    Equation 25. TPS61378-Q1
    Equation 26. TPS61378-Q1
  4. Set the Compensation Pole Capacitor, CP.

    Place the compensation pole at the zero produced by RESR and COUT. It is useful for canceling unhelpful effects of the ESR zero.

    Equation 27. TPS61378-Q1
    Equation 28. TPS61378-Q1

    Set ƒP2 = ƒESR, and get:

    Equation 29. TPS61378-Q1