SLVSET0D May 2020 – October 2021 TPS61378-Q1
PRODUCTION DATA
The TPS61378-Q1 integrates a power-good function. The power-good output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage supply like VCC. The PG pin goes high with a typical 3.4-ms delay time after VOUT reaches 90% of the target output voltage. When the output voltage drops below 85% of the target output voltage, the PG pin immediately goes low without delay.