SLVSFJ0B March 2021 – October 2021 TPS61379-Q1
PRODUCTION DATA
The TPS61379-Q1 features Down mode operation when input voltage is close to or higher than output voltage. In Down mode, output voltage is regulated at target value even when VIN > VO. The high-side and low-side FETs of the TPS61379-Q1 are switching devices that always work in boost operation, where the isolation FET always works as a linear device.
For boost circuits, on time or duty cycle is reduced as input voltage approaches output voltage. The TPS61379-Q1 enters Down mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz; while exiting Down mode requires VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.
In normal operation, isolation FET is fully on.
When Down mode is triggered and VIN is less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above VO pin voltage. Isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage drop.
When Down mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin has an approximated 3 V (typical) above VIN pin voltage, as VIN keeps rising, the OUT pin continues to raise with 3 V on top of VIN, isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of OUT pin and VO pin.
Refer to Figure 8-1.
Care should be taken during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the device operates in Down mode and isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).