SLVSFJ0B March   2021  – October 2021 TPS61379-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Bootstrap
      8. 8.3.8  Load Disconnect
      9. 8.3.9  MODE/SYNC Configuration
      10. 8.3.10 Overvoltage Protection (OVP)
      11. 8.3.11 Output Short Protection/Hiccup
      12. 8.3.12 Power-Good Indicator
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Selecting the Inductor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Input Capacitors
        6. 9.2.2.6 Loop Stability and Compensation
          1. 9.2.2.6.1 Small Signal Model
          2. 9.2.2.6.2 Loop Compensation Design Steps
          3. 9.2.2.6.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.6.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.6.1 Small Signal Model

The TPS61379-Q1 uses the fixed frequency peak current mode control. There is an internal adaptive slope compensation to avoid the subharmonic oscillation. With the inductor current information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. Figure 9-2 shows the equivalent small signal elements of a boost converter.

Figure 9-2 TPS61379-Q1 Control Equivalent Circuitry Model

The small signal of power stage is:

Equation 13. GUID-83FA4C6B-86A3-4B15-B8BE-9811A2FD8ACD-low.gif

where

  • D is the duty cycle
  • ROUT is the output load resistor
  • RSENSE is the equivalent internal current sense resistor, which is typically 118 mΩ

The single pole of the power stage is:

Equation 14. GUID-9D31B12E-9959-4312-95D1-0C70F0D489AD-low.gif

where

  • COUT is the output capacitance. For a boost converter having multiple, identical output capacitors in parallel, simply combine the capacitors with the equivalent capacitance

The zero created by the ESR of the output capacitor is:

Equation 15. GUID-FF33CE40-102C-4705-B02D-37AD15CF3F51-low.gif

where

  • RESR is the equivalent resistance in series of the output capacitor

The right-hand plane zero is:

Equation 16. GUID-DDBF920E-982D-404F-A66E-CA2A4EAC4FF4-low.gif

where

  • D is the duty cycle
  • ROUT is the output load resistor
  • L is the inductance

Equation 17 shows the equation for feedback resistor network and the error amplifier.

Equation 17. GUID-C56E5040-BBCA-4A6D-AF84-7C28F4AFB366-low.gif

where

  • REA is the output impedance of the error amplifier and typical REA = 500 MΩ.
  • ƒP1, ƒP2 is the pole's frequency of the compensation, fZ is the zero’s frequency of the compensation network
Equation 18. GUID-A28C15BB-FE3F-4B9D-B059-332B85A90282-low.gif

where

  • CC is the zero capacitor compensation
Equation 19. GUID-B56D0039-C147-4F56-A998-86D399C3FDA8-low.gif

where

  • CP is the pole capacitor compensation
  • RC is the resistor of the compensation network
Equation 20. GUID-710D1B1E-E921-43CF-9428-CDDAF4A24F41-low.gif