SLVSCM3B
january 2015 – august 2023
TPS62065-Q1
,
TPS62067-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Mode Selection (TPS62065-Q1) and Forced PWM Mode (TPS62067A-Q1)
9.3.2
Power Good (PG, TPS62067x-Q1)
9.3.3
Enable
9.3.4
Shutdown and Output Discharge
9.3.5
Soft Start
9.3.6
Undervoltage Lockout (UVLO)
9.3.7
Internal Current Limit and Foldback Current Limit For Short-Circuit Protection
9.3.8
Clock Dithering
9.3.9
Thermal Shutdown
9.4
Device Functional Modes
9.4.1
Power Save Mode
9.4.1.1
Dynamic Voltage Positioning
9.4.1.2
100% Duty-Cycle Low-Dropout Operation
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Output Voltage Setting
10.2.2.2
Output Filter Design (Inductor And Output Capacitor)
10.2.2.2.1
Inductor Selection
10.2.2.2.2
Output Capacitor Selection
10.2.2.2.3
Input Capacitor Selection
10.2.2.3
Checking Loop Stability
10.2.3
Application Curves
10.3
Power Supply Recommendations
10.4
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DSG|8
MPDS308C
Thermal pad, mechanical data (Package|Pins)
DSG|8
QFND141I
Orderable Information
slvscm3b_oa
slvscm3b_pm
10.4.2
Layout Example
Figure 10-20
PCB Layout