SLVSCM3B january   2015  – august 2023 TPS62065-Q1 , TPS62067-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6.     Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Selection (TPS62065-Q1) and Forced PWM Mode (TPS62067A-Q1)
      2. 9.3.2 Power Good (PG, TPS62067x-Q1)
      3. 9.3.3 Enable
      4. 9.3.4 Shutdown and Output Discharge
      5. 9.3.5 Soft Start
      6. 9.3.6 Undervoltage Lockout (UVLO)
      7. 9.3.7 Internal Current Limit and Foldback Current Limit For Short-Circuit Protection
      8. 9.3.8 Clock Dithering
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
        1. 9.4.1.1 Dynamic Voltage Positioning
        2. 9.4.1.2 100% Duty-Cycle Low-Dropout Operation
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
        2. 10.2.2.2 Output Filter Design (Inductor And Output Capacitor)
          1. 10.2.2.2.1 Inductor Selection
          2. 10.2.2.2.2 Output Capacitor Selection
          3. 10.2.2.2.3 Input Capacitor Selection
        3. 10.2.2.3 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS62065-Q1, TPS62067-Q1, and TPS62067A-Q1 devices are highly-efficient, synchronous, step-down DC/DC converters. The device provides up to 2-A output current.

With an input voltage range of 2.9 V to 6 V the device is an excellent fit for power conversion from a 5-V or 3.3-V system supply rail. The TPS62065-Q1 and TPS62067-Q1 device operates at 3-MHz fixed frequency and enters power-save mode operation at light load currents to maintain high efficiency over the entire load current range. The power save mode is optimized for low output-voltage ripple. For low noise applications, the TPS62065-Q1 device can be forced into fixed frequency PWM mode by pulling the MODE pin high. The TPS62067-Q1 provides an open drain power good output and has a power save mode, while the TPS62067A-Q1 operates in fixed frequency PWM mode. In the shutdown mode, the current consumption is reduced to 5 µA and an internal circuit discharges the output capacitor. The TPS62065-Q1, TPS62067-Q1, and TPS62067A-Q1 devices are optimized for operation with a tiny 1-µH inductor and a small 10-µF output capacitor to achieve smallest design size and high regulation performance.

The new product, TPS628502-Q1, offers reduced BOM cost and size, higher efficiency and other features.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS62065-Q1, TPS62067-Q1, TPS62067A-Q1 DSG (WSON, 8) 2.00 mm × 2.00 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-11C25B3D-E4C6-42DD-9079-5F5E831EE830-low.gifTypical Application Circuit
GUID-DFE91A18-7A11-4211-8533-6748671D5C7B-low.gifEfficiency vs Load Current