SLVSD94F November 2017 – November 2024 TPS62088 , TPS62088A , TPS62089A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
As the load current decreases, the device enters power save mode operation. The power save mode occurs when the inductor current becomes discontinuous. Power save mode is based on a fixed on-time architecture, as related in Equation 1.
In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing the output capacitor or inductor value.
When the device operates close to 100% duty cycle mode, the device cannot enter power save mode regardless of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains output regulation in PWM mode.