SLVSDZ7A September   2017  – December 2017 TPS62097-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      1.8-V Output, Typical Application
      2.      1.8-V Output, Efficiency, MODE = Open
  4. 4 Revision History
  5. 5 Terminal Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommend Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 100% Duty Cycle Mode
      2. 7.3.2 Switch Current Limit and Hiccup Short Circuit Protection
      3. 7.3.3 Under Voltage Lockout (UVLO)
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Function Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Power Save Mode and Forced PWM Mode (MODE)
      3. 7.4.3 Soft Startup (SS/TR)
      4. 7.4.4 Voltage Tracking (SS/TR)
      5. 7.4.5 Power Good (PG)
  8. 8 Application Information
    1. 8.1 Application Information
    2. 8.2 1.8-V Output Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Output Filter Design
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Power Save Mode and Forced PWM Mode (MODE)

The MODE pin is a multi-functional pin that allows the device operation in forced PWM mode or PWM/PSM mode, and to select the PWM switching frequency.

Once the EN pin is pulled high, the IC enables internal circuit blocks and prepares to ramp the output up. The period between the rising edge of the EN pin and the beginning of the power stage switching is called the MODE detection time, typically 50µs. During the MODE detection time period, shown in Figure 3, the PWM switching frequency and operating mode are set by the MODE pin status, as shown in Table 1.

The PWM switching frequency can't be changed after the detection time period. Only when the device is set in PWM/PSM mode during the MODE detection time period (MODE = AGND), it is possible to switch between PWM/PSM and forced PWM operation modes by toggling the MODE pin with a GPIO pin of a micro-controller, for example. The other four MODE pin selections force the device in PWM mode only.

TPS62097-Q1 Internal_Block_Powerup_Sequence.gifFigure 3. Power Up Sequence

Table 1. Switching Frequency and Mode Selection

Typical PWM Switching Frequency (MHz)Resistance at MODE pin
(E24 EIA Value)		Toggle MODE pin after MODE detectionON-Time EquationOperating Mode
1.50 8.2kΩ ±5% No tON = 667ns x VOUT / VIN Forced PWM
1.75 18kΩ ±5% No tON = 571ns x VOUT / VIN Forced PWM
2.00 AGND Yes tON = 500ns x VOUT / VIN PWM/PSM and Forced PWM
2.25 39kΩ ±5% No tON = 444ns x VOUT / VIN Forced PWM
2.50 75kΩ ±5% or Open No tON = 400ns x VOUT / VIN Forced PWM

Connecting the MODE pin to AGND with a resistor or leaving the MODE pin open forces the device into PWM mode for the whole load range. The device operates with a constant switching frequency that allows simple filtering of the switching frequency for noise sensitive applications. In forced PWM mode, the efficiency is lower than that of PSM at light load.

Connecting the MODE pin to the AGND pin enables Power Save Mode with an automatic transition between PWM and Power Save Mode. As the load current decreases and the inductor current becomes discontinuous, the device enters Power Save Mode operation automatically. In Power Save Mode, the switching frequency is reduced and estimated by Equation 2. In Power Save Mode, the output voltage rises slightly above the nominal output voltage, as shown in Figure 13. This effect is minimized by increasing the output capacitor.

Equation 2. TPS62097-Q1 EQ_PFM_Fsw.gif

When the device operates close to 100% duty cycle mode, the TPS62097-Q1 can't enter Power Save Mode regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The device maintains output regulation in PWM mode.