The TPS6212x device is a highly efficient synchronous step-down DC-DC converter optimized for low-power applications. The device supports up to 75-mA output current and allows the use of tiny external inductors and capacitors.
The wide operating input voltage range of 2 V to 15 V supports energy harvesting, battery powered and as well 9-V or 12-V line powered applications.
With its advanced hysteretic control scheme, the converter provides power save mode operation. At light loads the converter operates in pulse frequency modulation (PFM) mode and transitions automatically in pulse width modulation (PWM) mode at higher load currents. The power save mode maintains high efficiency over the entire load current range. The hysteretic control scheme is optimized for low output ripple voltage in PFM mode in order to reduce output noise to a minimum. The device consumes only 10-µA quiescent current from VIN in PFM mode operation.
In shutdown mode, the device is turned off.
An open-drain power good output is available in the TPS62120 and indicates once the output voltage is in regulation.
The TPS62120 has an additional SGND pin which is connected to GND during shutdown mode. This output can be used to discharge the output capacitor.
The TPS6212x operates over an free air temperature range of –40°C to 85°C. The TPS62120 is available in a small 8-pin SOT-23 package and the TPS62122 in a 2 mm × 2 mm 6-pin DFN package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS62120 | SOT-23 (8) | 2.90 mm × 1.63 mm |
TPS62122 | SON (6) | 2.00 mm × 2.00 mm |
Changes from * Revision (July 2010) to A Revision
PART NUMBER | ACTIVE DISCHARGE SWITCH | POWER GOOD | VOUT |
---|---|---|---|
TPS62120(1) | yes | Open-Drain | adjustable |
TPS62122(2) | no | no | adjustable |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | DFN | SOT-23 | ||
EN | 4 | 3 | I | Pulling this pin to high activates the device. Low level shuts it down. This pin must be terminated. |
FB | 3 | 5 | I | This is the feedback pin for the regulator. Connect external resistor-divider to this pin. |
GND | 6 | 2 | PWR | GND supply pin. |
PG | — | 6 | O | This pin is available in TPS62120 only. Open-drain power good output. Connect this terminal through a pullup resistor to a voltage rail up to 5.5 V or leave it open. This pin can sink 500 µA. |
SGND | — | 4 | I | This pin is available in TPS62120 only. Open-drain output which is turned on during shutdown mode (EN = 0) or VIN is below the UVLO threshold. The output connects the SGND pin to GND through an internal MOSFET with typical 370-Ω RDS(ON). When the device is enabled (EN = 1), this output is high impedance. To discharge the output capacitor during shutdown mode, connect this pin to VOUT (output capacitor) or leave it open. |
SW | 1 | 7 | O | This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this terminal. Do not tie this pin to VIN, VOUT or GND. |
VIN | 5 | 1 | PWR | VIN power supply pin. |
VOUT | 2 | 8 | I | This pin must be connected to the output capacitor. |
— | Exposed Thermal Pad | — | — | Exposed thermal pad available only in DRV package option. This pad must be connected to GND. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VI | Voltage at VIN(2) | –0.3 | 17 | V | |
Voltage at SW PIN | dynamically during switching t < 10 µs | 17 | V | ||
static DC | –0.3 | 6 | |||
Voltage at EN PIN(2) | –0.3 | VIN +0.3, but ≤17 | V | ||
Voltage on FB Pin | –0.3 | 3.6 | V | ||
Voltage at PG, VOUT, SGND(2) | –0.3 | 6 | V | ||
IIN | Current into PG pin | 0.5 | mA | ||
Maximum operating junction temperature, TJ | –40 | 125 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage VIN, device in operation | 2 | 15 | V | ||
Output current capability | VIN = 2 V, VOUT = 1.8 V, DCRL = 0.7 Ω | 25 | mA | ||
VIN ≥ 2.5 V, VOUT = 1.8 V, DCRL = 0.7 Ω | 75 | ||||
Effective inductance | 10 | 22 | 33 | µH | |
Effective output capacitance | 1.0 | 2 | 33 | µF | |
Output voltage | 1.2 | 5.5 | V | ||
Operating ambient temperature TA(1), (unless otherwise noted) | –40 | 85 | °C | ||
Operating junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | TPS62120 | TPS62122 | UNIT | |
---|---|---|---|---|
DCN [SOT-23] | DRV [DFN] | |||
8 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 259.7 | 114.4 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 114.1 | 73.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 185.8 | 201.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 21.6 | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 121.6 | 94.9 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | n/a | 122.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
VIN | Input voltage range(1) | Device operating | 2 | 15 | V | |
IQ | Quiescent current | IOUT = 0 mA, device not switching, EN = VIN, regulator sleeps | 11 | 18 | µA | |
IOUT = 0 mA, device switching, VIN = 8 V, VOUT = 1.8 V | 13 | |||||
IActive | Active mode current consumption | VIN = 5.5 V = VOUT, TJ = 25°C, high-side MOSFET switch fully turned on | 240 | 275 | µA | |
ISD | Shutdown current | EN = GND, VOUT = SW = 0 V, VIN = 3.6 V (2) | 0.3 | 1.2 | µA | |
VUVLO | Undervoltage lockout threshold | Falling VIN | 1.85 | 1.95 | V | |
Rising VIN | 2.5 | 2.61 | ||||
ENABLE, THRESHOLD | ||||||
VIH TH | Threshold for detecting high EN | 2 V ≤ VIN ≤ 15 V, rising edge | 0.8 | 1.1 | V | |
VIL TH HYS | Threshold for detecting low EN | 2 V ≤ VIN ≤ 15 V, falling edge | 0.4 | 0.6 | V | |
IIN | Input bias current, EN | EN = GND or VIN | 0 | 50 | nA | |
POWER SWITCH | ||||||
RDS(ON) | High-side MOSFET ON-resistance | VIN = 3.6 V | 2.3 | 3.4 | Ω | |
VIN = 8 V | 1.75 | 2.5 | ||||
Low-side MOSFET ON-resistance | VIN = 3.6 V | 1.3 | 2.5 | |||
VIN = 8 V | 1.2 | 1.75 | ||||
ILIMF | Forward current limit MOSFET high-side | VIN = 8 V, open loop | 200 | 250 | 400 | mA |
TSD | Thermal shutdown | Increasing junction temperature | 150 | °C | ||
Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | |||
REGULATOR | ||||||
tONmin | Minimum ON time | VIN = 3.6 V, VOUT = 1.8 V | 700 | ns | ||
tOFFmin | Minimum OFF time | VIN = 3.6 V, VOUT = 1.8 V | 60 | ns | ||
VREF | Internal reference voltage | 0.8 | V | |||
VFB | Feedback FB voltage comparator threshold | Referred to 0.8-V internal reference | –2.5% | 0% | 2.5% | |
Feedback FB voltage line regulation | IOUT = 50 mA (4) | 0.04 | %/V | |||
IIN | Input bias current FB | VFB = 0.8 V | 0 | 50 | nA | |
tStart | Regulator start-up time | Time from active EN to device starts switching, VIN = 2.6 V | 50 | 150 | µs | |
tRamp | Output voltage ramp time | Time to ramp up VOUT = 1.8 V, no load (3) | 120 | 300 | ||
ILK_SW | Leakage current into SW pin | VOUT = VIN = VSW = 1.8 V, EN = GND, device in shutdown mode | 1 | 1.5 | µA | |
POWER GOOD OUTPUT (TPS62120) | ||||||
VTHPG | Power good threshold voltage | Rising VFB feedback voltage | 93% | 95% | 97% | |
Falling VFB feedback voltage | 87% | 90% | 93% | |||
VOL | Output low voltage | Current into PG pin I = 500 µA, VOUT > 1.5 V | 165 | mV | ||
Current into PG pin I = 100 µA, 1.2 V < VOUT < 1.5 V | 50 | |||||
VH | Output high voltage | Open drain output, external pull up resistor | 5.5 | V | ||
ILKG | Leakage current into PG pin | V(PG) = 1.8 V, EN = high, FB = 0.85 V | 0 | 50 | nA | |
Leakage into VOUT pin | V(OUT) = 1.8 V | 0 | 50 | nA | ||
TPGDL | Internal power good comparator delay time | VOUT = 1.8 V | 2 | 5 | µs | |
SGND OPEN DRAIN OUTPUT (TPS62120) | ||||||
RDS(ON) | NMOS drain source resistance | SGND = 1.8 V, VIN = 2 V | 370 | Ω | ||
ILKG | Leakage current into SGND pin | EN = VIN, SGND = 1.8 V | 0 | 50 | nA |
The TPS6212x synchronous step-down converter family uses an unique hysteretic PFM/PWM controller scheme which enables switching frequencies of up to 800 kHz, excellent transient response and AC load regulation at operation with small output capacitors.
At high load currents the converter operates in quasi fixed frequency pulse width modulation (PWM) mode operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switch pulse to ramp the inductor current and charge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 10 µA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.
A significant advantage of TPS6212x compared to other hysteretic controller topologies is its excellent DC and AC load regulation capability in combination with low output voltage ripple over the entire load range which makes this part well suited for audio and RF applications.
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. The circuit prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.5 V typical for rising VIN and 1.85 V typical for falling VIN. The hysteresis between rising and falling UVLO threshold ensures proper start-up even with high-impedance sources. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level.
The device starts operation when EN pin is set high and the input voltage VIN has tripped the UVLO threshold for rising VIN. It starts switching after the regulator start-up time tStart of typically 50 µs has expired and enters the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating.
EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.3 µA.
In this mode, the high-side and low-side MOSFET switches as well as the entire internal-control circuitry are switched off.
In TPS62120 the internal N-MOSFET at pin SGND is activated and connects SGND to GND.
The Power Good Output is an open-drain output available in TPS62120. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB voltage and internal reference. The PG output provides a high level (open-drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the feedback voltage falls below typical 90% of its nominal value. The PG output is high (high impedance) with an internal delay of typically 2 µs. A pullup resistor is needed to generate a high level and limit the current into the PG pin to 0.5 mA. The PG pin can be connected through pullup resistors to a voltage up to 5.5 V.
The PG output is pulled low if the device is enabled but the input voltage is below the UVLO threshold or the device is turned into shutdown mode.
This is an NMOS open-drain output with a typical RDS(ON) of 370 Ω and can be used to discharge the output capacitor. The internal NMOS connects SGND pin to GND once the device is in shutdown mode or VIN falls below the UVLO threshold during operation. SGND becomes high impedance once the device is enabled and VIN is above the UVLO threshold. If SGND is connected to the output, the output capacitor is discharged through SGND.
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis.
The TPS6212x has an internal soft-start circuit which controls the ramp-up of the output voltage and limits the inrush current during start-up. This limits input voltage drop when a battery or a high-impedance power source is connected to the input of the converter.
The soft-start system generates a monotonic ramp up of the output voltage with a ramp of typically 15 mV/µs and reaches an output voltage of 1.8 V in typically 170 µs after EN pin was pulled high. The TPS6212x is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.
During start-up the device can provide an output current of half of the high-side MOSFET switch current limit ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during start-up. In this case the start-up ramp of the output voltage will be slower.
The feedback comparator monitors the voltage on the FB pin and compares it to an internal 800-mV reference voltage.
The feedback comparator trips once the FB voltage falls below the reference voltage. A switching pulse is initiated and the high-side MOSFET switch is turned on. The switch remains turned on at least for the minimum on-time TONmin of typical 700 ns until the feedback voltage is above the reference voltage or the inductor current reaches the high-side MOSFET switch current limit ILIMF. Once the high-side MOSFET switch turns off, the low-side MOSFET switch is turned on and the inductor current ramps down. The switch is turned on at least for the minimum off time TOFFmin of typically 60 ns. The low-side MOSFET switch stays turned on until the FB voltage falls below the internal reference and trips the FB comparator again. This will turn on the high-side MOSFET switch for a new switching cycle.
If the feedback voltage stays above the internal reference the low-side MOSFET switch is turned on until the zero current comparator trips and indicates that the inductor current has ramped down to zero. In this case, the load current is much lower than the average inductor current provided during one switching cycle. The regulator turns the low-side and high-side MOSFET switches off (high impedance state) and enters a sleep cycle with reduced quiescent current of typically 10 uA until the output voltage falls below the internal reference voltage and the feedback comparator trips again. This is called PFM mode and the switching frequency depends on the load current, input voltage, output voltage and the external inductor value.
Once the high-side switch current limit comparator has tripped its threshold of ILIMF, the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on until the inductor current has ramped down to zero.
The minimum on time TONmin for a single pulse can be estimated to:
Therefore the peak inductor current in PFM mode is approximately:
The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 × ILPFMpeak.
With:
TON = High-side MOSFET switch on time [µs]
VIN = Input voltage [V]
VOUT = Output voltage [V]
L = Inductance [µH]
ILPFMpeak = PFM inductor peak current [mA]
The maximum switch frequency can be estimated to:
The device will increase the on time of the high-side MOSFET switch once the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This will reduce the switch frequency.
With further decreasing input voltage VIN the high-side MOSFET switch is turned on completely. In this case the converter provides a low input-to-output voltage difference. This is particularly useful in applications with widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:
where
The TPS6212x integrates a high-side MOSFET switch current limit ILIMF to protect the device against short circuit. The current in the high-side MOSFET switch is monitored by current limit comparator and once the current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit 0.5 × ILIMF.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS6212x device is a highly efficient synchronous step-down DC-DC converter optimized for low-power applications. With its wide input voltage range, the device also fits for energy harvesting applications to convert electrical power from electromagnetic transducers.
The device operates over an input voltage range from 2 V to 15V. The output voltage is adjustable using an external feedback divider network.
The design guideline provides a component selection to operate the device within the Recommended Operating Conditions.
The output voltage can be calculated to:
To minimize the current through the feedback divider network, R2 should be within the range of 82 kΩ to 360 kΩ. The sum of R1 and R2 should not exceed approximately 1 MΩ, to keep the network robust against noise. An external feedforward capacitor Cff is required for optimum regulation performance. R1 and Cff places a zero in the feedback loop.
The value for Cff can be calculated as:
Table 1 shows a selection of suggested values for the feedback divider network for most common output voltages.
VOLTAGE SETTING (V) | 3.06 | 3.29 | 2.00 | 1.80 | 1.20 | 5.00 |
---|---|---|---|---|---|---|
R1 [kΩ] | 510 | 560 | 360 | 300 | 180 | 430 |
R2 [kΩ] | 180 | 180 | 240 | 240 | 360 | 82 |
Cff [pF] | 15 | 22 | 22 | 22 | 27 | 15 |
The TPS6212x operates with effective inductance values in the range of 10 µH to 33 µH and with effective output capacitance in the range of 1 µF to 33 µF. The device is optimized to operate for an output filter of L = 22 µH and COUT = 4.7 µF. Larger or smaller inductor and capacitor values can be used to optimize the performance of the device for specific operation conditions. For more details, see Checking Loop Stability.
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be estimated according to Equation 8.
Equation 9 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 9. This is recommended because during heavy load transient the inductor current will rise above the calculated value. A more conservative way is to select the inductor saturation current according to the high-side MOSFET switch current limit ILIMF.
where
In DC-DC converter applications, the efficiency is essentially affected by the inductor AC resistance (that is, quality factor) and by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following frequency-dependent components:
The following inductor series from different suppliers have been used with the TPS6212x converters.
INDUCTANCE (µH) | DIMENSIONS (mm3) | INDUCTOR TYPE | SUPPLIER |
---|---|---|---|
22 | 3 × 3 × 1.5 | LQH3NPN | Murata |
18/22 | 3 × 3 × 1.5 | LPS3015 | Coilcraft |
The unique hysteretic PFM/PWM control scheme of the TPS6212x allows the use of ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At light load currents the converter operates in power save mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM mode and tighten DC output accuracy in PFM mode.
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications a 4.7 µF to 10 µF ceramic capacitor is recommended. The voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering.
For specific applications like energy harvesting a tantalum or tantalum polymer capacitor can be used to achieve a specific DC-DC converter input capacitance. Tantalum capacitors provide much better DC bias performance compared to ceramic capacitors. In this case a 1-µF or 2.2-µF ceramic capacitor should be used in parallel to provide low ESR.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce large ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings.
Table 3 shows a list of input and output capacitors.
CAPACITANCE (µF) | SIZE | CAPACITOR TYPE | USAGE | SUPPLIER |
---|---|---|---|---|
4.7 | 0603 | GRM188 series 6.3 V X5R | COUT | Murata |
2.2 | 0603 | GRM188 series 6.3 V X5R | COUT | Murata |
4.7 | 0805 | GRM21Bseries 25 V X5R | CIN | Murata |
10 | 0805 | GRM21Bseries 16 V X5R | CIN | Murata |
8.2 | B2 (3.5 × 2.8 × 1.9) | 20TQC8R2M (20 V) | CIN | Sanyo |
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. During application of the load transient and the turn on of the high-side MOSFET switch, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET RDS(on)) which are temperature dependent, the loop stability analysis should be done over the input voltage range, load current range, and temperature range
All graphs have been generated using the circuit as shown in Figure 7 unless otherwise noted.
Beside the power good open drain output (PG pin) and the open drain output for output discharge (SGND pin) the TPS62122 provides the same functionality as the TPS62120.
The TPS6212x is operating with a wide input voltage range from 2 V to 15 V. An open-drain power good output and an additional SGND pin is available in the TPS62120 for output voltage regulation and to discharge the output capacitor.
The TPS6212x device family has no special requirements for its input power supply. The output current of the input power supply needs to be rated according to the supply voltage, output voltage, and output current of the TPS6212x.
As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues, as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor.
Use a common Power GND node and a different node for the signal GND to minimize the effects of ground noise. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. The FB divider network and the VOUT line must be connected to the output capacitor. The VOUT pin of the converter should be connected through a short trace to the output capacitor. The FB line must be routed away from noisy components and traces (for example, SW line).