SLVSAD5A July   2010  – August 2015 TPS62120 , TPS62122

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout
      2. 8.3.2 Enable and Shutdown
      3. 8.3.3 Power Good Output
      4. 8.3.4 SGND Open-Drain Output
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Main Control Loop
      3. 8.4.3 100% Duty Cycle Low-Dropout Operation
      4. 8.4.4 Short-Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS62120 With Open-Drain Output
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Voltage Setting
          2. 9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Output Capacitor Selection
          5. 9.2.1.2.5 Input Capacitor Selection
          6. 9.2.1.2.6 Checking Loop Stability
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Standard Circuit for TPS62122
    3. 9.3 System Examples
      1. 9.3.1 TPS62120 1.8-V Output Voltage Configuration
      2. 9.3.2 TPS62120 3.06-V Output Voltage Configuration
      3. 9.3.3 TPS62122 2.0-V Output Voltage Configuration
      4. 9.3.4 TPS62120 1.8-V VOUT Configuration Powered From a High-Impedance Source
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPS6212x synchronous step-down converter family uses an unique hysteretic PFM/PWM controller scheme which enables switching frequencies of up to 800 kHz, excellent transient response and AC load regulation at operation with small output capacitors.

At high load currents the converter operates in quasi fixed frequency pulse width modulation (PWM) mode operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switch pulse to ramp the inductor current and charge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 10 µA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.

A significant advantage of TPS6212x compared to other hysteretic controller topologies is its excellent DC and AC load regulation capability in combination with low output voltage ripple over the entire load range which makes this part well suited for audio and RF applications.

8.2 Functional Block Diagram

TPS62120 TPS62122 fbd_lvsad5.gif
1. Function available in TPS62120

8.3 Feature Description

8.3.1 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from misoperation at low input voltages. The circuit prevents the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions. The UVLO threshold is set to 2.5 V typical for rising VIN and 1.85 V typical for falling VIN. The hysteresis between rising and falling UVLO threshold ensures proper start-up even with high-impedance sources. Fully functional operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts operation again once the input voltage trips the rising UVLO threshold level.

8.3.2 Enable and Shutdown

The device starts operation when EN pin is set high and the input voltage VIN has tripped the UVLO threshold for rising VIN. It starts switching after the regulator start-up time tStart of typically 50 µs has expired and enters the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating.

EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.3 µA.

In this mode, the high-side and low-side MOSFET switches as well as the entire internal-control circuitry are switched off.

In TPS62120 the internal N-MOSFET at pin SGND is activated and connects SGND to GND.

8.3.3 Power Good Output

The Power Good Output is an open-drain output available in TPS62120. The circuit is active once the device is enabled. It is driven by an internal comparator connected to the FB voltage and internal reference. The PG output provides a high level (open-drain high impedance) once the feedback voltage exceeds typical 95% of its nominal value. The PG output is driven to low level once the feedback voltage falls below typical 90% of its nominal value. The PG output is high (high impedance) with an internal delay of typically 2 µs. A pullup resistor is needed to generate a high level and limit the current into the PG pin to 0.5 mA. The PG pin can be connected through pullup resistors to a voltage up to 5.5 V.

The PG output is pulled low if the device is enabled but the input voltage is below the UVLO threshold or the device is turned into shutdown mode.

8.3.4 SGND Open-Drain Output

This is an NMOS open-drain output with a typical RDS(ON) of 370 Ω and can be used to discharge the output capacitor. The internal NMOS connects SGND pin to GND once the device is in shutdown mode or VIN falls below the UVLO threshold during operation. SGND becomes high impedance once the device is enabled and VIN is above the UVLO threshold. If SGND is connected to the output, the output capacitor is discharged through SGND.

8.3.5 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis.

8.4 Device Functional Modes

8.4.1 Soft Start

The TPS6212x has an internal soft-start circuit which controls the ramp-up of the output voltage and limits the inrush current during start-up. This limits input voltage drop when a battery or a high-impedance power source is connected to the input of the converter.

The soft-start system generates a monotonic ramp up of the output voltage with a ramp of typically 15 mV/µs and reaches an output voltage of 1.8 V in typically 170 µs after EN pin was pulled high. The TPS6212x is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.

During start-up the device can provide an output current of half of the high-side MOSFET switch current limit ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during start-up. In this case the start-up ramp of the output voltage will be slower.

8.4.2 Main Control Loop

The feedback comparator monitors the voltage on the FB pin and compares it to an internal 800-mV reference voltage.

The feedback comparator trips once the FB voltage falls below the reference voltage. A switching pulse is initiated and the high-side MOSFET switch is turned on. The switch remains turned on at least for the minimum on-time TONmin of typical 700 ns until the feedback voltage is above the reference voltage or the inductor current reaches the high-side MOSFET switch current limit ILIMF. Once the high-side MOSFET switch turns off, the low-side MOSFET switch is turned on and the inductor current ramps down. The switch is turned on at least for the minimum off time TOFFmin of typically 60 ns. The low-side MOSFET switch stays turned on until the FB voltage falls below the internal reference and trips the FB comparator again. This will turn on the high-side MOSFET switch for a new switching cycle.

If the feedback voltage stays above the internal reference the low-side MOSFET switch is turned on until the zero current comparator trips and indicates that the inductor current has ramped down to zero. In this case, the load current is much lower than the average inductor current provided during one switching cycle. The regulator turns the low-side and high-side MOSFET switches off (high impedance state) and enters a sleep cycle with reduced quiescent current of typically 10 uA until the output voltage falls below the internal reference voltage and the feedback comparator trips again. This is called PFM mode and the switching frequency depends on the load current, input voltage, output voltage and the external inductor value.

Once the high-side switch current limit comparator has tripped its threshold of ILIMF, the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on until the inductor current has ramped down to zero.

The minimum on time TONmin for a single pulse can be estimated to:

Equation 1. TPS62120 TPS62122 EQ1_Ton_lvsad5.gif

Therefore the peak inductor current in PFM mode is approximately:

Equation 2. TPS62120 TPS62122 EQ2_ILPF_lvsad5.gif

The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 × ILPFMpeak.

With:

TON = High-side MOSFET switch on time [µs]
VIN = Input voltage [V]
VOUT = Output voltage [V]
L = Inductance [µH]
ILPFMpeak = PFM inductor peak current [mA]

The maximum switch frequency can be estimated to:

Equation 3. TPS62120 TPS62122 EQ3_fsw_lvsad5.gif

8.4.3 100% Duty Cycle Low-Dropout Operation

The device will increase the on time of the high-side MOSFET switch once the input voltage comes close to the output voltage in order to keep the output voltage in regulation. This will reduce the switch frequency.

With further decreasing input voltage VIN the high-side MOSFET switch is turned on completely. In this case the converter provides a low input-to-output voltage difference. This is particularly useful in applications with widely variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage span.

The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as:

Equation 4. TPS62120 TPS62122 EQ4_vin_lvsad5.gif

where

  • IOUTmax = maximum output current
  • RDS(ON)max = maximum P-channel switch RDS(ON)
  • RL = DC resistance of the inductor
  • VOUTmax = nominal output voltage plus maximum output voltage tolerance

8.4.4 Short-Circuit Protection

The TPS6212x integrates a high-side MOSFET switch current limit ILIMF to protect the device against short circuit. The current in the high-side MOSFET switch is monitored by current limit comparator and once the current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero current comparator trips and the inductor current has become zero. In this case, the output current is limited to half of the high-side MOSFET switch current limit 0.5 × ILIMF.