SLUSEC8B March   2021  – April 2024 TPS628501 , TPS628502 , TPS628503

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Schematic
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precise Enable (EN)
      2. 8.3.2 COMP/FSET
      3. 8.3.3 MODE / SYNC
      4. 8.3.4 Spread Spectrum Clocking (SSC)
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Power Good Output (PG)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (PWM/PFM)
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
      5. 8.4.5 Foldback Current Limit and Short Circuit Protection
      6. 8.4.6 Output Discharge
      7. 8.4.7 Soft Start
      8. 8.4.8 Input Overvoltage Protection
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Programming the Output Voltage
      2. 9.1.2 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. 9.1.3.1 Input Capacitor
        2. 9.1.3.2 Output Capacitor
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Synchronizing to an External Clock
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS62850x is a family of pin-to-pin 1A, 2A (continuous), and 3A (peak) high efficiency, easy-to-use synchronous step-down DC/DC converters. The devices are based on a peak current mode control topology. Low resistive switches allow up to 2A continuous output current and 3A peak current. The switching frequency is externally adjustable from 1.8MHz to 4MHz and can also be synchronized to an external clock in the same frequency range. In PWM and PFM mode, the TPS62850x automatically enters power save mode at light loads to maintain high efficiency across the whole load range. The TPS62850x provides a 1% output voltage accuracy in PWM mode, which helps design a power supply with high output voltage accuracy, fulfilling tight supply voltage requirements of digital processors and FPGA.

The TPS62850x is available in an 8-pin 1.60mm × 2.10mm SOT583 package.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS62850x DRL (SOT583, 8) 1.60mm × 2.10mm
(1) For more information, see Section 12.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
Device Information
PART NUMBER(1) OUTPUT CURRENT OUTPUT VOLTAGE
TPS628501DRLR 1A Adjustable
Fixed 1.8V
TPS628502DRLR 2A Adjustable
TPS628502ADRLR Fixed 1.2V
TPS628502MDRLR Fixed 1.8V
TPS628503DRLR 3A Adjustable
GUID-20200923-CA0I-5J4H-CKNS-KTXQSSRWHPVT-low.gifSimplified Schematic
GUID-20210228-CA0I-D5XL-LHG9-LBSBPCDWQW3N-low.gifEfficiency versus IOUT, VOUT = 3.3 V