SLVSEI1C June   2019  – October 2020 TPS62864 , TPS62866

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C InterfaceTiming Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 Start-up
      4. 8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Thermal Warning and Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Output Discharge
      3. 8.4.3 Start-up Output Voltage and I2C Slave Address Selection (VSET)
      4. 8.4.4 Select Output Voltage Registers (VID)
      5. 8.4.5 Power Good (PG)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
    6. 8.6 Register Map
      1. 8.6.1 Slave Address Byte
      2. 8.6.2 Register Address Byte
      3. 8.6.3 VOUT Register 1
      4. 8.6.4 VOUT Register 2
      5. 8.6.5 CONTROL Register
      6. 8.6.6 STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 6-A Output Current Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Setting The Output Voltage
          3. 9.2.1.2.3 Output Filter Design
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Smaller Application Solution
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YCG|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.5 Power Good (PG)

The TPS62864 and TPS62864 families provide device options with the VSET/ PG pin, instead of a VSET/VID pin, shown in Figure 9-1.

After the enable delay (tDelay), the device starts to compare the output voltage with the nominal value set by the external resistor or the output voltage registers. Table 8-2 shows the logic level of the PG pin. The pin is driven up to the input voltage for a logic high. The pin is pulled down to GND by the external resistor R1 for a logic low.

For the VSET/ PG option devices, be aware of the following:

  • VSET/ PG can not be connected to GND. A resistor, R1, must be connected between VSET/ PG and GND, for the start-up output voltage and I2C slave address setup.
  • The source current of the VSET/ PG pin is up to 1 mA.
  • VOUT Register 2 is disabled.
  • When the device is in shutdown, the shutdown current is high because of the leakage current through the external resistor, R1, when the VSET/ PG pin is high.

The VSET/ PG has a deglitch time, before the signal goes high or low, during normal operation. For start-up, the VSET/ PG has a delay time of 200 µs after the output voltage reaches the nominal voltage.

Table 8-2 VSET/ PG Pin Logic
DEVICE CONDITIONS PG LOGIC STATUS
HIGH LOW
Enable 0.91 x VOUT_NOM ≤ VVOS ≤ 1.11 x VOUT_NOM √
VVOS < 0.91 x VOUT_NOM or VVOS > 1.11 x VOUT_NOM √
Shutdown EN = Low √
Thermal Shutdown TJ > TJSD √
UVLO 1.8 V < VIN < VUVLO √
Power Supply Removal VIN < 1.8 V undefined