SLVSFU1C April   2023  – October 2024 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone, Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
  10. 9 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor CC
        6. 10.2.2.6 Selecting the Compensation Capacitor CC2
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 10.3.1 Design Requirements For Two Stacked Devices
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1 Selecting the Compensation Resistor
        2. 10.3.2.2 Selecting the Output Capacitors
        3. 10.3.2.3 Selecting the Compensation Capacitor CC
      3. 10.3.3 Application Curves for Two Stacked Devices
    4. 10.4 Typical Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 10.4.1 Design Requirements For Three Stacked Devices
      2. 10.4.2 Detailed Design Procedure
        1. 10.4.2.1 Selecting the Compensation Resistor
        2. 10.4.2.2 Selecting the Output Capacitors
        3. 10.4.2.3 Selecting the Compensation Capacitor CC
      3. 10.4.3 Application Curves for Three Stacked Devices
    5. 10.5 Best Design Practices
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Device Registers

Table 9-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1 DEVICE Registers
AddressAcronymRegister NameSection
0hVSETOutput Voltage SetpointSection 9.1
1hCONTROL1Control 1Section 9.2
2hCONTROL2Control 2Section 9.3
3hCONTROL3Control 3Section 9.4
4hSTATUSStatusSection 9.5

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

9.1 VSET Register (Address = 0h) [Reset = XXh]

VSET is shown in Table 9-3.

Return to the Summary Table.

This register controls the output voltage setpoint

Table 9-3 VSET Register Field Descriptions
BitFieldTypeResetDescription
7-0VSETR/Wxxxxxxxxb Output voltage setpoint (see also the range-setting bits in the CONTROL2 register).
Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV
Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV
Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV
The state of the VSEL pin during power up determines the reset value.

9.2 CONTROL1 Register (Address = 1h) [Reset = X8h]

CONTROL1 is shown in Table 9-4.

Return to the Summary Table.

This register controls various device configuration options

Table 9-4 CONTROL1 Register Field Descriptions
BitFieldTypeResetDescription
7RESETR/W0b Reset device.
0b = No effect
1b = The device is powered down, the pin status is read and all registers are reset to their default value. The device is then powered up again starting with a soft-start cycle.
Reading this bit always returns 0.
6SSCENR/Wxb Spread spectrum clocking enable. Please see the DEVICE OPTIONS table if SSC is enabled by default.
0b = SSC operation disabled
1b = SSC operation enabled
5SWENR/W1b Software enable.
0b = Switching disabled (register values retained)
1b = Switching enabled (without the enable delay)
4FPWMENR/W0b Forced-PWM enable.
0b = Power-save operation enabled
1b = Forced-PWM operation enabled
This bit is logically ORed with the MODE/SYNC pin: If a high level or a synchronization clock is applied to the the MODE/SYNC pin, the device operates in Forced-PWM, regardless of the state of this bit.
3DISCHENR/W1b Output discharge enable.
0b = Output discharge disabled.
1b = Output discharge enabled.
2HICCUPENR/W0b Hiccup operation enable.
0b = Hiccup operation disabled
1b = Hiccup operation enabled. Do not enable Hiccup operation during stacked operation
1-0VRAMPR/W00b Output voltage ramp speed when changing from one output voltage setting to another.
00b = 10 mV/µs
01b = 5 mV/µs
10b = 1.25 mV/µs
11b = 0.5 mV/µs

9.3 CONTROL2 Register (Address = 2h) [Reset = 0Ah]

CONTROL2 is shown in Table 9-5.

Return to the Summary Table.

This register controls various device configuration options

Table 9-5 CONTROL2 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000b Reserved for future use. To ensure compatibility with future device variants, program these bits to 0.
4SYNC_OUT_PHASER/W0b Phase shift of SYNC_OUT with reference to internal clk or external clk applied at MODE/SYNC.
0b = SYNC_OUT is phase shifted by 120°
1b = SYNC_OUT is phase shifted by 180° The phase relation of 180° is only valid from the primary to the first secondary converter.
3-2VRANGER/W10b Output voltage range.
00b = 0.4 V to 0.71875 V in 1.25-mV steps
01b = 0.4 V to 1.0375 V in 2.5-mV steps
10b = 0.4 V to 1.675 V in 5-mV steps
11b = 0.4 V to 1.675 V in 5-mV steps
1-0SSTIMER/W10b Soft-start ramp time.
00b = 0.5 ms
01b = 0.77 ms
10b = 1 ms
11b = 2 ms

9.4 CONTROL3 Register (Address = 3h) [Reset = 0Xh]

CONTROL3 is shown in Table 9-6.

Return to the Summary Table.

This register controls various device configuration options

Table 9-6 CONTROL3 Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W00000b Reserved for future use. To ensure compatibility with future device variants, program these bits to 0.
2DROOPENR/Wxb Droop compensation enable. Please see the DEVICE OPTIONS table if droop compensation is enabled by default.
0b = droop compensation disabled
1b = droop compensation enabled
1SINGLER/W0b Single operation. This bit controls the internal EN pulldown and SYNCOUT functions.
0b = EN pin pulldown and SYNCOUT enabled
1b = EN pin pulldown and SYNCOUT disabled. Do not set during stacked operation
0PGBLNKDVSR/W0b Power-good blanking during DVS.
0b = PG pin reflects the output of the window comparator
1b = PG pin is high impedance during DVS

9.5 STATUS Register (Address = 4h) [Reset = 00h]

STATUS is shown in Table 9-7.

Return to the Summary Table.

This register returns the device status flags

Table 9-7 STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR00b Reserved for future use. To ensure compatibility with future device variants, ignore these bits.
5HICCUPR0b Hiccup. This bit reports whether a hiccup event occurred since the last time the STATUS register was read.
0b = No hiccup event occured
1b = A hiccup event occurred
4ILIMR0b Current limit. This bit reports whether an current limit event occurred since the last time the STATUS register was read.
0b = No current limit event occured
1b = An current limit event occurred
3TWARNR0b Thermal warning. This bit reports whether a thermal warning event occurred since the last time the STATUS register was read.
0b = No thermal warning event occurred
1b = A thermal warning event occurred
2TSHUTR0b Thermal shutdown. This bit reports whether a thermal shutdown event occurred since the last time the STATUS register was read.
0b = No thermal shutdown event occurred
1b = A thermal shutdown event occurred
1PBUVR0b Power-bad undervoltage. This bit reports whether a power-bad event (output voltage too low) occurred since the last time the STATUS register was read.
0b = No power-bad undervoltage event occurred
1b = A power-bad undervoltage event occurred
0PBOVR0b Power-bad overvoltage. This bit reports whether a power-bad event (output voltage too high) occurred since the last time the STATUS register was read.
0b = No power-bad overvoltage event occurred
1b = A power-bad overvoltage event occurred