SLVSFU1D April   2023  – December 2024 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone, Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
  10. 9 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor CC
        6. 10.2.2.6 Selecting the Compensation Capacitor CC2
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 10.3.1 Design Requirements For Two Stacked Devices
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1 Selecting the Compensation Resistor
        2. 10.3.2.2 Selecting the Output Capacitors
        3. 10.3.2.3 Selecting the Compensation Capacitor CC
      3. 10.3.3 Application Curves for Two Stacked Devices
    4. 10.4 Typical Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 10.4.1 Design Requirements For Three Stacked Devices
      2. 10.4.2 Detailed Design Procedure
        1. 10.4.2.1 Selecting the Compensation Resistor
        2. 10.4.2.2 Selecting the Output Capacitors
        3. 10.4.2.3 Selecting the Compensation Capacitor CC
      3. 10.4.3 Application Curves for Three Stacked Devices
    5. 10.5 Best Design Practices
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating junction temperature (TJ = –40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = High, IOUT = 0mA, device not switching; MODE = Low 2.1 3.8 mA
ISD Shutdown current EN = Low, V(SW) = 0 V, max value at TJ = 125°C 18 450 µA
VIT+(UVLO) Positive-going UVLO threshold voltage (VIN) 2.5 2.6 2.7 V
VIT-(UVLO) Negative-going UVLO threshold voltage (VIN) 2.4 2.5 2.6 V
Vhys(UVLO) UVLO hysteresis voltage (VIN) 80 mV
VIT+(OVLO) Positive-going OVLO threshold voltage (VIN) 6.1 6.3 6.5 V
VIT-(OVLO) Negative-going OVLO threshold voltage (VIN) 6.0 6.2 6.4 V
Vhys(OVLO) OVLO hysteresis voltage (VIN) 80 mV
VIT-(POR) Negative-going power-on reset threshold voltage (VIN) 1.4 V
TSD Thermal shutdown threshold temperature TJ rising 170 °C
Thermal shutdown hysteresis 20 °C
TW Thermal warning threshold temperature TJ rising 150 °C
Thermal warning hysteresis 20 °C
CONTROL and INTERFACE
VIT+ Positive-going input threshold voltage (EN) 0.97 1.0 1.03 V
VIT- Negative-going input threshold voltage (EN) 0.87 0.9 0.93 V
Vhys Hysteresis voltage (EN) 95 mV
R(EN) Input resistance to GND (EN) Only active during start-up in stacked operation. 1.4 1.8 3 kΩ
IIH High-level input current (EN) VIH = VIN, internal pulldown resistor disabled 3 µA
IIL Low-level input current (EN) VIL = 0V, internal pulldown resistor disabled –200 nA
VIH High-level input voltage (MODE/SYNC, VSEL, FSEL, SYNC_OUT, PG) 0.8 V
VIH High-level input voltage (SDA, SCL) 0.95 V
VIL Low-level input voltage (MODE/SYNC, VSEL, FSEL, SYNC_OUT, PG) 0.4 V
VIL Low-level input voltage (SDA, SCL) 0.5 V
RIN Input resistance to GND on pins MODE/SYNC, EN and PG 2 3 4 MΩ
VOL Low-level output voltage (SDA) IOL = 9mA 0.4 V
VOL Low-level output voltage (SDA) IOL = 5mA 0.2 V
ILKG Input leakage current into SDA, SCL VOH = 3.3V 200 nA
IIL Low-level input current (MODE/SYNC) VIL = 0V –100 100 nA
IIH High-level input current (MODE/SYNC) VIH = VIN 3 µA
IIL Low-level input current (SYNC_OUT) VIL = 0V –230 nA
IIH High-level input current (SYNC_OUT) VIH = 2V 110 nA
VOL Low-level output voltage (SYNC_OUT) IOL = 1mA 0.3 V
VOH High-level output voltage (SYNC_OUT) IOH = 0.1mA 1.3 2.1 V
td(EN)1 Enable delay time when EN tied to VIN Measured from when EN goes high to when device starts switching, SRVIN = 1V/µs 200 600 µs
td(EN)2 Enable delay time when VIN already applied Measured from when EN goes high to when device starts switching 40 100 µs
td(Ramp) Output voltage ramp time for CONTROL2[1:0] = 00 Measured from when device starts switching to rising edge of PG 0.35 0.5 0.65 ms
Output voltage ramp time for CONTROL2[1:0] = 01 0.54 0.77 1.0 ms
Output voltage ramp time for CONTROL2[1:0] = 10, default 0.7 1 1.3 ms
Output voltage ramp time for CONTROL2[1:0] = 11 1.4 2 2.6 ms
f(SYNC) Synchronization clock frequency range (MODE/SYNC) f(SW)nom = 1.5MHz, D(MODE/SYNC) = 45%...55% 1.2 1.8 MHz
Synchronization clock frequency range (MODE/SYNC) f(SW)nom = 2.25MHz, D(MODE/SYNC) = 45%...55% 1.8 2.7 MHz
Synchronization clock frequency range (MODE/SYNC) f(SW)nom = 2.5MHz, D(MODE/SYNC) = 45%...55% 2 3.0 MHz
f(SYNC) Synchronization clock frequency range (MODE/SYNC) f(SW)nom = 3MHz, D(MODE/SYNC) = 45%...55% 2.4 3.3 MHz
D(MODE/SYNC) Duty cycle of synchronization clock frequency (MODE/SYNC) 45 55 %
Phase shift at SYNC_OUT with reference to internal CLK or external CLK CONTROL2:SYNCH_OUT_PHASE = 0b0 120 °
Phase shift at SYNC_OUT with reference to internal CLK or external CLK CONTROL2:SYNCH_OUT_PHASE = 0b1 180 °
Time to lock to external frequency 50 µs
Resistance on FSEL, VSEL to GND if not tied to GND directly 6.2 kΩ
Resistance on FSEL, VSEL to VIN if not tied to VIN directly 47 kΩ
VT+(UVP) Positive-going power good threshold voltage (output undervoltage) 94 96 98 %
VT-(UVP) Negative-going  power good threshold voltage (output undervoltage) 92 94 96 %
VT+(OVP) Positive-going power good threshold voltage (output overvoltage) 104 106 108 %
VT-(OVP) Negative-going  power good threshold voltage (output overvoltage) 102 104 106 %
VOL Low-level output voltage (PG) IOL = 1mA 0.012 0.3 V
IOH High-level output current (PG) VOH = 5V 3 µA
IIH High-level input current (PG) Device configured as secondary device in stacked operation 3 µA
IIL Low-level input current (PG) Device configured as secondary device in stacked operation –1 µA
td(PG) Deglitch time (PG) High-to-low or low-to-high transition on the PG pin 34 40 46 µs
OUTPUT
ΔVOUT Output voltage accuracy VIN ≥ VOUT + 1.6V, droop compensation disabled –0.8 0.8 %
ΔVOUT Output voltage change from no current to rated current droop compensation enabled ±12 mV
Accuracy of droop compensation voltage; TPS62874-Q1 device in forced PWM mode –3.75 3.75 mV
Accuracy of droop compensation voltage; TPS62875-Q1 device in forced PWM mode –3.5 3.5 mV
Accuracy of droop compensation voltage; TPS62876-Q1 and TPS62877-Q1 device in forced PWM mode –3 3 mV
Line regulation IOUT = 15A, VIN ≥ VOUT + 1.6V 0.02 %/V
IIB Input bias current (GOSNS) EN = High; V(GOSNS) = –100mV to 100mV
 		 –60 3 µA
IIB Input  bias current (VOSNS) V(VOSNS) = 1.675 V, VIN = 6V, droop compensation disabled –5.5 5.5 µA

IIB
 		 Input  bias current (VOSNS) V(VOSNS) = 1.675V, VIN = 6V, droop compensation enabled –13.2 13.2
µA
VICR Input common-mode range (GOSNS) –100 100 mV
RDIS Output discharge resistance VOUT ≤ 1V 2.7 9.2 Ω
fSW Switching frequency (SW) fSW = 1.5MHz, PWM operation  1.35 1.5 1.65 MHz
fSW = 2.25MHz, PWM operation 2.025 2.25 2.475 MHz
fSW = 2.5MHz, PWM operation  2.25 2.5 2.75 MHz
fSW = 3MHz, PWM operation 2.7 3 3.3 MHz
fSSC Modulation frequency fsw/2048 kHz
ΔfSW Switching frequency variation during spread spectrum operation fSW–10% fSW+10%
gm Transconductance of OTA on COMP pin 1.5 mS
τ Emulated current time constant 11.87 12.5 13.2 µs
RDS(ON) High-side FET static on-resistance VIN = 3.3V 3.4 6.4 mΩ
RDS(ON) Low-side FET static on-resistance VIN = 3.3V 1.9 3.6 mΩ
I(SW)(off) SW pin current when HS-FET and LS-FET are off VIN = 6V; V(SW) = 0V, TJ = 25°C –1.5 0.1 µA
SW pin current when HS-FET and LS-FET are off VIN = 6V; V(SW) = 6V, TJ = 25°C  60 130 µA
SW pin current when HS-FET and LS-FET are off V(SW) = 0.4V, current into SW pin 11 3000 µA
ILIM High-side FET forward switch current limit, DC TPS62874-Q1 19 22.5 26 A
ILIM High-side FET forward switch current limit, DC TPS62875-Q1 24 28.5 32 A
ILIM High-side FET forward switch current limit, DC TPS62876-Q1 29 34 39 A
ILIM High-side FET forward switch current limit, DC TPS62877-Q1 34 39 44 A
ILIM Low-side FET forward switch current limit, DC TPS62874-Q1 15 20 24 A
ILIM Low-side FET forward switch current limit, DC TPS62875-Q1 20 24.5 29 A
ILIM Low-side FET forward switch current limit, DC TPS62876-Q1 24.5 29 33 A
ILIM Low-side FET forward switch current limit, DC TPS62877-Q1  29.5 33.5 38 A
ILIM Low-side FET negative current limit, DC –10 A
ton, min Minimum on-time of HS FET VIN = 3.3V 45 53 ns
ton, min Minimum on-time of HS FET VIN = 5V 35 44 ns
toff, min Minimum off-time of HS FET VIN = 5V 70 100 ns
Maximum duty cycle of power stage for TPS62877-Q1   only 45 %