SLVSGG8C November 2023 – October 2024 TPS6287B10 , TPS6287B15 , TPS6287B20 , TPS6287B25 , TPS6287B30
PRODUCTION DATA
During device initialization, a resistor-to-digital converter in the device determines the state of the FSET pin and sets the switching frequency of the DC/DC converter according to Table 8-2.
Resistor at FSET (1%) | Switching Frequency |
---|---|
6.2 kΩ to GND | 1.5 MHz |
Short to GND | 2.25 MHz |
Short to VIN | 2.5 MHz |
47 kΩ to VIN | 3 MHz |
The following figure shows a simplified block diagram of the R2D converter used to detect the state of the FSET pin (an identical circuit detects the state of the VSET pin – see Output Voltage Setpoint).
To detect the most significant bit (MSB), the circuit opens S1 and S2, and the input buffer detects if a high or a low level is connected to the FSET pin.
To detect the least significant bit (LSB):
The propagation delay of the current-sensing comparator limits the minimum on-time of the device. In practice, this means that the maximum switching frequency the device can support decreases with small duty cycles. Figure 6-5 shows the practical operating range of the device with 3.3-V and 5-V supplies.