SLVS844A September   2008  – June 2015 TPS65055

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 DCDC1 Converter
      2. 8.1.2 DCDC2 Converter
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
        1. 8.3.1.1 Dynamic Voltage Positioning
        2. 8.3.1.2 Soft Start
        3. 8.3.1.3 100% Duty Cycle Low Dropout Operation
        4. 8.3.1.4 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Discharge
      4. 8.3.4 RST and DPD
      5. 8.3.5 Short-Circuit Protection
      6. 8.3.6 Thermal Shutdown
      7. 8.3.7 LDO1 to LDO4
        1. 8.3.7.1 Default Voltage Setting for LDOs and DCDC1
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Interface Specification
        1. 8.5.1.1 Serial Interface
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 (DCDC1)
          2. 9.2.2.1.2 Converter 2 (DCDC2)
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

This device integrates two step-down converters and four LDOs, which can be used to power the voltage rails needed by a processor or any other application. The PMIC can be controlled through the ENABLE and MODE pins or sequenced from the VIN using RC delay circuits. In addition to these control pins the device can be controlled by software through I2C interface. Thus, the TPS65055 is very flexible and compatible with many application systems. There is a logic output, RESET, provide the application processor or load a logic signal indicating power good or reset.

9.2 Typical Application

TPS65055 fbd_lvs844.gifFigure 29. Typical Application Schematic

9.2.1 Design Requirements

The TPS6505x devices have only a few design requirements. Use the following parameters for the design examples:

  • 1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground.
  • VCC and VINDCDC1/2 must be connected to the same voltage supply with minimal voltage difference.
  • Input capacitors must be present on the VINDCDC1/2, VIN_LDO1, VINLDO2, and VIN_LDO3/4 supplies if used.
  • Output inductor and capacitors must be used on the outputs of the DC-DC converters if used.
  • Output capacitors must be used on the outputs of the LDOs if used.

9.2.2 Detailed Design Procedure

9.2.2.1 Output Voltage Setting

9.2.2.1.1 Converter 1 (DCDC1)

The output voltage of converter 1 is set by the status of the DEFLDO pins and the I2C compatible interface. See Table 2 for output voltage options.

9.2.2.1.2 Converter 2 (DCDC2)

The output voltage of converter 2 is selected with the DEFDCDC2 pin.

Table 19. Default Fixed Output Voltages

CONVERTER 2 DEFDCDC2 = LOW DEFDCDC2 = HIGH
TPS65055 1.2 V 1 V

9.2.2.2 Output Filter Design (Inductor and Output Capacitor)

9.2.2.2.1 Inductor Selection

The two converters operate typically with 2.2 μH output inductors. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore an inductor with the lowest DC resistance should be selected for highest efficiency. Due to the internal control scheme used, the inductor should have a minimum value of 3.3 μH for an output voltage of 3 V or higher.

Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is recommended because during heavy load transient the inductor current rises above the calculated value.

Equation 4. TPS65055 eq4_lvs844.gif

where

  • f = Switching frequency (2.25 MHz typical)
  • L = Inductor value
  • ΔIL = Peak-to-peak inductor ripple current
  • ILmax = Maximum inductor current

The highest inductor current occurs at maximum Vin.

Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. It must be considered, that the core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.

Refer to Table 20 and the typical applications for possible inductors.

Table 20. Tested Inductors

INDUCTOR TYPE INDUCTOR VALUE SUPPLIER
LPS3010 2.2 μH Coilcraft
VLF3010 2.2 μH TDK
LPS4012 2.2 μH Coilcraft
VLF4012 2.2 μH TDK

9.2.2.2.2 Output Capacitor Selection

The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in the lowest output voltage ripple and are therefore recommended. Refer to Table 21 for recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. For completeness, the RMS ripple current is calculated as:

Equation 5. TPS65055 eq5_lvs844.gif

At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:

Equation 6. TPS65055 eq6_lvs844.gif

Where the highest output voltage ripple occurs at the highest input voltage, Vin.

At light load currents the converters operate in power save mode, and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

9.2.2.2.3 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. The converters require a ceramic input capacitor of 10 μF. The input capacitor can be increased without limit for better input voltage filtering.

Table 21. Possible Capacitors

CAPACITOR VALUE SIZE SUPPLIER TYPE
22 μF 0805 TDK C2012X5R0J226MT Ceramic
22 μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic
10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic
10 μF 0805 TDK C2012X5R0J106M Ceramic
10 μF 0603 Taiyo Yuden JMK107BJ106MA Ceramic

9.2.3 Application Curves

TPS65055 pwm_ltr_lvs844.gifFigure 30. Load Transient Response DCDC1; PWM
TPS65055 pwm2_ltr_lvs844.gifFigure 32. Load Transient Response DCDC2; PWM
TPS65055 pfm_ltr_lvs844.gifFigure 31. Load Transient Response DCDC1; PFM
TPS65055 pfm2_ltr_lvs844.gifFigure 33. Load Transient Response DCDC2; PFM