SLVS844A September   2008  – June 2015 TPS65055

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 DCDC1 Converter
      2. 8.1.2 DCDC2 Converter
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
        1. 8.3.1.1 Dynamic Voltage Positioning
        2. 8.3.1.2 Soft Start
        3. 8.3.1.3 100% Duty Cycle Low Dropout Operation
        4. 8.3.1.4 Undervoltage Lockout
      2. 8.3.2 Enable
      3. 8.3.3 Discharge
      4. 8.3.4 RST and DPD
      5. 8.3.5 Short-Circuit Protection
      6. 8.3.6 Thermal Shutdown
      7. 8.3.7 LDO1 to LDO4
        1. 8.3.7.1 Default Voltage Setting for LDOs and DCDC1
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Interface Specification
        1. 8.5.1.1 Serial Interface
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 (DCDC1)
          2. 9.2.2.1.2 Converter 2 (DCDC2)
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPS65055 device includes two synchronous step-down converters. The converters operate with typically 2.25-MHz fixed-frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converters automatically enter power save mode and operate with PFM (pulse frequency modulation).

During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead time preventing shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch.

The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Therefore smaller input capacitors can be used.

8.1.1 DCDC1 Converter

The converter 1 output voltage is set by the status of the DEFLDO1 and DEFLDO2 pins. The pins can be pulled low, pulled high or left floating to allow 9 different logic states. See the description for the LDOs for further details. With the TPS65055 it is also possible to change the output voltage of converter DCDC1 through the I2C compatible interface. The VDCDC1 pin must be directly connected to VOUT1 and no external resistor network may be connected.

8.1.2 DCDC2 Converter

The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter output voltage can be selected through the DEFDCDC2 pin or the I2C compatible interface.

The DEFDCDC2 pin can either be connected to GND, or to VCC. The converter 2 defaults to 1 V or 1.2 V depending on the logic level of the DEFDCDC2 pin. If DEFDCDC2 is tied to ground, the default is 1.2 V; if it is tied to VCC, the default is 1 V.

With the TPS65055, the voltage can also be changed using the I2C registers – see Application and Implementation for details.

8.2 Functional Block Diagram

TPS65055 fbd_lvs844.gif

8.3 Feature Description

8.3.1 Power Save Mode

Power save mode is enabled per default and can be disabled using the I2C compatible interface. If the load current decreases, the converters enter power save mode operation automatically. During power save mode the converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

To optimize converter efficiency at light load the average current is monitored, and if in PWM mode the inductor current remains below a certain threshold, then power save mode is entered. The typical threshold can be calculated according to:

Equation 1: Average output current threshold to enter PFM mode

Equation 1. TPS65055 eq1_lvs844.gif

Equation 2: Average output current threshold to leave PFM mode

Equation 2. TPS65055 eq2_lvs844.gif

During power save mode, the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch turns on and the converter effectively delivers a constant current as defined above. If the load is below the delivered current, then the output voltage rises until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the skip comparator low (skip comp low) threshold set to 1% below nominal Vout, whereupon power save mode is exited and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency to a minimum achieving the highest converter efficiency. PFM mode operates with very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero.

8.3.1.1 Dynamic Voltage Positioning

This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in power save mode operation when the converter runs in PFM mode. It provides more headroom for both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient behavior.

At light loads, in which the converter operates in PFM mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.

TPS65055 n_ch_swt_lvs844.gifFigure 20. Dynamic Voltage Positioning

8.3.1.2 Soft Start

The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 21.

TPS65055 sft_start_lvs844.gifFigure 21. Soft Start

8.3.1.3 100% Duty Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range, for example. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as:

Equation 3. TPS65055 eq3_lvs844.gif

where

  • Ioutmax = maximum output current plus inductor ripple current.
  • RDSonmax = maximum P-channel switch RDSon.
  • RL = DC resistance of the inductor.
  • Voutmax = nominal output voltage plus maximum output voltage tolerance.

With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency.

In power save mode the converter only operates when the output voltage trips below its nominal output voltage. It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage exceeds the nominal output voltage.

8.3.1.4 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters and LDOs. The undervoltage lockout threshold is typically 1.8 V.

8.3.2 Enable

The DC-DC converters and the LDOs are enabled using external enable pins or enable bits with the I2C compatible interface. The signal of the enable pin and the enable bit are logically XORed to generate the enable signal to the converter or LDO. There is one enable pin and one enable bit for each of the LDOs or DCDC converters, which allows start-up of each converter independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, ENLDO3, or EN_LDO4 are set to high, the corresponding converter starts up with soft start as previously described. The converters and LDOs can also be enabled by setting the enable bits for each of the LDOs or DCDC converters in register REG_CTRL. See the register description for more details.

Disabling the DC-DC converter or LDO forces the device into shutdown with a shutdown quiescent current as defined in Electrical Characteristics. In this mode, the P- and N-Channel MOSFETs are turned off, and the entire internal control circuitry is switched off. For proper operation the enable pins must be terminated and must not be left floating.

8.3.3 Discharge

The TPS65055 contains a comparator that supervises a voltage applied to the threshold pin and drives a open-drain NMOS according to the input level applied at threshold. If the input voltage at the threshold pin is lower than 1 V, the open-drain NMOS at the discharge output is turned on, pulling the pin to GND. This circuitry is functional as soon as the supply voltage at Vcc exceeds the undervoltage lockout threshold. Therefore the TPS65055 has a shutdown current (all DC-DC converters and LDOs are off) of 9 μA to supply bandgap and comparator.

TPS65055 dischg_lvs844.gifFigure 22. Discharge

8.3.4 RST and DPD

The TPS65055 contains two open-drain outputs that are controlled by the I2C compatible interface. The RST and DPD outputs are low (internal NMOS active) per default, once the undervoltage lockout threshold has been exceeded. The status of these outputs can be changed using the REG_CTRL register. See Register Maps for more details.

8.3.5 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.

8.3.6 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds typically 150°C for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P- and N-Channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be used to power an external voltage never heats up the device that high to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turn off simultaneously.

8.3.7 LDO1 to LDO4

The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3, and EN_LDO4 pin EXOR with a bit in register REG_CTRL (Reg#02h).

8.3.7.1 Default Voltage Setting for LDOs and DCDC1

In the TPS65055, the output voltage of the LDOs and of DCDC1 is set using two pins, DEFLDO1 and DEFLDO2. These pins can either be connected to a logic low level, a logic high level, or left floating to define a set of output voltages for LDO1 to LDO4 and DCDC1 according to the following table. The status of the DEFLDO pins is latched after an undervoltage lockout event (UVLO) and sets the registers LDO_CTRL1, LDO_CTRL2, and DEFDCDC1 accordingly. The output voltage of each LDO and DCDC1 can be changed later by reprogramming these registers. See Register Maps for more details.

The TPS65055 default voltage options are adjustable with DEFLDO2 and DEFLDO1 according to the following table:

Table 2. Voltage Table for LDOs and DCDC1

DEFLDO2 DEFLDO1 VLDO1 VLDO2 VLDO3 VLDO4 DCDC1
400mA LDO 400mA LDO 200mA LDO 200mA LDO 600mA
0 0 1.2 V 1.8 V 2.8 V 1.3 V 2.1 V
0 float 1.2 V 1.8 V 2.8 V 2.8 V 1.8 V
0 1 1.2 V 1.8 V 2.8 V 1.3 V 1.8 V
float 0 1.2 V 1.8 V 2.8 V 2.8 V 2.1 V
float float 1.2 V 1.8 V 2.8 V 1.8 V 2.1 V
float 1 1.2 V 1.8 V 2.8 V 2.8 V 1.2 V
1 0 1.2 V 1.8 V 2.8 V 1.0 V 1.9 V
1 float 1.2 V 1.8 V 2.8 V 3.0 V 2.1 V
1 1 1.0 V 1.2 V 1.0 V 1.0 V 1.2 V

8.4 Device Functional Modes

The TPS6505x devices are either in the ON or the OFF mode. The OFF mode is entered when the voltage on VCC is below the UVLO threshold, 1.8 V (typically). Once the voltage at VCC has increased above UVLO, the device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use.

8.5 Programming

8.5.1 Interface Specification

8.5.1.1 Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS65055 has a 7bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65055 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65055 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge – related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65055 device must leave the data line high to enable the master to generate the stop condition.

TPS65055 bit_trans_lvs844.gifFigure 23. Bit Transfer on the Serial Interface
TPS65055 st_stop_lvs844.gifFigure 24. Start and Stop Conditions
TPS65055 srl_if_lvs844.gifFigure 25. Serial Interface Write to the TPS65055 Device
TPS65055 srl_prota_lvs844.gifFigure 26. Serial Interface Read From TPS65055: Protocol A
TPS65055 srl_protb_lvs844.gifFigure 27. Serial Interface Read From TPS65055: Protocol B
TPS65055 srl_tim_lvs844.gifFigure 28. Serial Interface Timing Diagram

Table 3. Serial Interface Timing

MIN MAX UNIT
fMAX Clock frequency 400 kHz
twH(HIGH) Clock high time 600 ns
twL(LOW) Clock low time 1300 ns
tR DATA and CLK rise time 300 ns
tF DATA and CLK fall time 300 ns
th(STA) Hold time (repeated) start condition (after this period the first clock pulse is generated) 600 ns
th(DATA) Setup time for repeated start condition 600 ns
th(DATA) Data input hold time 100 ns
tsu(DATA) Data input setup time 100 ns
tsu(STO) Stop condition setup time 600 ns
t(BUF) Bus free time 1300 ns

8.6 Register Maps

Table 4. PGOODZ. Register Address: 01h (read only)

PGOODZ B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function discharge DVM PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
LDO1
PGOODZ
LDO2
PGOODZ
LDO3
PGOODZ
LDO4
Set by signal PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
LDO1
PGOODZ
LDO2
PGOODZ
LDO3
PGOODZ
LDO4
Default value loaded by: PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
LDO1
PGOOD
LDO2
PGOOD
LDO3
PGOOD
LDO4
Read/write R R R R R R R R
Bit 7 discharge:
0 = Indicates that the comparator input voltage is below the 1 V threshold.
1 = Indicates that the comparator input voltage is above the 1 V threshold.
Bit 6 DVM:
0 = Indicates that the voltage of DCDC2 is not changing.
1 = Indicates that a voltage change of DCDC2 is ongoing.
Bit 5 PGOODZ VDCDC1:
0 = Indicates that the VDCDC1 converter output voltage is within its nominal range.
1 = Indicates that the VDCDC1 converter output voltage is below its target regulation voltage or is disabled.
Bit 4 PGOODZ VDCDC2:
0 = Indicates that the VDCDC2 converter output voltage is within its nominal range.
1 = Indicates that the VDCDC2 converter output voltage is below its target regulation voltage or is disabled.
Bit 3 PGOODZ LDO1:
0 = Indicates that the LDO1 output voltage is within its nominal range.
1 = Indicates that the LDO1 output voltage is below its target regulation voltage or is disabled.
Bit 2 PGOODZ LDO2:
0 = Indicates that the LDO2 output voltage is within its nominal range.
1 = Indicates that LDO2 output voltage is below its target regulation voltage or is disabled.
Bit 1 PGOODZ LDO3:
0 = Indicates that the LDO3 output voltage is within its nominal range.
1 = Indicates that the LDO3 output voltage is below its target regulation voltage or is disabled.
Bit 0 PGOODZ LDO4:
0 = Indicates that the LDO4 output voltage is within its nominal range.
1 = Indicates that the LDO4 output voltage is below its target regulation voltage or is disabled.

Table 5. REG_CTRL. Register Address: 02h (read/write)  Default Value: 00h

REG_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function RST DPD DCDC1 ENABLE DCDC2 ENABLE LDO1 ENABLE LDO2 ENABLE LDO3 ENABLE LDO4
ENABLE
Default 0 0 0 0 0 0 0 0
Set by signal
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R/W R/W R/W R/W R/W R/W R/W R/W

The REG_CTRL register can be used to disable and enable all power supplies through the serial interface. The following tables indicate how the enable pins and the REG_CTRL register are combined.

EN_DCDC1 Pin REG_CTRL<5> DCDC1 Converter
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
EN_DCDC2 pin REG_CTRL<4> DCDC2
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
EN_LDO1 pin REG_CTRL<3> LDO1
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
EN_LDO2 Pin REG_CTRL<2> LDO2
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
EN_LDO3 pin REG_CTRL<1> LDO3
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
EN_LDO4 pin REG_CTRL<0> LDO4
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Disabled
Bit 7 RST:
0 = The internal NMOS is turned on and drives the output to GND.
1 = The internal NMOS is turned off, an external pullup resistor at RST drives the output high.
Bit 6 DPD:
0 = The internal NMOS is turned on and drives the output to GND.
1 = The internal NMOS is turned off, an external pullup resistor at DPD drives the output high.

Table 6. CON_CTRL. Register Address: 03h (read/write)  Default Value: 00h

CON_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function LOW RIPPLE
DCDC1
LOW RIPPLE
DCDC2
FPWM
DCDC1
FPWM
DCDC2
Default 0 0 0 0 0 0 0 1
Default value loaded by: UVLO UVLO UVLO UVLO
Read/write R R R R R/W R/W R/W R/W

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital.

Bit 3 LOW RIPPLE DCDC1:
0 = PFM mode operation optimized for high efficiency for DCDC1.
1 = PFM mode operation optimized for low output voltage ripple for DCDC1.
Bit 2 LOW RIPPLE DCDC2:
0 = PFM mode operation optimized for high efficiency for DCDC2.
1 = PFM mode operation optimized for low output voltage ripple for DCDC2.
Bit 1 FPWM DCDC1:
0 = DCDC1 converter operates in PWM / PFM mode.
1 = DCDC1 converter is forced into fixed frequency PWM mode.
Bit 0 FPWM DCDC2:
0 = DCDC2 converter operates in PWM / PFM mode.
1 = DCDC2 converter is forced into fixed frequency PWM mode.

Table 7. CON_CTRL2. Register Address: 04h (read/write)  Default Value: 0Fh

CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function GO DCDC1 discharge DCDC2 discharge LDO1 discharge LDO2 discharge LDO3 discharge LDO4 discharge
Default 0 0 0 0 1 1 1 1
Default value loaded by: UVLO + DONE* UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W

The CON_CTRL2 register can be used to take control of the inductive converters.

Bit 7 GO:
0 = No change in the output voltage for the DCDC2 converter.
1 = A voltage change for the DCDC2 converter is ongoing. The voltage is changed to the value written into the DEFDCDC2_HIGH or DEFDCDC2_LOW register with the slew rate defined in DEFSLEW. This bit is automatically set and cleared internally. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC2 output voltage is actually in regulation at the desired voltage. The GO bit is also high when a voltage change is ongoing caused by changing the logic level of the DEFDCDC2 pin.
Bit 5–0 0 = The output capacitor of the associated converter or LDO is not actively discharged when the converter or LDO is disabled.
1 = The output capacitor of the associated converter or LDO is actively discharged when the converter or LDO is disabled. This decreases the fall time of the output voltage at light load.

Table 8. DEFDCDC2_LOW. Register Address: 05h (read/write)  Default Value: 10h

DEFDCDC2_LOW B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function DCDC2[5] DCDC2[4] DCDC2[3] DCDC2[2] DCDC2[1] DCDC2[0]
Default 0 0 0 1 0 0 0 0
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W

Table 9. DEFDCDC2_HIGH. Register Address: 06h (read/write)  Default Value: 08h

DEFDCDC2_HIGH B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function DCDC2[5] DCDC2[4] DCDC2[3] DCDC2[2] DCDC2[1] DCDC2[0]
Default 0 0 0 0 1 0 0 0
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W

The output voltage for DCDC2 is switched between the value defined in DEFDCDC2_LOW and DEFDCDC2_HIGH depending on the status of the DEFDCDC2 pin. IF DEFDCDC2 is low, the value in DEFDCDC2_LOW is selected, if DEFDCDC2 = high, the value in DEFDCDC2_HIGH is selected.

Table 10. Voltage Table for DCDC2

OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0
0 0.800 0 0 0 0 0 0
1 0.825 0 0 0 0 0 1
2 0.850 0 0 0 0 1 0
3 0.875 0 0 0 0 1 1
4 0.900 0 0 0 1 0 0
5 0.925 0 0 0 1 0 1
6 0.950 0 0 0 1 1 0
7 0.975 0 0 0 1 1 1
8 1.000 0 0 1 0 0 0
9 1.025 0 0 1 0 0 1
10 1.050 0 0 1 0 1 0
11 1.075 0 0 1 0 1 1
12 1.100 0 0 1 1 0 0
13 1.125 0 0 1 1 0 1
14 1.150 0 0 1 1 1 0
15 1.175 0 0 1 1 1 1
16 1.200 0 1 0 0 0 0
17 1.225 0 1 0 0 0 1
18 1.250 0 1 0 0 1 0
19 1.275 0 1 0 0 1 1
20 1.300 0 1 0 1 0 0
21 1.325 0 1 0 1 0 1
22 1.350 0 1 0 1 1 0
23 1.375 0 1 0 1 1 1
24 1.400 0 1 1 0 0 0
25 1.425 0 1 1 0 0 1
26 1.450 0 1 1 0 1 0
27 1.475 0 1 1 0 1 1
28 1.500 0 1 1 1 0 0
29 1.525 0 1 1 1 0 1
30 1.550 0 1 1 1 1 0
31 1.575 0 1 1 1 1 1

Table 11. Voltage Table for DCDC2

OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0
0 1.600 1 0 0 0 0 0
1 1.650 1 0 0 0 0 1
2 1.700 1 0 0 0 1 0
3 1.750 1 0 0 0 1 1
4 1.800 1 0 0 1 0 0
5 1.850 1 0 0 1 0 1
6 1.900 1 0 0 1 1 0
7 1.950 1 0 0 1 1 1
8 2.000 1 0 1 0 0 0
9 2.050 1 0 1 0 0 1
10 2.100 1 0 1 0 1 0
11 2.150 1 0 1 0 1 1
12 2.200 1 0 1 1 0 0
13 2.250 1 0 1 1 0 1
14 2.300 1 0 1 1 1 0
15 2.350 1 0 1 1 1 1
16 2.400 1 1 0 0 0 0
17 2.450 1 1 0 0 0 1
18 2.500 1 1 0 0 1 0
19 2.550 1 1 0 0 1 1
20 2.600 1 1 0 1 0 0
21 2.650 1 1 0 1 0 1
22 2.700 1 1 0 1 1 0
23 2.750 1 1 0 1 1 1
24 2.800 1 1 1 0 0 0
25 2.850 1 1 1 0 0 1
26 2.900 1 1 1 0 1 0
27 2.950 1 1 1 0 1 1
28 3.000 1 1 1 1 0 0
29 3.100 1 1 1 1 0 1
30 3.200 1 1 1 1 1 0
31 3.300 1 1 1 1 1 1

Table 12. DEFSLEW. Register Address: 07h (read/write)  Default Value: 06h

DEFSLEW B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function SLEW2 SLEW1 SLEW0
Default 0 0 0 0 0 1 1 0
Default value loaded by: UVLO UVLO UVLO
Read/write R R R R R R/W R/W R/W
SLEW2 SLEW1 SLEW0 VDCDC3 SLEW RATE
0 0 0 0.11 mV/μs
0 0 1 0.22 mV/μs
0 1 0 0.45 mV/μs
0 1 1 0.9 mV/μs
1 0 0 1.8 mV/μs
1 0 1 3.6 mV/μs
1 1 0 7.2 mV/μs
1 1 1 Immediate

Table 13. LDO_CTRL1. Register Address: 08h (r/w)  Default Value: Set With DEFLDO1, DEFLDO2

LDO_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function LDO2[2] LDO2[1] LDO2[0] LDO1[2] LDO1[1] LDO1[0]
Default 0 DEFLDO pins DEFLDO pins DEFLDO pins 0 DEFLDO pins DEFLDO pins DEFLDO pins
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R/W R/W R/W R R/W R/W R/W

The LDO_CTRLx registers can be used to set the output voltages of LDO1 to LDO4. The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

LDO2[2] LDO2[1] LDO2[0] LDO2
OUTPUT VOLTAGE
0 0 0 1.2 V
0 0 1 1.3 V
0 1 0 1.8 V
0 1 1 2.6 V
1 0 0 2.7 V
1 0 1 2.8 V
1 1 0 2.9 V
1 1 1 3 V
LDO1[2] LDO1[1] LDO1[0] LDO1
OUTPUT VOLTAGE
0 0 0 0.8 V
0 0 1 1 V
0 1 0 1.2 V
0 1 1 1.5 V
1 0 0 1.8 V
1 0 1 2.1 V
1 1 0 2.5 V
1 1 1 2.8 V

Table 14. LDO_CTRL2. Register Address: 09h (r/w)  Default Value: Set With DEFLDO1, DEFLDO2

LDO_CTRL B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function LDO4[2] LDO4[1] LDO4[0] LDO3[2] LDO3[1] LDO3[0]
Default 0 DEFLDO pins DEFLDO pins DEFLDO pins 0 DEFLDO pins DEFLDO pins DEFLDO pins
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R/W R/W R/W R R/W R/W R/W

The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

LDO4[2] LDO4[1] LDO4[0] LDO4
OUTPUT VOLTAGE
0 0 0 1 V
0 0 1 1.2 V
0 1 0 1.3 V
0 1 1 1.8 V
1 0 0 2.6 V
1 0 1 2.7 V
1 1 0 2.8 V
1 1 1 3 V
LDO3[2] LDO3[1] LDO3[0] LDO3
OUTPUT VOLTAGE
0 0 0 0.8 V
0 0 1 1 V
0 1 0 1.2 V
0 1 1 1.5 V
1 0 0 1.8 V
1 0 1 2.1 V
1 1 0 2.5 V
1 1 1 2.8 V

Table 15. DEFDCDC1. Register Address: 0Ah (r/w)  Default Value: Set With DEFLDO1, DEFLDO2

DEFDCDC1 B7 B6 B5 B4 B3 B2 B1 BO
Bit name and function DCDC1[5] DCDC1[4] DCDC1[3] DCDC1[2] DCDC1[1] DCDC1[0]
Default 0 0 DEFLDO pins DEFLDO pins DEFLDO pins DEFLDO pins DEFLDO pins DEFLDO pins
Default value loaded by: UVLO UVLO UVLO UVLO UVLO UVLO UVLO
Read/write R R R/W R/W R/W R/W R/W R/W

Per default the DCDC1 converter is internally adjustable and the default output voltage for DCDC1 (bits B0 to B5) depends on the status of the DEFLDO pins – see Default Voltage Setting for LDOs and DCDC1. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

DCDC1 voltage is listed in Table 16.

Table 16. Voltage Table for DCDC1

OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0
0 0.800 0 0 0 0 0 0
1 0.825 0 0 0 0 0 1
2 0.850 0 0 0 0 1 0
3 0.875 0 0 0 0 1 1
4 0.900 0 0 0 1 0 0
5 0.925 0 0 0 1 0 1
6 0.950 0 0 0 1 1 0
7 0.975 0 0 0 1 1 1
8 1.000 0 0 1 0 0 0
9 1.025 0 0 1 0 0 1
10 1.050 0 0 1 0 1 0
11 1.075 0 0 1 0 1 1
12 1.100 0 0 1 1 0 0
13 1.125 0 0 1 1 0 1
14 1.150 0 0 1 1 1 0
15 1.175 0 0 1 1 1 1
16 1.200 0 1 0 0 0 0
17 1.225 0 1 0 0 0 1
18 1.250 0 1 0 0 1 0
19 1.275 0 1 0 0 1 1
20 1.300 0 1 0 1 0 0
21 1.325 0 1 0 1 0 1
22 1.350 0 1 0 1 1 0
23 1.375 0 1 0 1 1 1
24 1.400 0 1 1 0 0 0
25 1.425 0 1 1 0 0 1
26 1.450 0 1 1 0 1 0
27 1.475 0 1 1 0 1 1
28 1.500 0 1 1 1 0 0
29 1.525 0 1 1 1 0 1
30 1.550 0 1 1 1 1 0
31 1.575 0 1 1 1 1 1

Table 17. Voltage Table for DCDC1

OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0
0 1.600 1 0 0 0 0 0
1 1.650 1 0 0 0 0 1
2 1.700 1 0 0 0 1 0
3 1.750 1 0 0 0 1 1
4 1.800 1 0 0 1 0 0
5 1.850 1 0 0 1 0 1
6 1.900 1 0 0 1 1 0
7 1.950 1 0 0 1 1 1
8 2.000 1 0 1 0 0 0
9 2.050 1 0 1 0 0 1
10 2.100 1 0 1 0 1 0
11 2.150 1 0 1 0 1 1
12 2.200 1 0 1 1 0 0
13 2.250 1 0 1 1 0 1
14 2.300 1 0 1 1 1 0
15 2.350 1 0 1 1 1 1
16 2.400 1 1 0 0 0 0
17 2.450 1 1 0 0 0 1
18 2.500 1 1 0 0 1 0
19 2.550 1 1 0 0 1 1
20 2.600 1 1 0 1 0 0
21 2.650 1 1 0 1 0 1
22 2.700 1 1 0 1 1 0
23 2.750 1 1 0 1 1 1
24 2.800 1 1 1 0 0 0
25 2.850 1 1 1 0 0 1
26 2.900 1 1 1 0 1 0
27 2.950 1 1 1 0 1 1
28 3.000 1 1 1 1 0 0
29 3.100 1 1 1 1 0 1
30 3.200 1 1 1 1 1 0
31 3.300 1 1 1 1 1 1

Table 18. VERSION. Register Address: 0Bh (r)

VERSION B7 B6 B5 B4 B3 B2 B1 BO
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R