8.1.1 DCDC1 Converter

The converter 1 output voltage is set by the status of the DEFLDO1 and DEFLDO2 pins. The pins can be pulled low, pulled high or left floating to allow 9 different logic states. See the description for the LDOs for further details. With the TPS65055 it is also possible to change the output voltage of converter DCDC1 through the I²C compatible interface. The VDCDC1 pin must be directly connected to V_OUT1 and no external resistor network may be connected.

8.1.2 DCDC2 Converter

The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter output voltage can be selected through the DEFDCDC2 pin or the I²C compatible interface.

The DEFDCDC2 pin can either be connected to GND, or to V_CC. The converter 2 defaults to 1 V or 1.2 V depending on the logic level of the DEFDCDC2 pin. If DEFDCDC2 is tied to ground, the default is 1.2 V; if it is tied to V_CC, the default is 1 V.

With the TPS65055, the voltage can also be changed using the I²C registers – see Application and Implementation for details.

8.3.1 Power Save Mode

Power save mode is enabled per default and can be disabled using the I²C compatible interface. If the load current decreases, the converters enter power save mode operation automatically. During power save mode the converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

To optimize converter efficiency at light load the average current is monitored, and if in PWM mode the inductor current remains below a certain threshold, then power save mode is entered. The typical threshold can be calculated according to:

Equation 1: Average output current threshold to enter PFM mode

Equation 1.

Equation 2: Average output current threshold to leave PFM mode

Equation 2.

During power save mode, the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp) of V_OUTnominal +1%, the P-channel switch turns on and the converter effectively delivers a constant current as defined above. If the load is below the delivered current, then the output voltage rises until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the skip comparator low (skip comp low) threshold set to 1% below nominal V_out, whereupon power save mode is exited and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency to a minimum achieving the highest converter efficiency. PFM mode operates with very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero.

8.3.1.1 Dynamic Voltage Positioning

This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in power save mode operation when the converter runs in PFM mode. It provides more headroom for both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient behavior.

At light loads, in which the converter operates in PFM mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch.

Figure 20. Dynamic Voltage Positioning

8.3.1.2 Soft Start

The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 21.

Figure 21. Soft Start

8.3.1.3 100% Duty Cycle Low Dropout Operation

The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range, for example. The minimum input voltage to maintain regulation depends on the load current and output voltage and can be calculated as:

Equation 3.

where

• Iout_max = maximum output current plus inductor ripple current.
• RDSon_max = maximum P-channel switch RDSon.
• R_L = DC resistance of the inductor.
• Vout_max = nominal output voltage plus maximum output voltage tolerance.

With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency.

In power save mode the converter only operates when the output voltage trips below its nominal output voltage. It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage exceeds the nominal output voltage.

8.3.2 Enable

The DC-DC converters and the LDOs are enabled using external enable pins or enable bits with the I²C compatible interface. The signal of the enable pin and the enable bit are logically XORed to generate the enable signal to the converter or LDO. There is one enable pin and one enable bit for each of the LDOs or DCDC converters, which allows start-up of each converter independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, ENLDO3, or EN_LDO4 are set to high, the corresponding converter starts up with soft start as previously described. The converters and LDOs can also be enabled by setting the enable bits for each of the LDOs or DCDC converters in register REG_CTRL. See the register description for more details.

Disabling the DC-DC converter or LDO forces the device into shutdown with a shutdown quiescent current as defined in Electrical Characteristics. In this mode, the P- and N-Channel MOSFETs are turned off, and the entire internal control circuitry is switched off. For proper operation the enable pins must be terminated and must not be left floating.

8.3.3 Discharge

The TPS65055 contains a comparator that supervises a voltage applied to the threshold pin and drives a open-drain NMOS according to the input level applied at threshold. If the input voltage at the threshold pin is lower than 1 V, the open-drain NMOS at the discharge output is turned on, pulling the pin to GND. This circuitry is functional as soon as the supply voltage at Vcc exceeds the undervoltage lockout threshold. Therefore the TPS65055 has a shutdown current (all DC-DC converters and LDOs are off) of 9 μA to supply bandgap and comparator.

Figure 22. Discharge

8.3.4 RST and DPD

The TPS65055 contains two open-drain outputs that are controlled by the I²C compatible interface. The RST and DPD outputs are low (internal NMOS active) per default, once the undervoltage lockout threshold has been exceeded. The status of these outputs can be changed using the REG_CTRL register. See Register Maps for more details.

8.3.5 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.

8.3.6 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds typically 150°C for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P- and N-Channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be used to power an external voltage never heats up the device that high to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turn off simultaneously.

8.3.7 LDO1 to LDO4

The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3, and EN_LDO4 pin EXOR with a bit in register REG_CTRL (Reg#02h).

8.5.1 Interface Specification

8.5.1.1 Serial Interface

The serial interface is compatible with the standard and fast mode I²C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as V_CC remains above the UVLO threshold. The TPS65055 has a 7bit address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from register addresses not listed in this section result in 00h being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65055 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65055 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge – related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65055 device must leave the data line high to enable the master to generate the stop condition.

Figure 23. Bit Transfer on the Serial Interface

Figure 24. Start and Stop Conditions

Figure 25. Serial Interface Write to the TPS65055 Device

Figure 26. Serial Interface Read From TPS65055: Protocol A

Figure 27. Serial Interface Read From TPS65055: Protocol B

Figure 28. Serial Interface Timing Diagram

Table 3. Serial Interface Timing

		MIN	MAX	UNIT
fMAX	Clock frequency		400	kHz
twH(HIGH)	Clock high time	600		ns
twL(LOW)	Clock low time	1300		ns
tR	DATA and CLK rise time		300	ns
tF	DATA and CLK fall time		300	ns
th(STA)	Hold time (repeated) start condition (after this period the first clock pulse is generated)	600		ns
th(DATA)	Setup time for repeated start condition	600		ns
th(DATA)	Data input hold time	100		ns
tsu(DATA)	Data input setup time	100		ns
tsu(STO)	Stop condition setup time	600		ns
t(BUF)	Bus free time	1300		ns

Table 4. PGOODZ. Register Address: 01h (read only)

Table 5. REG_CTRL. Register Address: 02h (read/write)  Default Value: 00h

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital.

The CON_CTRL2 register can be used to take control of the inductive converters.

The output voltage for DCDC2 is switched between the value defined in DEFDCDC2_LOW and DEFDCDC2_HIGH depending on the status of the DEFDCDC2 pin. IF DEFDCDC2 is low, the value in DEFDCDC2_LOW is selected, if DEFDCDC2 = high, the value in DEFDCDC2_HIGH is selected.

The LDO_CTRLx registers can be used to set the output voltages of LDO1 to LDO4. The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

Per default the DCDC1 converter is internally adjustable and the default output voltage for DCDC1 (bits B0 to B5) depends on the status of the DEFLDO pins – see Default Voltage Setting for LDOs and DCDC1. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

DCDC1 voltage is listed in Table 16.