SWCS133E September   2015  – October 2024 TPS65094

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
    1. 4.1 OTP Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 6.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Good (PGOOD)
      2. 7.3.2 Register Reset Conditions
      3. 7.3.3 SMPS Voltage Regulators
        1. 7.3.3.1 Controller Overview
        2. 7.3.3.2 Converter Overview
        3. 7.3.3.3 DVS
        4. 7.3.3.4 Current Limit
      4. 7.3.4 LDOs and Load Switches
        1. 7.3.4.1 VTT LDO
        2. 7.3.4.2 LDOA1–LDOA3
        3. 7.3.4.3 Load Switches
      5. 7.3.5 Power Sequencing and VR Control
        1. 7.3.5.1 Cold Boot
        2. 7.3.5.2 Cold OFF
        3. 7.3.5.3 Connected Standby Entry and Exit
        4. 7.3.5.4 S0 to S3 Entry and Exit
        5. 7.3.5.5 S0 to S4/5 Entry and Exit
        6. 7.3.5.6 Emergency Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 F/S-Mode Protocol
    6. 7.6 Register Maps
      1. 7.6.1  55
      2. 7.6.2  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
      3. 7.6.3  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
      4. 7.6.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.6.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.6.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.6.7  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.6.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
      9. 7.6.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
      10. 7.6.10 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
      11. 7.6.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
      12. 7.6.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
      13. 7.6.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
      14. 7.6.14 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
      15. 7.6.15 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
      16. 7.6.16 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
      17. 7.6.17 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
      18. 7.6.18 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      19. 7.6.19 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
      20. 7.6.20 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
      21. 7.6.21 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
      22. 7.6.22 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
      23. 7.6.23 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
      24. 7.6.24 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
      25. 7.6.25 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
      26. 7.6.26 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
      27. 7.6.27 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
      28. 7.6.28 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
      29. 7.6.29 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
      30. 7.6.30 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
      31. 7.6.31 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
      32. 7.6.32 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      33. 7.6.33 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. 7.6.33.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
        2. 7.6.33.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      34. 7.6.34 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Controller Design Procedure
          1. 8.1.2.1.1 Selecting the Output Capacitors
          2. 8.1.2.1.2 Selecting the Inductor
          3. 8.1.2.1.3 Selecting the FETs
          4. 8.1.2.1.4 Bootstrap Capacitor
          5. 8.1.2.1.5 Selecting the Input Capacitors
            1. 8.1.2.1.5.1 Setting the Current Limit
        2. 8.1.2.2 Converter Design Procedure
          1. 8.1.2.2.1 Selecting the Inductor
          2. 8.1.2.2.2 Selecting the Output Capacitors
          3. 8.1.2.2.3 Selecting the Input Capacitors
        3. 8.1.2.3 LDO Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Specific Application for TPS650944
    3. 8.3 Dos and Don'ts
    4.     Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from Revision D (May 2019) to Revision E (October 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated revision history dates to reflect actual past releasesGo
  • Updated the first page content to the latest technical and formatting standardsGo
  • Added note about Forced PWM Mode to Summary of TPS65094x OTP Differences tableGo

Changes from Revision C (February 2019) to Revision D (May 2019)

  • Added "TPS650947" column to Summary of TPS65094x OTP Differences tableGo
  • Changed TPS650945 DEVICEID register to "Dh" and TPS650944 DEVICEID register to "Ch" in Summary of TPS65094x OTP Differences tableGo
  • Added TPS650947 settings to Section 7.6 Go

Changes from Revision B (February 2017) to Revision C (February 2019)

  • Added "BUCK3-5 Mode" row and "TPS650945" column to Summary of TPS65094x OTP Differences tableGo
  • Changed VSYS to PVIN in the efficiency graphs for BUCK3, BUCK4, and BUCK5 in the Typical Characteristics sectionGo
  • Added to the description of the deassertion condition that causes an emergency shutdown in the Emergency Shutdown sectionGo
  • Added TPS650945 settings to Section 7.6 Go
  • Changed OCP event to power fault event in the OCP bit description in the OFFONSRC Register Field Descriptions tableGo
  • Changed second reference of TPS650940 to TPS650944 for the bit reset values in the LDOA2VID Register Field Descriptions and LDOA3VID Register Field Descriptions tablesGo
  • Changed the bit values of the LDOA3_SLPVID[0] and LDOA3_VID[0] bits in the LDOA3VID Register figureGo

Changes from Revision A (June 2016) to Revision B (February 2017)

  • Changed Features to show currents described are not device limitsGo
  • Changed the values for LX3, LX4, LX5 from –1 V and 7 V to –2 V and 8 V in the Absolute Maximum Ratings tableGo
  • Changed the reset value of the LDOA2 VID register (LDOA2VID) to OTP dependentGo

Changes from Revision * (August 2015) to Revision A (June 2016)

  • Released full data sheet as SWCS133A version from SWCS130B versionGo
  • Changed device status to PROD_DATAGo
  • Changed VIN recommended minimum Go
  • Changed Features to improve description of converters Go
  • Changed Features to up to 400 mA of output current for load switchesGo
  • Changed PROCHOTB to PROCHOT throughout the documentGo
  • Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 6.1 Go
  • Deleted nominal value from PVINVTT in Section 6.3, Recommended Operating Conditions Go
  • Deleted (nu = symbol for efficiency) Go
  • Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 6.7 Go
  • Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 6.7 Go
  • Changed BUCK2 DC output voltage to show full range and be consistent in Section 6.7 Go
  • Changed set condition for BUCK6 for VOUT range in Section 6.7 to match BUCK1 and BUCK2 Go
  • Updated formatting and added new OTP information for BUCK6 in Section 6.7 Go
  • Updated formatting for BUCK3 DC output voltage in Section 6.8 Go
  • Changed DC output voltage formatting for BUCK4 in Section 6.8 Go
  • Changed maximum IOUT value for BUCK4 in Section 6.8 to match device capabilities Go
  • Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 6.9 for new OTPs Go
  • Changed test conditions for VTT LDO overcurrent protection in Section 6.9 Go
  • Changed Section 6.10 to show SWB1_2 RDSON is specified per output Go
  • Changed fSW values in Section 6.15 to provide more values Go
  • Changed current to 1.9 A to match SoC requirements in Table 7-1 Go
  • Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 7-1 Go
  • Changed table note to include additional DDR types in Table 7-1 Go
  • Changed PMIC Functional Block Diagram to match specifications table Go
  • Changed PROCHOTB to PROCHOT in the Apollo Lake Power Map Go
  • Changed current ratings in Apollo Lake Power Map Go
  • Deleted SWBx PG from PG of PCH_PWROK in Power Good SummaryGo
  • Deleted SWBx PG from PG of PCH_PWROK in Power Good SummaryGo
  • Changed BUCK1–2 to all BUCKs and LDOAs in Section 7.3.3.3 Go
  • Added Table 7-5 and Table 7-6 to Section 7.3.4.2 Go
  • Added more DDR values to the table note in Table 7-7 Go
  • Changed Section 7.3.5 to include LDOA1 and reset informationGo
  • Changed Section 7.6 to include multiple DDRsGo
  • Changed Figure 7-7 and Figure 7-8 to include alternate SWB1_2 TimingGo
  • Changed SWB1_2 from: V3P3A to: V1P8U in Table 7-10 Go
  • Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 7-11 Go
  • Updated Figure 7-10 to include alternate SWB1_2 TimingGo
  • Changed Section 7.3.5.5 to include alternate SWB1_2 TimingGo
  • Changed Section 7.3.5.6 to include THERMTRIPB Go
  • Added the TPS65094x family OTP values to Section 7.6 Go
  • Replaced VID values with link to full VID table in Table 7-18 and Table 7-19 Go
  • Updated naming of bits in the TEMPHOT registerGo