The TPS65132 family is designed to supply positive/negative driven applications. The device uses a single inductor scheme for both outputs to provide the user smallest solution size, a small bill-of-material as well as high efficiency. The devices offer best line and load regulation at low noise. With its input voltage range of 2.5 V to 5.5 V, it is optimized for products powered by single-cell batteries (Li-Ion, Ni-Li, Li-Polymer) and fixed 3.3-V and 5-V rails. The TPS656132 family provides 80 mA and 150 mA output current options with programmability to 40 mA. There are both CSP and QFN package options available.
PART NUMBER | PACKAGE | BODY SIZE (NOM.) |
---|---|---|
TPS65132 -B, -L, -T, -S |
DSBGA (15) | 2.11 mm × 1.51 mm |
TPS65132W | WQFN (20) | 4.00 mm × 3.00 mm |
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Changes from G Revision (August 2015) to H Revision
Changes from F Revision (June 2015) to G Revision
Changes from E Revision (November 2014) to F Revision
Changes from D Revision (October 2014) to E Revision
Changes from C Revision (July 2014) to D Revision
Changes from B Revision (May 2014) to C Revision
Changes from A Revision (August 2013) to B Revision
Changes from * Revision (June 2013) to A Revision
PART NUMBER(1) | PRE-PROGRAMMED OUTPUT VOLTAGES |
IOUT_MAX | PRE-PROGRAMMED IOUT |
PRE-PROGRAMMED ACTIVE DISCHARGE(2) |
STARTUP TIME VPOS / VNEG (4) |
ISD | PACKAGE |
---|---|---|---|---|---|---|---|
TPS65132A | VPOS = 5.4 V VNEG = –5.4 V |
80 mA | 40 mA | VPOS / VNEG | FAST | 30 µA | CSP |
TPS65132A0 | VPOS = 5.0 V VNEG = –5.0 V |
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TPS65132B | VPOS = 5.4 V VNEG = –5.4V |
80 mA | 40 mA | VPOS / VNEG | FAST | 130 nA | CSP |
TPS65132B0 | VPOS = 5.0 V VNEG = –5.0 V |
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TPS65132B5 | VPOS = 5.5 V VNEG = –5.5 V |
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TPS65132B2 | VPOS = 5.2 V VNEG = –5.2 V |
80 mA | 40 mA | VPOS / VNEG | SLOW | 130 nA | CSP |
TPS65132L | VPOS = 5.4 V VNEG = –5.4 V |
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TPS65132L0 | VPOS = 5.0 V VNEG = –5.0 V |
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TPS65132L1 (3) | VPOS = 5.1 V VNEG = –5.1 V |
80 mA | 40 mA | VPOS / VNEG | SLOW | 130 nA | CSP |
TPS65132T6 | VPOS = 5.6 V VNEG = –5.6 V |
80 mA | 80 mA | VPOS / VNEG | SLOW | 130 nA | CSP |
TPS65132S | VPOS = 5.4 V VNEG = –5.4 V |
150 mA | 80 mA | VPOS / VNEG | SLOW | 130 nA | CSP |
TPS65132W | VPOS = 5.4 V VNEG = –5.4 V |
80 mA | 80 mA | VPOS / VNEG | SLOW | 130 nA | QFN |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | Ax, Bx, Lx, Tx | Sx | ||
AGND | D2 | D2 | — | Analog ground |
CFLY1 | C3 | C3 | I/O | Negative charge pump flying capacitor pin |
CFLY2 | A3 | A3 | I/O | Negative charge pump flying capacitor pin |
EN | — | B1 | Enable pin (sequence programmed) | |
ENN | A1 | — | I | Enable pin for VNEG rail |
ENP | B1 | B1 | I | Enable pin for VPOS rail |
OUTP | E3 | E3 | O | Output pin of the LDO (VPOS) |
OUTN | A2 | A2 | O | Output pin of the negative charge pump (VNEG) |
PGND | B3 | B3 | — | Power ground |
E1 | E1 | |||
REG | D3 | D3 | I/O | Boost converter output pin |
E2 | E2 | |||
SCL | B2 | B2 | I/O | I²C interface clock signal pin |
SDA | C2 | C2 | I/O | I²C interface data signal pin |
SW | D1 | D1 | I/O | Switch pin of the boost converter |
SYNC | — | A1 | I | Synchronization pin. 150 mA current enabled if this pin is pulled HIGH. |
VIN | C1 | C1 | I | Input voltage supply pin |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | Wx | ||
AGND | 3 | — | Analog ground |
17 | |||
CFLY1 | 13 | I/O | Negative charge pump flying capacitor pin |
CFLY2 | 10 | I/O | Negative charge pump flying capacitor pin |
ENN | 6 | I | Enable pin for VNEG rail |
ENP | 5 | I | Enable pin for VPOS rail |
OUTP | 16 | O | Output pin of the LDO (VPOS) |
15 | |||
OUTN | 9 | O | Output pin of the negative charge pump (VNEG) |
PGND | 1 | — | Power ground |
2 | |||
11 | |||
12 | |||
REG | 14 | I/O | Boost converter output pin |
18 | |||
SCL | 8 | I/O | I²C interface clock signal pin |
SDA | 7 | I/O | I²C interface data signal pin |
SW | 19 | I/O | Switch pin of the boost converter |
20 | |||
VIN | 4 | I | Input voltage supply pin |
VALUE | UNIT | |||
---|---|---|---|---|
MIN | MAX | |||
Voltage range | CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC, VIN | –0.3 | 7 | V |
CFLY2, OUTN | –7 | 0.3 | V | |
Continuous total power dissipation | See Thermal Information | |||
Operating junction temperature, TJ | –40 | 150 | °C | |
Operating ambient temperature, TA | –40 | 85 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
Charged device model (CDM) per JEDEC specification JESD22-C101, all pins(2) | ±500 | V |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage range | 2.5 | 5.5 | V | |
L | Inductor(1) | 2.2 | 4.7 | µH | |
CIN | Input capacitor(1)(2) | 4.7 | µF | ||
CFLY | Flying capacitor(1)(2) | 2.2 | µF | ||
COUTP, COUTN, CREG | Output capacitors(1)(2) | 4.7 | µF | ||
TA | Operating ambient temperature | –40 | 85 | °C | |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS65132 | TPS65132 | UNIT | |
---|---|---|---|---|
YFF | RVC | |||
(15) BALLS | (20) PINS | |||
RθJA | Junction-to-ambient thermal resistance | 76.5 | 39.0 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 0.2 | 42.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 44 | 13.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.6 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 43.4 | 13.6 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | N/A | 3.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCL | SCL clock frequency | Standard mode | 100 | kHz | ||
Fast mode | 400 | kHz | ||||
tLOW | LOW period of the SCL clock | Standard mode | 4.7 | µs | ||
Fast mode | 1.3 | µs | ||||
tHIGH | HIGH period of the SCL clock | Standard mode | 4.0 | µs | ||
Fast mode | 600 | ns | ||||
tBUF | Bus free time between a STOP and START condition | Standard mode | 4.7 | µs | ||
Fast mode | 1.3 | µs | ||||
thd;STA | Hold time for a repeated START condition | Standard mode | 4.0 | µs | ||
Fast mode | 600 | ns | ||||
tsu;STA | Setup time for a repeated START condition | Standard mode | 4.7 | µs | ||
Fast mode | 600 | ns | ||||
tsu;DAT | Data setup time | Standard mode | 250 | ns | ||
Fast mode | 100 | ns | ||||
thd;DAT | Data hold time | Standard mode | 0.05 | 3.45 | µs | |
Fast mode | 0.05 | 0.9 | µs | |||
tRCL1 | Rise time of SCL signal after a repeated START condition and after an acknowledge bit | Standard mode | 20 + 0.1CB | 1000 | ns | |
Fast mode | 20 + 0.1CB | 1000 | ns | |||
tRCL | Rise time of SCL signal | Standard mode | 20 + 0.1CB | 1000 | ns | |
Fast mode | 20 + 0.1CB | 300 | ns | |||
tFCL | Fall time of SCL signal | Standard mode | 20 + 0.1CB | 300 | ns | |
Fast mode | 20 + 0.1CB | 300 | ns | |||
tRDA | Rise time of SDA signal | Standard mode | 20 + 0.1CB | 1000 | ns | |
Fast mode | 20 + 0.1CB | 300 | ns | |||
tFDA | Fall time of SDA signal | Standard mode | 20 + 0.1CB | 300 | ns | |
Fast mode | 20 + 0.1CB | 300 | ns | |||
tsu;STO | Setup time for STOP condition | Standard mode | 4.0 | µs | ||
Fast mode | 600 | ns | ||||
CB | Capacitive load for SDA and SCL | 0.4 | nF |
The TPS65132, supporting input voltage range from 2.5 V to 5.5 V, operates with a single inductor scheme to provide a high efficiency with a small solution size. The synchronous boost converter generates a positive voltage that is regulated down by an integrated LDO, providing the positive supply rail (VPOS). The negative supply rail (VNEG) is generated by an integrated negative charge pump (or CPN) driven from the boost converter output pin, REG. The operating mode can be selected between 40mA and 80mA in order to select the necessary output current capability and to get the best efficiency possible based on the application. The device topology allows a 100% asymmetry of the output currents.
The TPS65132 integrates an undervoltage lockout block (UVLO) that enables the device once the voltage on the VIN pin exceeds the UVLO threshold (2.5 V maximum). No output voltage will be generated as long as the enable signals are not pulled HIGH. The device, as well as all converters (boost converter, LDO, CPN), will be disabled as soon as the VIN voltage falls below the UVLO threshold. The UVLO threshold is designed in a way that the TPS65132 will continue operating as long as VIN stays above 2.3 V. This guarantees a proper operation even in the event of extensive line transients when the battery gets suddenly heavily loaded.
For TPS65132Ax, a 40 ms delay is starting as soon as the UVLO threshold is reached. This delay prevents the device to be disabled and enabled by an unwanted VIN voltage spike. Once this delay has passed, the output rails can be enabled and disabled as desired with the enable signals without any delay.
An active discharge of the positive rail and/or the negative rail can be programmed (DISP and DISN bits respectively - refer to Registers). If programmed to be active, the discharge will occur at power down, when the enable signals go LOW (Figure 37 and Figure 38 for TPS65132Ax, Bx, Lx, Tx, Wx — Figure 105 and Figure 104 for TPS65132Sx). See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant implements the active discharge function.
The synchronous boost converter uses a current mode topology and operates at a quasi-fixed frequency of typically 1.8 MHz, allowing chip inductors such as 2.2 µH or 4.7 µH to be used. The converter is internally compensated and provides a regulated output voltage automatically adjusted depending on the programmed VPOS and VNEG voltages. The boost converter operates either in continuous conduction mode (CCM) or Pulse Frequency Modulation mode (PFM), depending on the load current in order to provide the highest efficiency possible. The switch node waveforms for CCM and DCM operation are shown in Figure 6 and Figure 7.
The boost converter starts switching as soon as one enable signal is pulled HIGH and the voltage on VIN pin is above the UVLO threshold. For TPS65132Ax, in the case where one enable signal is already HIGH when VIN reaches the UVLO threshold, the boost converter will only start switching after a 40 ms delay has passed (see Undervoltage Lockout (UVLO)).
The boost converter starts up with an integrated soft-start to avoid drawing excessive inrush current from the supply. The output voltage VREG is slowly ramped up to its target value. Typical startup waveforms for low-current applications are shown in Figure 33 and Figure 35.
The boost converter stops switching when VIN is below the UVLO threshold or when both output rails are disabled. For example, due to a special sequencing, the LDO might still be operating while the CPN is already disabled, in which case, the boost will continue operating until the LDO has been disabled. Typical power-down waveforms for low-current applications are shown in Figure 34 and Figure 36.
The boost converter output (REG) is isolated from the input supply VIN, providing a true shutdown.
The output voltage of the boost converter is automatically adjusted depending on the programmed VPOS and VNEG voltages.
The TPS65132 device integrates a power save mode to improve efficiency at light load. In power save mode the converter stops switching when the inductor current reaches 0 A. The device resumes its switching activity with one or more pulses once the VREG voltage falls below its regulation level, and goes again into power save mode once the inductor current reaches 0 A. The pulse duration remains constant, but the frequency of these pulses varies according to the output load. This operating mode is also known as Pulse Frequency Modulation or PFM. Figure 6 provides plots of the inductor current and the switch node in PFM mode.
The Low Dropout regulator (or LDO) generates the positive voltage rail, VPOS, by regulating down the output voltage of the boost converter (VREG). Its inherent power supply rejection helps filtering the output ripple of the boost converter in order to provide on OUTP pin a clean voltage, e.g. to supply the source driver IC of the display.
The LDO starts operating as soon as the ENP signal is pulled HIGH, VIN voltage is above the UVLO threshold and the boost converter has reached its Power Good threshold.
In the case where the enable signal is already HIGH when VIN exceeds the UVLO threshold, the boost converter will start first and the LDO will only start after the boost converter has reached its target voltage. For TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).
For TPS65132Sx the LDO startup is defined by the setting of the DLYx register and the SEQU bits, see Registers for more details.
The LDO integrates a soft-start that slowly ramps up its output voltage VPOS regardless of the output capacitor and the target voltage, as long as the LDO current limit is not reached. For TPS65132Ax and TPS65132Bx (except TPS65132B2), the typical startup time is 140 µs. For TPS65132B2, TPS65132Lx, TPS65132Sx, TPS65132Tx and TPS65132Wx, the typical ramp-up time is 500 µs and the inrush current is also reduced by a factor of 3. Typical startup waveforms for the low-current application are shown in Figure 33 to Figure 35.
The LDO stops operating when VIN is below the UVLO threshold or when ENP is pulled LOW. Or for TPS65132Sx when EN is pulled LOW, and the internal sequencing has passed.
The positive rail can be actively discharged to GND during power-down if required. A discharge selection bit is available to enable or disable this function. See Registers for more details, as well as waveforms in Figure 37 and Figure 38. Table 1 shows the VPOS active discharge behavior of each device variant.
PART NUMBER | VIN | ENP (or EN) | ENN (or SYNC) | VPOS DISCHARGE |
---|---|---|---|---|
TPS65132Ax | < VUVLO | Don't Care | Don't Care | On |
> VUVLO | Low | Low | Determined by DISP bit | |
Low | High | Determined by DISP bit | ||
High | Low | Off | ||
High | High | Off | ||
TPS65132Bx TPS65132Lx TPS65132Sx TPS65132Tx TPS65132Wx |
< VUVLO | Don't Care | Don't Care | On |
> VUVLO | Low | Low | On | |
Low | High | Determined by DISP bit | ||
High | Low | Off | ||
High | High | Off |
The LDO is isolating the VPOS rail from VREG (boost converter output) as long as the rail is not enabled in order to ensure flexible startup like VNEG before VPOS.
The output voltage of the LDO is programmable via a I2C compatible interface, from –6.0 V to –4.0 V in 100 mV steps. For more details, please refer to the VPOS Register – Address: 0x00
The negative charge pump (CPN) generates the negative voltage rail, VNEG, by inverting and regulating the output voltage of the boost converter (VREG). The charge pump uses 4 switches and an external flying capacitor to generate the negative rail. Two of the switches are turned on in the first phase to charge the flying capacitor up to VREG, and in the second phase they are turned-off and the two others turn on to pump the energy negatively out of the OUTN capacitor.
The CPN starts operating as soon as the ENN signal is pulled HIGH, VIN voltage is above the UVLO threshold and the boost converter has reached its Power Good threshold.
In the case where the enable signal is already HIGH when VIN reaches the UVLO threshold, the boost converter will start first and the CPN will only start after the boost converter has reached its target voltage. For TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).
For TPS65132Sx the CPN startup is defined by the setting of the DLYx register and the SEQU bits, see Registers for more details.
The CPN integrates a soft-start that slowly ramps up its output voltage VNEG within a time defined by the selected mode (40mA or 80mA), the output voltage and the output capacitor value. For TPS65132Ax and TPS65132Bx (except TPS65132B2), the startup current charging the output capacitor in 40mA mode is 50 mA, and 100 mA typically in 80mA mode. For TPS65132B2, TPS65132Lx, TPS65132Tx, and TPS65132Wx, the typical ramp-up times are slowed down by a factor of 4 (i.e 12.5 mA and 25 mA typical output current for 40mA and 80mA modes respectively) and the inrush current is also reduced by a factor of about 4. Typical startup waveforms for the low-current application are shown in Figure 39 to Figure 42.
For TPS65132Sx, the negative rail starts-up in 40mA or 80mA mode, thus the startup current is set by the mode the device is programmed to, and not related to the SYNC pin state. The full current of 150 mA minimum is only released once both rails (VPOS and VNEG) have reached their Power Good levels.
The estimated startup time can be calculated using the following formula:
Where:
tSTARTUP = startup time of the VNEG rail
COUT = output capacitance of the VNEG rail
VNEG = target output voltage
ISTARTUP = output current of the VNEG rail charging up the output capacitor at startup (12.5 mA, 25 mA, 50 mA or 100 mA as described above)
The CPN stops operating when VIN is below the UVLO threshold or when ENN is pulled LOW.
Or when EN is pulled LOW in the TPS65132Sx, and the internal sequencing has passed.
The negative rail can be actively discharged to GND during power-down if required. A discharge selection bit is available to enable or disable this function. See for more details, as well as waveforms Figure 37 and Figure 38. Table 2 shows the VNEG discharge behavior of each device variant.
PART NUMBER | VIN | ENP (or EN) | ENN (or SYNC) | VNEG DISCHARGE |
---|---|---|---|---|
TPS65132Ax | < VUVLO | Don't Care | Don't Care | On |
> VUVLO | Low | Low | Determined by DISN bit | |
Low | High | Off | ||
High | Low | Determined by DISN bit | ||
High | High | Off | ||
TPS65132Bx TPS65132Lx TPS65132Tx TPS65132Wx |
< VUVLO | Don't Care | Don't Care | On |
> VUVLO | Low | Low | On | |
Low | High | Off | ||
High | Low | Determined by DISN bit | ||
High | High | Off | ||
TPS65132Sx | < VUVLO | Don't Care | Don't Care | On |
> VUVLO | Low | Low | On | |
Low | High | Determined by DISN bit | ||
High | Low | Off | ||
High | High | Off |
The CPN isolates the VNEG rail from VREG (boost converter output) as long as the rail is not enabled in order to ensure flexible startup like VPOS before VNEG.
The output voltage of the CPN is programmable via a I2C compatible interface, from –4.0 V to –6.0 V in 100 mV steps. For more details, please refer to the VNEG Register – Address 0x01.
At startup (VIN goes above UVLO and at least one of the enable pins (ENP, ENN, or EN) goes HIGH), the EEPROM content is loaded into the DAC registers and the IC starts with these default values. The TPS65132 is enabled as long as the VIN voltage is above the UVLO and one of the enable pins (ENP, ENN, or EN) is HIGH.
Pulling ENP or ENN LOW disables either rail (VPOS or VNEG respectively); and, pulling both pins LOW disables the device entirely (the internal oscillator of the TPS65132Ax continues running to allow access to the I²C interface).
For TPS65132Sx, pulling EN LOW disables the device.
The TPS65132 communicates through an industry standard I2C compatible interface, to receive data in slave mode. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000).
The TPS65132 integrates a non-volatile memory (EEPROM) that allows the storage of the register values with a capability of up to 1000 programming cycles. At startup the TPS65132 loads first the EEPROM content into the registers and uses these voltages to start.
It is recommended to stop I2C communication with the TPS65132 for 50 ms after the command "Write EEPROM data" was sent. If the device is accessed via I2C during EEPROM programming, the device will pull down the SCL line (clock stretch) after it recognized its I2C address. The SCL line will be released after EEPROM programming is finished.
The TPS65132 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus specification: standard mode (100 kbps) and fast mode (400 kbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The TPS65132 supports 7-bit addressing. The device 7-bit address is 3E (see Figure 8), and the LSB enables the write or read function.
MSB | TPS65132 | Address | LSB | ||||
0 | 1 | 1 | 1 | 1 | 1 | 0 | R/W |
R/W = R/(W) |
NOTE
With TPS65132Ax, the I2C interface is accessible as long as the input voltage is above the undervoltage lockout threshold. In all other versions, the I2C interface is accessible only as soon as one of the enable pins is pulled HIGH while the input voltage is above the undervoltage lockout.
The TPS65132 has a non-volatile memory (EEPROM) which contains the initial values and one volatile memory (Registers) which contains the actual settings. The EEPROM and the Registers are accessed with the same address.
Startup option: At power-up, the values contained in the EEPROM are loaded into the Registers to the last stored setting within less than 20 µs. The programmed factory value of the EEPROM of each address is described in section Factory Default Register Value.
Write description: The user has to program all Registers first (0×00 to 0×03), then set the WED (Write EEPROM Data) bit to 1. A dead time of 50 ms is then initiated during which the register content or all registers (0×00 ~ 0×03) are stored into the non-volatile EEPROM cells. During that time, there should be no data flowing through the I2C because the I2C interface is momentarily not responding.
After the 50 ms have passed, the WED bit is automatically reset to 0, and the user is able to read the values or program again.
Slave address: | 0x3E |
X = R/W | R/W = 1 → read mode |
R/W = 0 → write mode |
Attempting to read data from register addresses not listed in the following section will result in 0x00 being read out.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | VPOS[4:0] | ||||
0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
R | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Description | |||
---|---|---|---|---|---|
7:5 | RSVD[2:0] | Reserved, always set to 0 | |||
4:0 | VPOS[4:0] | VPOS output voltage adjustment | |||
VPOS[4:0] Value (binary) | VPOS Output Voltage (V) | VPOS[4:0] Value (binary) | VPOS Output Voltage (V) | ||
00000 | 4.0 | 01011 | 5.1 | ||
00001 | 4.1 | 01100 | 5.2 | ||
00010 | 4.2 | 01101 | 5.3 | ||
00011 | 4.3 | 01110 | 5.4 | ||
00100 | 4.4 | 01111 | 5.5 | ||
00101 | 4.5 | 10000 | 5.6 | ||
00110 | 4.6 | 10001 | 5.7 | ||
00111 | 4.7 | 10010 | 5.8 | ||
01000 | 4.8 | 10011 | 5.9 | ||
01001 | 4.9 | 10100 | 6.0 | ||
01010 | 5.0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | VNEG[4:0] | ||||
0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
R | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Description | |||
---|---|---|---|---|---|
7:5 | RSVD[2:0] | Reserved, always set to 0 | |||
4:0 | VNEG[4:0] | VNEG output voltage adjustment | |||
VNEG[4:0] Value (binary) | VNEG Output Voltage (V) | VNEG[4:0] Value (binary) | VNEG Output Voltage (V) | ||
00000 | –4.0 | 01011 | –5.1 | ||
00001 | –4.1 | 01100 | –5.2 | ||
00010 | –4.2 | 01101 | –5.3 | ||
00011 | –4.3 | 01110 | –5.4 | ||
00100 | –4.4 | 01111 | –5.5 | ||
00101 | –4.5 | 10000 | –5.6 | ||
00110 | –4.6 | 10001 | –5.7 | ||
00111 | –4.7 | 10010 | –5.8 | ||
01000 | –4.8 | 10011 | –5.9 | ||
01001 | –4.9 | 10100 | –6.0 | ||
01010 | –5.0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLYP2 | DLYP2 | DLYN2 | DLYN2 | DLYP1 | DLYP1 | DLYN1 | DLYN1 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
R/W |
Bit | Field | Description | |||
---|---|---|---|---|---|
7:6 | DLYP2[1:0] | Delay in milliseconds | |||
5:4 | DLYN2[1:0] | ||||
3:2 | DLYP1[1:0] | ||||
1:0 | DLYN1[1:0] | ||||
DLYx[1:0] | DLYx Value (binary) | DLYx Delay (ms) | |||
00 | 0 | ||||
01 | 1 | ||||
10 | 5 | ||||
11 | 10 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | APPS | SEQU | SEQU | SEQD | SEQD | DISP | DISN |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Description | Value (binary) | Action | ||
---|---|---|---|---|---|---|
7 | RSVD | Reserved, always set to 0 | ||||
6 | APPS | Application | APPS Value | 0 | 40mA | |
1 | 80mA | |||||
5:4 | SEQU(1) | Sequencing at Startup | SEQU Value | 00 | VPOS and VNEG simultaneously (DLYP1 after EN goes HIGH) | |
01 | VPOS (DLYP1 after EN goes HIGH) and then VNEG (DLYN1 after VPOS) | |||||
10 | VNEG (DLYN1 after EN goes HIGH) and then VPOS (DLYP1 after VNEG) | |||||
11 | VPOS only | |||||
3:2 | SEQD(1) | Sequencing at Shutdown | SEQD Value | 00 | VPOS and VNEG simultaneously (DLYP2 after EN goes LOW) | |
01 | VPOS (DLYP2 after EN goes LOW) and then VNEG (DLYN2 after VPOS) | |||||
10 | VNEG (DLYN2 after EN goes LOW) and then VPOS (DLYP2 after VNEG) | |||||
11 | Ignored | |||||
1 | DISP(2) | Discharge VPOS | DISP Value | 0 | No discharge | |
1 | VPOS actively discharged | |||||
0 | DISN(2) | Discharge VNEG | DISN Value | 0 | No discharge | |
1 | VNEG actively discharged |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WED | RSVD[6:1] | EE/(DR) |
The Reserved bits are ignored when written and return either 0 or 1 when read. |
Bit | Field | Value (binary) | Description | |||
---|---|---|---|---|---|---|
7 | WED | 0 | No action | |||
1 | Write EEPROM Data | |||||
6:1 | RSVD[6:1] | Reserved | ||||
0 | EE/(DR) | 0 | Read from Registers | |||
1 | Read from EEPROM |
Part number | Register address | ||||
---|---|---|---|---|---|
0x00 | 0x01 | 0x02 | 0x03 | ||
TPS65132A | 0x0E | 0x0E | — | 0x03 | |
TPS65132A0 | 0x0A | 0x0A | — | 0x03 | |
TPS65132B | 0x0E | 0x0E | — | 0x03 | |
TPS65132B0 | 0x0A | 0x0A | — | 0x03 | |
TPS65132B2 | 0x0C | 0x0C | — | 0x03 | |
TPS65132B5 | 0x0F | 0x0F | — | 0x03 | |
TPS65132L | 0x0E | 0x0E | — | 0x03 | |
TPS65132L0 | 0x0A | 0x0A | — | 0x03 | |
TPS65132L1 (1) | 0x0B | 0x0B | — | 0x03 | |
TPS65132S | 0x0E | 0x0E | 0x00 | 0x43 | |
TPS65132T6 | 0x10h | 0x10h | — | 0x43 | |
TPS65132W | 0x0E | 0x0E | — | 0x43 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS65132xx devices, primarily intended to supplying TFT LCD displays, can be used for any application that requires positive and negative supplies, ranging from ±4 V to ±6 V and current up to 80 mA (150 mA for the TPS65132Sx version). Both output voltages can be set independently and their sequencing is also independent. The following section presents the different operating modes that the device can support as well as the different features that the user can select.
The TPS65132 can be programmed to 40mA mode with the APPS bit to support applications that require output currents up to 40 mA (refer to Figure 17). The 40mA mode limits the negative charge pump output current to 40 mA DC in order to provide the highest efficiency possible. The VPOS rail can deliver up to 200 mA DC regardless of the mode. Output peak currents are supported by the output capacitors.
PARAMETERS | EXAMPLE VALUES |
---|---|
Input Voltage Range | 2.5 V to 5.5 V |
Output Voltages | 4.0 V to 6.0 V, –4.0 V to –6.0 V |
Output Current Rating | 40 mA |
Boost Converter Switching Frequency | 1.8 MHz |
Negative Charge Pump Switching Frequency | 1.0 MHz |
Each output rail (VPOS and VNEG) is enabled and disabled using an external enable signal. If not explicitly specified, the enable signal in the rest of the document refers to ENN or ENP: ENP for the positive rail VPOS and ENN for the negative rail VNEG. Figure 33 to Figure 36 show the typical sequencing waveforms.
NOTE
In the case where VIN falls below the UVLO threshold while one of the enable signals is still high, all converters will be shut down instantaneously and both VPOS and VNEG output rails will be actively discharged to GND.
The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. A simple approach is to estimate the converter efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load or to use a worst case assumption for the expected efficiency, e.g., 85%.
η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒSW = Boost converter switching frequency (1.8 MHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Boost converter switch current at the desired output current (must be < [ ILIM_min + ΔIL])
ΔIL = Inductor peak-to-peak ripple current
VREG = max (VPOS, |VNEG|) + 200 mV (in 40mA mode — + 300 mV in 80mA mode — + 500 mV with TPS65132Sx with SYNC = HIGH)
IOUT = IOUT_VPOS + | IOUT_VNEG| (IOUT_max being the maximum current delivered on each rail)
The peak switch current is the current that the integrated switch and the inductor have to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest.
Saturation current: the inductor must handle the maximum peak current (IL_SAT > ISWPEAK, or IL_SAT > [ ILIM_min + ΔIL] as conservative approach)
DC Resistance: the lower the DCR, the lower the losses
Inductor value: in order to keep the ratio IOUT/ΔIL low enough for proper sensing operation purpose, it is recommended to use a 4.7 µH inductor for 40mA mode (a 2.2 µH might however be used, but the efficiency might be lower than with 4.7 µH at light loads depending on the inductor characteristics).
L (µH) |
SUPPLIER(1) | COMPONENT CODE | EIA SIZE | DCR TYP (mΩ) |
ISAT
(A) |
---|---|---|---|---|---|
2.2 | Toko | 1269AS-H-2R2N=P2 | 1008 | 130 | 2.4 |
2.2 | Murata | LQM2HPN2R2MG0 | 1008 | 80 | 1.3 |
2.2 | Murata | LQM21PN2R2NGC | 0805 | 250 | 0.8 |
4.7 | Toko | 1269AS-H-4R7N=P2 | 1008 | 250 | 1.6 |
4.7 | Murata | LQM21PN4R7MGR | 0805 | 230 | 0.8 |
4.7 | FDK | MIPS2520D4R7 | 1008 | 280 | 0.7 |
For best input voltage filtering low ESR ceramic capacitors are recommended. TPS65132 has an analog input pin VIN. A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also used as the boost converter input capacitor.
For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for input capacitor recommendations.
For the best output voltage filtering, low-ESR ceramic capacitors are recommended. A minimum of 4.7 µF ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for output capacitor recommendations.
CAPACITOR (µF) |
SUPPLIER | COMPONENT CODE | EIA SIZE (Thickness max.) | VOLTAGE RATING (V) |
COMMENTS |
---|---|---|---|---|---|
2.2 | Murata | GRM188R61C225KAAD | 0603 (0.9 mm) | 16 | CFLY |
4.7 | Murata | GRM188R61C475KAAJ | 0603 (0.95 mm) | 16 | CIN, CNEG, CPOS, CREG |
10 | Murata | GRM219R61C106KA73 | 0603 (0.95 mm) | 16 | CNEG, CREG |
The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.
The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.
The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.
The CPN is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 19.
The CPN needs an external flying capacitor. The minimum value is 2.2 µF. Special care must be taken while choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation performance. Therefore, a minimum capacitance of 1 µF must be achieved by the capacitor at a DC bias voltage of │VNEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of the boost converter on REG pin.
REFERENCE | DESCRIPTION | MANUFACTURER AND PART NUMBER(1) |
---|---|---|
C | 2.2 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C225KAAD |
4.7 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C475KAAJ | |
10 μF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61E106MA73 | |
L | 2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm | Toko - DFE252010C (1269AS-H-2R2N=P2) |
4.7 µH, 1.6 A, 250 mΩ, 2.5 mm × 2.0 mm × 1.0 mm | Toko - DFE252010C (1269AS-H-4R7N=P2) | |
U1 | TPS65132AYFF | Texas Instruments |
PARAMETER | CONDITIONS | Figure |
---|---|---|
EFFICIENCY | ||
Efficiency vs. Output Current | ± 5.0 V — 40mA Mode — L = 4.7 µH | Figure 20 |
Efficiency vs. Output Current | ± 5.4 V — 40mA Mode — L = 4.7 µH | Figure 21 |
Efficiency vs. Output Current | ± 5.0 V — 40mA Mode — L = 2.2 µH | Figure 22 |
Efficiency vs. Output Current | ± 5.4 V — 40mA Mode — L = 2.2 µH | Figure 23 |
CONVERTERS WAVEFORMS | ||
VNEG Output Ripple | INEG = 2 mA / 20 mA / 40 mA — 40mA Mode — COUT = 4.7 µF | Figure 24 |
VNEG Output Ripple | INEG = 2 mA / 20 mA / 40 mA — 40mA Mode — COUT = 2 × 4.7 µF | Figure 25 |
VPOS Output Ripple | Any load | Figure 26 |
LOAD TRANSIENT | ||
Load Transient | VIN = 2.9 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH | Figure 27 |
Load Transient | VIN = 3.7 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH | Figure 28 |
Load Transient | VIN = 4.5 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH | Figure 29 |
LINE TRANSIENT | ||
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 0 mA — 40mA Mode — L = 4.7 µH | Figure 30 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 5 mA — 40mA Mode — L = 4.7 µH | Figure 31 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 35 mA — 40mA Mode — L = 4.7 µH | Figure 32 |
POWER SEQUENCING | ||
Power-up Sequencing | Simultaneous — no load | Figure 33 |
Power-down Sequencing | Simultaneous — no load with Active Discharge | Figure 34 |
Power-up Sequencing | Sequential — no load | Figure 35 |
Power-down Sequencing | Sequential — no load with Active Discharge | Figure 36 |
Power-up/down Sequencing | Simultaneous — no load with Active Discharge | Figure 37 |
Power-up/down Sequencing | Simultaneous — no load without Active Discharge | Figure 38 |
INRUSH CURRENT | ||
Inrush Current | Simultaneous — no load — 40mA Mode | Figure 39 |
Inrush Current | Sequential — no load — 40mA Mode | Figure 40 |
Inrush Current | Simultaneous — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx | Figure 41 |
Inrush Current | Sequential — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx | Figure 42 |
LOAD REGULATION | ||
VPOS vs Output Current | VPOS = 5.0 V — 40mA Mode — IPOS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH | Figure 43 |
VPOS vs Output Current | VPOS = 5.4 V — 40mA Mode — IPOS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH | Figure 44 |
VNEG vs Output Current | VNEG = –5.0 V — 40mA Mode — INEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH | Figure 45 |
VNEG vs Output Current | VNEG = –5.4 V — 40mA Mode — INEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH | Figure 46 |
LINE REGULATION | ||
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — 40mA Mode — IPOS = 20 mA — L = 4.7 µH and 2.2 µH | Figure 47 |
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — 40mA Mode — IPOS = 20 mA — L = 4.7 µH and 2.2 µH | Figure 48 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — 40mA Mode — INEG = 20 mA — L = 4.7 µH and 2.2 µH | Figure 49 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — 40mA Mode — INEG = 20 mA — L = 4.7 µH and 2.2 µH | Figure 50 |
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
± 5.0 V | L = 4.7 µH |
± 5.4 V | L = 4.7 µH |
± 5.0 V | L = 2.2 µH |
L = 4.7 µH | COUT = 4.7 µF |
± 5.4 V | L = 2.2 µH |
L = 4.7 µH | COUT = 2 × 4.7 µF |
VIN = 2.9 V | ΔIOUT = 30 mA |
VIN = 4.5 V | ΔIOUT = 30 mA |
IOUT = 5 mA | ΔVIN = 1.7 V |
VIN = 3.7 V | ΔIOUT = 30 mA |
IOUT = 0 mA | ΔVIN = 1.7 V |
IOUT = 35 mA | ΔVIN = 1.7 V |
VPOS = 5 V |
VNEG = –5 V |
VPOS = 5 V |
VNEG = –5 V |
VPOS = 5.4 V |
VNEG = –5.4 V |
VPOS = 5.4 V |
VNEG = –5.4 V |
The TPS65132 can be programmed to 80mA mode with the APPS bit to support applications that require output currents up to 80 mA (refer to Figure 17). The 80mA mode is limiting the negative charge pump (CPN) output current to 80 mA DC in order to provide the highest efficiency possible where the V(POS) rail can deliver up to 200 mA DC regardless of the mode. Output peak currents are supported by the output capacitors.
PARAMETERS | EXAMPLE VALUES |
---|---|
Input Voltage Range | 2.5 V to 5.5 V |
Output Voltages | 4.0 V to 6.0 V, –4.0 V to –6.0 V |
Output Current Rating | 80 mA |
Boost Converter Switching Frequency | 1.8 MHz |
Negative Charge Pump Switching Frequency | 1.0 MHz |
The design procedure for the mid-current applications (80mA mode) is identical to the one for the low-current applications (40mA mode), except for the BOM (bill of materials). Refer to the Detailed Design Procedure for details about the sequencing and the general component selection.
In order to keep the ratio IOUT/ΔIL low enough for proper sensing operation purpose, it is recommended to use a 2.2 µH inductor for 80mA mode. For details, see Inductor Selection (Boost Converter).
A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also used as the boost converter input capacitor.
For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the Recommended Operating Conditions, Table 10 and Figure 51 for input capacitor recommendations.
For best output voltage filtering low ESR ceramic capacitors are recommended. A minimum of 10 µF ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer to the Recommended Operating Conditions, Table 10 and Figure 51 for output capacitor recommendations.
The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.
The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.
The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.
The CPN is designed to operate with a 10 µF minimum ceramic output capacitor. Refer to the Recommended Operating Conditions, Table 10 and Figure 51.
The CPN needs an external flying capacitor. The minimum value is 4.7 µF. Special care must be taken while choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation performance. Therefore, a minimum capacitance of 2.2 µF must be achieved by the capacitor at a DC bias voltage of │VNEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of the boost converter on REG pin.
REFERENCE | DESCRIPTION | MANUFACTURER AND PART NUMBER(1) |
---|---|---|
C | 2.2 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C225KAAD |
4.7 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C475KAAJ | |
10 μF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61E106MA73 | |
L | 2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm | Toko - DFE252010C (1269AS-H-2R2N=P2) |
U1 | TPS65132AYFF | Texas Instruments |
PARAMETER | CONDITIONS | Figure |
---|---|---|
EFFICIENCY | ||
Efficiency vs. Output Current | ± 5.0 V — 80mA Mode — L = 2.2 µH | Figure 52 |
Efficiency vs. Output Current | ± 5.4 V — 80mA Mode — L = 2.2 µH | Figure 53 |
CONVERTERS WAVEFORMS | ||
VNEG Output Ripple | INEG = 4 mA / 40 mA / 80 mA — 80mA Mode — COUT = 10 µF | Figure 54 |
VNEG Output Ripple | INEG = 4 mA / 40 mA / 80 mA — 80mA Mode — COUT = 2 × 10 µF | Figure 55 |
VPOS Output Ripple | IPOS = 150 mA — 80mA Mode | Figure 56 |
LOAD TRANSIENT | ||
Load Transient | VIN = 2.9 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH | Figure 57 |
Load Transient | VIN = 3.7 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH | Figure 58 |
Load Transient | VIN = 4.5 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH | Figure 59 |
LINE TRANSIENT | ||
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 0 mA — 80mA Mode — L = 2.2 µH | Figure 60 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 40 mA — 80mA Mode — L = 2.2 µH | Figure 61 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 70 mA — 80mA Mode — L = 2.2 µH | Figure 62 |
POWER SEQUENCING | ||
Power-up Sequencing | Simultaneous — no load | Figure 63 |
Power-down Sequencing | Simultaneous — no load with Active Discharge | Figure 64 |
Power-up Sequencing | Sequential — no load | Figure 65 |
Power-down Sequencing | Sequential — no load with Active Discharge | Figure 66 |
Power-up/down Sequencing | Simultaneous — no load with Active Discharge | Figure 67 |
Power-up/down Sequencing | Simultaneous — no load without Active Discharge | Figure 68 |
INRUSH CURRENT | ||
Inrush Current | Simultaneous — no load — 80mA Mode | Figure 69 |
Inrush Current | Sequential — no load — 80mA Mode | Figure 70 |
Inrush Current | Simultaneous — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx | Figure 71 |
Inrush Current | Sequential — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx | Figure 72 |
LOAD REGULATION | ||
VPOS vs Output Current | VPOS = 5.0 V — 80mA Mode — IPOS = 0 mA to 80 mA — L = 2.2 µH | Figure 73 |
VPOS vs Output Current | VPOS = 5.4 V — 80mA Mode — IPOS = 0 mA to 80 mA — L = 2.2 µH | Figure 74 |
VNEG vs Output Current | VNEG = –5.0 V — 80mA Mode — INEG = 0 mA to 80 mA — L = 2.2 µH | Figure 75 |
VNEG vs Output Current | VNEG = –5.4 V — 80mA Mode — INEG = 0 mA to 80 mA — L = 2.2 µH | Figure 76 |
LINE REGULATION | ||
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — 80mA Mode — IPOS = 60 mA — L = 2.2 µH | Figure 77 |
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — 80mA Mode — IPOS = 60 mA — L = 2.2 µH | Figure 78 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — 80mA Mode — INEG = 60 mA — L = 2.2 µH | Figure 79 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — 80mA Mode — INEG = 60 mA — L = 2.2 µH | Figure 80 |
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
± 5 V | L = 2.2 µH |
L = 2.2 µH | COUT = 10 µF |
± 5.4 V | L = 2.2 µH |
L = 2.2 µH | COUT = 2 × 10 µF |
VIN = 2.9 V | ΔIOUT = 60 mA |
VIN = 4.5 V | ΔIOUT = 60 mA |
IOUT = 40 mA | ΔVIN = 1.7 V |
VIN = 3.7 V | ΔIOUT = 60 mA |
IOUT = 0 mA | ΔVIN = 1.7 V |
IOUT = 70 mA | ΔVIN = 1.7 V |
VPOS = 5 V |
VNEG = –5 V |
VPOS = 5 V |
VNEG = –5 V |
VPOS = 5.4 V |
VNEG = –5.4 V |
VPOS = 5.4 V |
VNEG = –5.4 V |
The TPS65132Sx version allows output current up to 150 mA on both VPOS and VNEG when the SYNC pin is pulled HIGH. If the SYNC pin is pulled LOW, the TPS65132Sx can be programmed to 40mA or 80mA mode with the APPS bit to lower the output current capability of the VNEG rail if needed (in the case the efficiency is an important parameter). See Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details about the 40mA and 80mA modes.
PARAMETERS | EXAMPLE VALUES |
---|---|
Input Voltage Range | 2.5 V to 5.5 V |
Output Voltages | 4.0 V to 6.0 V, –4.0 V to –6.0 V |
Output Current Rating | 150 mA |
Boost Converter Switching Frequency | 1.8 MHz |
Negative Charge Pump Switching Frequency | 1.0 MHz |
The design procedure and BOM list of the TPS65132Sx is identical to the 80mA mode. Please refer to the Mid-current Applications (≤ 80 mA) for more details about the general component selection.
The output rails (VPOS and VNEG) are enabled and disabled using an external logic signal on the EN pin. The power-up and power-down sequencing events are programmable. Please refer to Programmable Sequencing Scenarios for the different sequencing as well as Registers for the programming options. Figure 98 to Figure 103 show the typical sequencing waveforms.
NOTE
When the SYNC pin is pulled HIGH, the boost converter voltage increases instantaneously to allow enough headroom to deliver the 150 mA. See Figure 88 to Figure 91 for detailed waveforms.
When SYNC pin is pulled LOW, the boost converter keeps its offset for 300 µs typically, and during this time, the device is still capable if supplying 150 mA on both output rail. After these 300 µs have passed, current limit settles at 40 mA or 80 mA maximum, depending on the application mode it is programmed to (40mA or 80mA — see Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details ) and the boost output voltage regulates down to its nominal value.
The TPS65132Sx can startup with SYNC = HIGH, however, the boost offset as well as the 150 mA output current capability will only be available as soon as the last rail to start is in regulation.
REFERENCE | DESCRIPTION | MANUFACTURER AND PART NUMBER |
---|---|---|
C | 2.2 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C225KAAD |
4.7 µF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61C475KAAJ | |
10 μF, 16 V, 0603, X5R, ceramic | Murata - GRM188R61E106MA73 | |
L | 2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm | Toko - DFE252010C (1269AS-H-2R2N=P2) |
U1 | TPS65132SYFF | Texas Instruments |
PARAMETER | CONDITIONS | Figure |
---|---|---|
EFFICIENCY | ||
Efficiency vs. Output Current | ± 5.0 V — SYNC = HIGH — L = 2.2 µH | Figure 83 |
Efficiency vs. Output Current | ± 5.4 V — SYNC = HIGH — L = 2.2 µH | Figure 84 |
CONVERTERS WAVEFORMS | ||
VPOS Output Ripple | IPOS = 150 mA — SYNC = HIGH | Figure 85 |
VNEG Output Ripple | INEG = 10mA / 80 mA / 150 mA — SYNC = HIGH — COUT = 10 µF | Figure 86 |
VNEG Output Ripple | INEG = 4 mA / 40 mA / 80 mA — SYNC = HIGH — COUT = 2 × 10 µF | Figure 87 |
SYNC = HIGH Signal | ||
SYNC = HIGH | IPOS = –INEG = 10 mA | Figure 88 |
SYNC = HIGH | IPOS = –INEG = 150 mA | Figure 89 |
SYNC = HIGH Zoom | IPOS = –INEG = 10 mA | Figure 90 |
SYNC = LOW Zoom | IPOS = –INEG = 10 mA | Figure 91 |
LOAD TRANSIENT | ||
Load Transient | VIN = 2.9 V — IPOS = –INEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH | Figure 92 |
Load Transient | VIN = 3.7 V — IPOS = –INEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH | Figure 93 |
Load Transient | VIN = 4.5 V — IPOS = –INEG = 10 mA → 150 mA → 10mA — SYNC = HIGH — L = 2.2 µH | Figure 94 |
LINE TRANSIENT | ||
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 10 mA — SYNC = HIGH — L = 2.2 µH | Figure 95 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 100 mA — SYNC = HIGH — L = 2.2 µH | Figure 96 |
Line Transient | VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 150 mA — SYNC = HIGH — L = 2.2 µH | Figure 97 |
POWER SEQUENCING | ||
Power-up Sequencing | Simultaneous — no load | Figure 98 |
Power-down Sequencing | Simultaneous — no load with Active Discharge | Figure 99 |
Power-up Sequencing | Sequential (VPOS → VNEG) — no load | Figure 100 |
Power-down Sequencing | Sequential (VNEG → VPOS) — no load with Active Discharge | Figure 101 |
Power-up Sequencing | Sequential (VNEG → VPOS) — no load | Figure 102 |
Power-down Sequencing | Sequential (VPOS → VNEG) — no load with Active Discharge | Figure 103 |
Power-up/down Sequencing | Simultaneous — no load without Active Discharge | Figure 104 |
Power-up/down Sequencing | Simultaneous — no load with Active Discharge | Figure 105 |
INRUSH CURRENT | ||
Inrush Current | Simultaneous — no load — SYNC = HIGH — L = 2.2 µH | Figure 106 |
Inrush Current | Sequential — no load — SYNC = HIGH — L = 2.2 µH | Figure 107 |
LOAD REGULATION | ||
VPOS vs Output Current | VPOS = 5.0 V — SYNC = HIGH — IPOS = 0 mA to 150 mA — L = 2.2 µH | Figure 108 |
VPOS vs Output Current | VPOS = 5.4 V — SYNC = HIGH — IPOS = 0 mA to 150 mA — L = 2.2 µH | Figure 109 |
VNEG vs Output Current | VNEG = –5.0 V — SYNC = HIGH — INEG = 0 mA to 150 mA — L = 2.2 µH | Figure 110 |
VNEG vs Output Current | VNEG = –5.4 V — SYNC = HIGH — INEG = 0 mA to 150 mA — L = 2.2 µH | Figure 111 |
LINE REGULATION | ||
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — SYNC = HIGH — IPOS = 120 mA — L = 2.2 µH | Figure 112 |
VPOS vs Output Voltage | VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — SYNC = HIGH — IPOS = 120 mA — L = 2.2 µH | Figure 113 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — SYNC = HIGH — INEG = 120 mA — L = 2.2 µH | Figure 114 |
VNEG vs Output Voltage | VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — SYNC = HIGH — INEG = 120 mA — L = 2.2 µH | Figure 115 |
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NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.