SLVSBC9C March   2012  – February 2016 TPS65177 , TPS65177A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 I2C Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up
        1. 7.3.1.1 TPS65177
        2. 7.3.1.2 TPS65177A
      2. 7.3.2 Power-Down
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Short-Circuit and Overload Protection
        1. 7.3.5.1 Boost Converter (V(AVDD)):
        2. 7.3.5.2 Buck 1 Converter (V(IO)):
        3. 7.3.5.3 Buck 2 Converter (V(CORE)):
        4. 7.3.5.4 Buck 3 Converter (V(HAVDD)):
        5. 7.3.5.5 Positive Charge-Pump Controller (V(GH)):
        6. 7.3.5.6 Negative Charge-Pump Controller (V(GL)):
    4. 7.4 Device Functional Modes
      1. 7.4.1 Boost Converter (V(AVDD))
        1. 7.4.1.1 Soft-Start
        2. 7.4.1.2 Compensation
        3. 7.4.1.3 Setting the Output Voltage V(AVDD)
        4. 7.4.1.4 High Voltage Stress Mode (HVS)
        5. 7.4.1.5 Programmable Current Limit
        6. 7.4.1.6 Design Procedure
        7. 7.4.1.7 Inductor Selection
        8. 7.4.1.8 Rectifier Diode Selection
          1. 7.4.1.8.1 Diode Type
          2. 7.4.1.8.2 Forward Voltage
          3. 7.4.1.8.3 Reverse Voltage
          4. 7.4.1.8.4 Thermal Characteristics
        9. 7.4.1.9 Output Capacitor Selection
      2. 7.4.2 Buck 1 Converter (V(IO))
        1. 7.4.2.1 Soft-Start
        2. 7.4.2.2 Setting the Output Voltage V(IO)
        3. 7.4.2.3 Design Procedure
        4. 7.4.2.4 Inductor Selection
        5. 7.4.2.5 Rectifier Diode Selection
          1. 7.4.2.5.1 Diode Type
          2. 7.4.2.5.2 Forward Voltage
          3. 7.4.2.5.3 Reverse Voltage
          4. 7.4.2.5.4 Forward Current
          5. 7.4.2.5.5 Thermal Characteristics
        6. 7.4.2.6 Output Capacitor Selection
      3. 7.4.3 BUCK 2 CONVERTER (V(CORE))
        1. 7.4.3.1 Soft-Start
        2. 7.4.3.2 Setting the Output Voltage V(CORE)
        3. 7.4.3.3 Design Procedure
        4. 7.4.3.4 Inductor Selection
        5. 7.4.3.5 Output Capacitor Selection
      4. 7.4.4 Buck 3 Converter (V(HAVDD))
        1. 7.4.4.1 Soft-Start
        2. 7.4.4.2 Setting the Output Voltage V(HAVDD)
        3. 7.4.4.3 High Voltage Stress Mode (HVS)
        4. 7.4.4.4 Design Procedure
        5. 7.4.4.5 Inductor Selection
        6. 7.4.4.6 Output Capacitor Selection
      5. 7.4.5 Positive Charge Pump Controller (V(GH)) with Temperature Compensation
        1. 7.4.5.1 Soft-Start
        2. 7.4.5.2 Setting the Output Voltage V(GH)
        3. 7.4.5.3 Design Procedure
        4. 7.4.5.4 Output Capacitor Selection
      6. 7.4.6 Negative Charge Pump Controller (V(GL))
        1. 7.4.6.1 Soft-Start
        2. 7.4.6.2 Setting the Output Voltage V(GL)
        3. 7.4.6.3 Design Procedure
        4. 7.4.6.4 Output Capacitor Selection
    5. 7.5 Gate Pulse Modulation (V(GHM))
    6. 7.6 Programming
      1. 7.6.1  I2C Serial Interface Description
      2. 7.6.2  Memory Description
      3. 7.6.3  Read / Write Description
      4. 7.6.4  Write Operation
        1. 7.6.4.1 Write Single Byte to the DAC Register (DR):
        2. 7.6.4.2 Write Multiple Bytes to the DAC Register (DR):
        3. 7.6.4.3 Write All DAC Register (DR) Data to EEPROM (EE):
      5. 7.6.5  READ OPERATION
        1. 7.6.5.1 Read single data from DAC register (DR):
        2. 7.6.5.2 Read Multiple Data from DAC Register (DR):
        3. 7.6.5.3 Read Single Data to EEPROM (EE):
        4. 7.6.5.4 Read Multiple Data to EEPROM (EE):
      6. 7.6.6  Write Single Data to DAC:
      7. 7.6.7  Write Multiple Data to DAC (Auto Increment Address):
      8. 7.6.8  Write all DAC Data to EEPROM:
      9. 7.6.9  Read Single Data From DAC / EEPROM:
      10. 7.6.10 Read Multiple Data fFom DAC / EEPROM (Auto Increment Address):
    7. 7.7 Register Map
      1. 7.7.1 Registers and DAC Settings
        1. 7.7.1.1  Channel Register (with factory value) - 00h (00h)
        2. 7.7.1.2  Boost Output Voltage V(AVDD) Register (with factory value) - 01h (0Fh)
        3. 7.7.1.3  Boost HVS Offset Voltage Register (with factory value) - 02h (05h)
        4. 7.7.1.4  Boost Current Limit Negative Offset Current Register (with factory value) - 03h (00h)
        5. 7.7.1.5  Boost Soft-start Time Register (with factory value) - 04h (00h)
        6. 7.7.1.6  Buck 1 Output Voltage V(IO) Register (with factory value) - 05h (03h):
        7. 7.7.1.7  Buck 2 Output Voltage V(CORE) Register (with factory value) - 06h (02h)
        8. 7.7.1.8  Buck 3 Output Voltage V(HAVDD) Register (with factory value) - 07h (1Bh)
        9. 7.7.1.9  Pos. Charge Pump Low Output Voltage V(GH_L) Register (with factory value) - 08h (08h):
        10. 7.7.1.10 Positive Charge Pump Low Output Voltage V(GH_L) to V(GH_H) Positive Offset Voltage V(GH_OFS) Register (with factory value) - 09h (04h):
        11. 7.7.1.11 Gate Pulse Modulation Limit Voltage Register (with factory value) - 0Ah (00h)
        12. 7.7.1.12 Negative Charge Pump Output Voltage V(GL) Register (with factory value) - 0Bh (04h)
        13. 7.7.1.13 Buck 3 HVS Offset Voltage Register (with factory value) - 0Ch (00h):
        14. 7.7.1.14 Memory Write Remain Time Register (with factory value) - FEh (0Fh):
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guideline
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 19 shows a typical application circuit suitable for supplying LCD panels with GIP or non-GIP technology.

8.2 Typical Applications

TPS65177 TPS65177A Externals.gif Figure 19. Typical Application

8.2.1 Design Requirements

For this design example, use the values shown in Table 6

Table 6. Design Parameters

PARAMETER VALUE
Voltage VI = 12 V, V(AVDD) = 18 V, V(HAVDD) = 9 V, V(IO) = 3.3 V, V(CORE) = 1.2 V, V(GH) = 28 V, V(GL) = –10.3 V
Switching Frequency Boost, Buck 1 = 750 kHz, Buck2, Buck 3 = 1 MHz

8.2.2 Detailed Design Procedure

See the Device Functional Modes section for the detailed design procedure.

8.2.3 Application Curves

PARAMETER CONDITIONS FIGURE
SEQUENCING
Power-on V(GL) driven by Buck 1 switch node VI = 12 V, V(IO) = 3.3 V, V(CORE) = 1.2 V, V(AVDD) = 18 V, V(HAVDD) = 9 V,
V(GH) = 28 V, V(GL) = –10.3 V		 Figure 20
Power-on V(GL) driven by Boost switch node VI = 12 V, V(IO) = 3.3 V, V(CORE) = 1.2 V, V(AVDD) = 18 V, V(HAVDD) = 9 V,
V(GH) = 28 V, V(GL) = –10.3 V		 Figure 21
Buck 1 Converter (VI = 12 V, L = 6.8 µH, COUT = 30 µF)
Efficiency vs. load current V(IO) = 3.3 V Figure 22
PWM switching – light load V(IO) = 3.3 V / 10 mA Figure 23
PWM switching – normal load V(IO) = 3.3 V / 500 mA Figure 24
Load Transient response V(IO) = 3.3 V / 100 mA → 500 mA Figure 25
Buck 2 Converter (VI = 3.3 V, L = 4.7 µH, COUT = 20 µF)
Efficiency vs. load current V(CORE) = 1.2 V Figure 26
PWM switching – light load V(CORE) = 1.2 V / 10 mA Figure 27
PWM switching – normal load V(CORE) = 1.2 V / 500 mA Figure 28
Load Transient response V(CORE) = 1.2 V / 10 mA → 300 mA Figure 29
Buck 3 Converter (VI = 12 V, L = 6.8 µH, COUT = 10 µF)
Efficiency vs. load current V(HAVDD) = 9 V Figure 30
PWM switching – light load sourcing V(HAVDD) = 9 V / 10 mA Figure 31
PWM switching – light load sinking V(HAVDD) = 9 V / -10 mA Figure 32
PWM switching –normal load sourcing V(HAVDD) = 9 V / 500 mA Figure 33
PWM switching – normal load sinking V(HAVDD) = 9 V / -500 mA Figure 34
Load Transient response V(HAVDD) = 9 V / 0 mA → 300 mA → 0 mA → -350 mA Figure 35
Boost Converter (VI = 12 V, L = 6.8 µH, C(ISOSW) = 10 µF, COUT = 40 µF)
Efficiency vs. load current V(AVDD) = 18 V Figure 36
PWM switching – light load V(AVDD) = 18 V / 10 mA Figure 37
PWM switching – normal load V(AVDD) = 18 V / 500 mA Figure 38
Load Transient response V(AVDD) = 18 V / 100 mA → 500 mA Figure 39
Positive Charge-Pump (VI = 12 V, Diode = BAV99, R(SW) = 2.2 Ω, Transistor = KTA1666, COUT = 4.7 µF)
Light load operation V(GH) = 28 V / 10 mA Figure 40
Normal load operation V(GH) = 28 V / 50 mA Figure 41
Load Transient response V(GH) = 28 V / 10 mA → 50 mA Figure 42
Negative Charge-Pump (VI = 12 V, Diode = BAV99, R(SW) = 2.2 Ω, Transistor = KTC4376, COUT = 4.7 µF)
Light load operation V(GL) = –7.9 V / 10 mA Figure 43
Normal load operation V(GL) = –7.9 V / 50 mA Figure 44
Load Transient response V(GL) = –7.9 V / 10 mA → 50 mA Figure 45
TPS65177 TPS65177A g01_lvsbb1.gif
Figure 20. Startup Sequencing V(GL) Driven By Buck 1
TPS65177 TPS65177A G027_lvsbb1.png
Figure 22. Buck 1 (V(IO)) Efficiency vs Load Current
TPS65177 TPS65177A g05_lvsbb1.gif
Figure 24. Buck 1 (V(IO)) PWM Switching – Normal Load
TPS65177 TPS65177A G028A_lvsbb1.gif
Figure 26. Buck 2 (V(CORE)) Efficiency vs Load Current
TPS65177 TPS65177A g09_lvsbb1.gif
Figure 28. Buck 2 (V(CORE)) PWM Switching – Normal Load
TPS65177 TPS65177A G029_lvsbb1.png
Figure 30. Buck 3 (V(HAVDD)) Efficiency vs Load Current
TPS65177 TPS65177A g013_lvsbb1.gif
Figure 32. Buck 3 (V(HAVDD)) PWM – Light Load Sink
TPS65177 TPS65177A g015_lvsbb1.gif
Figure 34. BUCK 3 (V(HAVDD)) PWM – Normal Load Sink
TPS65177 TPS65177A G030_lvsbb1.png
Figure 36. Boost (V(AVDD)) Efficiency vs Load Current
TPS65177 TPS65177A g019_lvsbb1.gif
Figure 38. Boost (V(AVDD)) PWM Switching – Normal Load
TPS65177 TPS65177A g021_lvsbb1.gif
Figure 40. Positive Charge-Pump (V(GH)) Light Load
TPS65177 TPS65177A g023_lvsbb1.gif
Figure 42. Positive CP (V(GH)) Load Transient Response
TPS65177 TPS65177A g025_lvsbb1.gif
Figure 44. Negative Charge-Pump (V(GL)) Normal Load
TPS65177 TPS65177A g02_lvsbb1.gif
Figure 21. Startup Sequencing V(GL) Driven By Boost
TPS65177 TPS65177A g04_lvsbb1.gif Figure 23. Buck 1 (V(IO)) PWM Switching – Light Load
TPS65177 TPS65177A g06_lvsbb1.gif
Figure 25. Buck 1 (V(IO)) Load Transient Response
TPS65177 TPS65177A g08_lvsbb1.gif
Figure 27. Buck 2 (V(CORE)) PWM Switching – Light Load
TPS65177 TPS65177A g010_lvsbb1.gif
Figure 29. Buck 2 (V(CORE)) Load Transient Response
TPS65177 TPS65177A g012_lvsbb1.gif
Figure 31. Buck 3 (V(HAVDD)) PWM – Light Load Source
TPS65177 TPS65177A g014_lvsbb1.gif
Figure 33. Buck 3 (V(HAVDD)) PWM – Normal Load Source
TPS65177 TPS65177A g016_lvsbb1.gif
Figure 35. BUCK 3 (V(HAVDD)) Load Transient Response
TPS65177 TPS65177A g018_lvsbb1.gif
Figure 37. Boost (V(AVDD)) PWM Switching – Light Load
TPS65177 TPS65177A g020_lvsbb1.gif
Figure 39. Boost (V(AVDD)) Load Transient Response
TPS65177 TPS65177A g022_lvsbb1.gif
Figure 41. Positive Charge-Pump (V(GH)) Normal Load
TPS65177 TPS65177A g024_lvsbb1.gif
Figure 43. Negative Charge-Pump (V(GL)) Light Load
TPS65177 TPS65177A g026_lvsbb1.gif
Figure 45. Negative CP (V(GL)) Load Transient Response

8.3 System Examples

TPS65177 TPS65177A Typ.Application_Tempcomp_off.gif Figure 46. V(GH) Temperature Compensation Disabled (by I2C)
TPS65177 TPS65177A Typ.Application_GPM_off.gif Figure 47. Gate Pulse Modulation Disabled (by I2C)

For best input voltage filtering low ESR ceramic capacitors are recommended. For better input voltage filtering the capacitor values can be increased.

  • Internal logic: 100 nF close to the INVL-pin
  • Boost converter: 10 µF near the inductor
  • Buck 1 converter: 10 µF close to the INBK1-pins
  • Buck 2 converter: 4.7 µF close to the INBK2-pin (also one of the Buck 2 output capacitors can be used)
  • Buck 3 converter: 4.7 µF close to the INBK3-pin

Table 7. Input Capacitor Selection

CAPACITOR VOLTAGE RATING TEMPERATURE CHARACTERISTICS SUPPLIER(1) COMPONENT CODE
100 nF / 0402 16 V X5R Murata GRM155R61C104KA88
100 nF / 0402 16 V X5R Taiyo Yuden EMK105BJ104KV
4.7 µF / 0402 6.3 V X5R Murata GRM155R60J475ME87
4.7 µF / 0402 6.3 V X5R Taiyo Yuden JMK105BBJ475MV
4.7 µF / 0805 16 V X5R Murata GRM21BR61C475KA88
4.7 µF / 0805 16 V X5R Taiyo Yuden EMK212ABJ475KG
10 µF / 1206 16 V X5R Murata GRM31CR61C106KA88
10 µF / 1206 16 V X7R Taiyo Yuden EMK316AB7106KL
(1) See Third-Party Products disclaimer.