SLDS234B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The TPS65218D0 can be reset by holding the PB pin low for more than 8 or 15 s, depending on the value of the TRST bit. All rails are shut down by the sequencer and all register values reset to their default values. Rails not controlled by the sequencer are shut down additionally. Note that the RESET function power-cycles the device and only temporarily shuts down the output rails. Resetting the device does not lead to OFF state. If the PB_IN pin is kept low for an extended amount of time, the device continues to cycle between ACTIVE and RESET state, entering RESET every 8 or 15 s.
The device is also reset if a PGOOD or OTS fault occurs. The TPS65218D0 remains in the recovery state until the fault is removed, at which time it transitions back to the ACTIVE state.