SLVSD80D
November 2015 – May 2021
TPS65235
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Boost Converter
7.3.2
Linear Regulator and Current Limit
7.3.3
Boost Converter Current Limit
7.3.4
Charge Pump
7.3.5
Slew Rate Control
7.3.6
Short Circuit Protection, Hiccup and Overtemperature Protection
7.3.7
Tone Generation
7.3.8
Tone Detection
7.3.9
Disable and Enable
7.3.10
Component Selection
7.3.10.1
Boost Inductor
7.3.10.2
Capacitor Selection
7.3.10.3
Surge Components
7.3.10.4
Consideration for Boost Filtering and LNB Noise
7.4
Device Functional Modes
7.5
Programming
7.5.1
Serial Interface Description
7.5.2
TPS65235 I2C Update Sequence
7.6
Register Maps
7.6.1
Control Register 1 (address = 0x00H) [reset = 00010000]
7.6.2
Control Register 2 (address = 0x01H) [reset = 0000101]
7.6.3
Status Register (address = 0x02H) [reset = x0100000]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application for DiSEqc1.x Support
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.2.4
Typical Application for DiSEqc2.x Support
8.2.4.1
Design Requirements
8.2.4.2
Detailed Design Procedure
8.2.4.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RUK|20
MPQF220D
Thermal pad, mechanical data (Package|Pins)
RUK|20
QFND191D
Orderable Information
slvsd80d_oa
slvsd80d_pm
7.2
Functional Block Diagram