SLVSD80D November   2015  – May 2021 TPS65235

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Disable and Enable
      10. 7.3.10 Component Selection
        1. 7.3.10.1 Boost Inductor
        2. 7.3.10.2 Capacitor Selection
        3. 7.3.10.3 Surge Components
        4. 7.3.10.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
      2. 7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
      3. 7.6.3 Status Register (address = 0x02H) [reset = x0100000]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application for DiSEqc1.x Support
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application for DiSEqc2.x Support
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

MINNOMMAXUNIT
OUTPUT VOLTAGE
tr, tf13 V to 18 V transition rising falling timeC(TCAP) = 22 nF2ms
tON(min)Minimum on time for the Low side FET75102130ns
TONE
tr(tone)Tone rise timeIO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0		11µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has 44 kHz input		5.5µs
tf(tone)Tone fall timeIO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0		10.8µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has 44 kHz input		5.4µs
PROTECTION
tONOvercurrent protection ON TimeTIMER=02.33.755.52ms
tOFFOvercurrent protection OFF TimeTIMER=098.5118133.5ms
I2C INTERFACE
tBUFBus free time between a STOP and START condition1.3µs
tHD_STAHold time (repeated) START condition0.6µs
tSU_STOSetup time for STOP condition0.6µs
tLOWLOW period of the SCL clock1.3µs
tHIGHHIGH period of the SCL clock0.6µs
tSU_STASetup time for a repeated START condition0.6µs
tSU_DATData setup time0.1µs
tHD_DATData hold time00.9µs
tRCLRise time of SCL signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tRCL1Rise time of SCL Signal after a Repeated START condition and after an acknowledge BITCapacitance of one bus line (pF)20 + 0.1 CB300ns
tFCLFall time of SCL signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tRDARise time of SDA signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
tFDAFall time of SDA signalCapacitance of one bus line (pF)20 + 0.1 CB300ns
CBCapacitance of one bus line(SCL and SDA)400pF