SLVSD50D March   2016  – June 2017 TPS65320C-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Regulator
        1. 7.3.1.1  Fixed-Frequency PWM Control
        2. 7.3.1.2  Slope Compensation Output
        3. 7.3.1.3  Pulse-Skip Eco-mode™ Control Scheme
        4. 7.3.1.4  Dropout Mode Operation and Bootstrap Voltage (BOOT)
        5. 7.3.1.5  Error Amplifier
        6. 7.3.1.6  Voltage Reference
        7. 7.3.1.7  Adjusting the Output Voltage
        8. 7.3.1.8  Soft-Start and Tracking Pin (SS/TR)
        9. 7.3.1.9  Overload-Recovery Circuit
        10. 7.3.1.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
        11. 7.3.1.11 Overcurrent Protection and Frequency Shift
        12. 7.3.1.12 Selecting the Switching Frequency
        13. 7.3.1.13 How to Interface to RT/CLK Pin
        14. 7.3.1.14 Overvoltage Transient Protection
        15. 7.3.1.15 Small-Signal Model for Loop Response
        16. 7.3.1.16 Simple Small-Signal Model for Peak-Current Mode Control
        17. 7.3.1.17 Small-Signal Model for Frequency Compensation
      2. 7.3.2 LDO Regulator
        1. 7.3.2.1 Charge-Pump Operation
        2. 7.3.2.2 Low-Voltage Tracking
        3. 7.3.2.3 Adjusting the Output Voltage
      3. 7.3.3 Thermal Shutdown
      4. 7.3.4 Power-Good Output, nRST
      5. 7.3.5 Enable and Undervoltage Lockout
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Soft-Start Discharge
      2. 8.1.2 Passive Discharge Through a Resistor in Parallel With the SS Capacitor
      3. 8.1.3 Active Discharge Through A NPN Transistor
    2. 8.2 Typical Application
      1. 8.2.1 2-MHzSwitching Frequency, 9-V to 16-V Input, 5-V Output Buck Regulator, 3.3-V Output LDO Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency Selection for the Buck Regulator
          2. 8.2.1.2.2  Output Inductor Selection for the Buck Regulator
          3. 8.2.1.2.3  Output Capacitor Selection for the Buck Regulator
          4. 8.2.1.2.4  Catch Diode Selection for the Buck Regulator
          5. 8.2.1.2.5  Input Capacitor Selection for the Buck Regulator
          6. 8.2.1.2.6  Soft-Start Capacitor Selection for the Buck Regulator
          7. 8.2.1.2.7  Bootstrap Capacitor Selection for the Buck Regulator
          8. 8.2.1.2.8  Output Voltage and Feedback Resistor Selection for the Buck Regulator
          9. 8.2.1.2.9  Frequency Compensation Selection for the Buck Regulator
          10. 8.2.1.2.10 LDO Regulator
          11. 8.2.1.2.11 Power Dissipation
            1. 8.2.1.2.11.1 Power Dissipation Losses of the Buck Regulator
          12. 8.2.1.2.12 Power Dissipation Losses of the LDO Regulator
          13. 8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
14-Pin HTSSOP With Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between the BOOT and SW pins. Every time the high-side MOSFET (HS-FET) turns off, the capacitor is recharged. In case of drop-out mode, the FET is forced off every 8th clock-cycle to refresh the boot voltage.
COMP 12 O The COMP pin is the error-amplifier output of the buck regulator, and the input to the output switch-current comparator of the buck regulator. Connect frequency-compensation components to the COMP pin.
EN1 8 I The EN1 pin is the enable and disable input for the buck regulator (high-voltage tolerant) and is internally pulled to ground. Pull this pin up externally to enable the buck regulator.
EN2 7 I The EN2 pin is the enable and disable input for the LDO regulator (high-voltage tolerant) and is internally pulled to ground. Pull this pin up externally to enable the LDO regulator.
FB1 11 I The FB1 pin is the feedback pin of the buck regulator. Connect an external resistive divider between the buck regulator output, the FB2 pin, and the GND pin to set the desired output voltage of the buck regulator.
FB2 5 I The FB2 pin is the feedback pin of the LDO regulator. Connect an external resistive divider between the LDO_OUT pin, the FB2 pin, and the GND pin to set the desired output voltage of the LDO regulator.
GND 13 — This pin is the ground pin.
LDO_OUT 4 O This pin is the LDO regulator output.
nRST 6 O The nRST pin is the active-low, push-pull reset output of the LDO regulator. Connect this pin with an external bias voltage through an external resistor. This pin is asserted high after the LDO regulator begins regulating.
RT/CLK 9 I Connect this pin to an external resistor to ground to program the switching frequency of the buck regulator. An alternative option is to feed an external clock to provide a reference for the switching frequency of the buck regulator.
SS 10 I Connect this pin to an external capacitor to ground which sets the soft-start time of the buck regulator.
SW 14 I The SW pin is the source node of the internal high-side MOSFET of the buck regulator.
VIN 2 — The VIN pin is the input supply pin for the internal biasing and high-side MOSFET of the buck regulator.
VIN_LDO 3 — The VIN_LDO pin is the input supply pin for the LDO regulator.
Exposed PowerPAD — Electrically connect the PowerPAD to ground and solder to the ground plane of the PCB for thermal performance.