5.3.1.1 System Power Up

Figure 5-2 System Power Up State Diagram

5.3.1.2 System Operation Using Push Button Switch

Figure 5-3 Push Button State Diagram

5.3.1.3 System Operation Using Slider Switch

Figure 5-4 System Operation Using Slider Switch

5.3.2.1 Battery and TS Detection

To detect and determine between a good or damaged battery, the device checks for a short circuit on the BAT pin by sourcing I_BAT(SC) to the battery and monitoring the voltage on the BAT pin. While sourcing this current if the BAT pin voltage exceeds V_BAT(SC), a battery has been detected. If the voltage stays below the V_BAT(SC) level, the battery is presumed to be damaged and not safe to charge.

The device will also check for the presence of a 10-kΩ NTC thermistor attached to the TS pin of the device. The check for the NTC thermistor on the TS pin is done much like the battery detection feature described previously. The voltage on the TS pin is compared against a defined level and if it is found to be above the threshold, the NTC thermistor is assumed to be disconnected or not used in the system. To reduce the system quiescent current, the NTC thermistor temperature sensing function is only enabled when the device is charging and when the thermistor has been detected.

Figure 5-5 Thermistor Detection and Circuit

5.3.2.2 Battery Charging

The battery is charged in three phases: conditioning pre-charge, constant-current fast charge (current regulation), and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. Figure 5-6 shows what happens in each of the three charge phases:

Figure 5-6 Battery Charge Phases

In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the V_LOWV threshold, the battery is charged with the fast-charge current (I_CHG). As the battery voltage reaches V_BAT(REG), the battery is held at a constant voltage of V_BAT(REG) and the charge current tapers off as the battery approaches full charge. When the battery current reaches I_TERM, the charger indicates charging is done by making the nCHG_STAT pin high impedance. Note that termination detection is disabled whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the DPM loop, or the V_IN(LOWV) loop.

5.3.2.3 Charger Status (nCHG_STAT Pin)

The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The table below details the status of the nCHG_STAT pin for various operating states of the charger.

Table 5-2 VLDO_SET Functionality

5.3.3.1 LDO Internal Current Limit

The internal current limit feature helps protect the LDO regulator during fault conditions. During current limit, the output sources a fixed amount of current, defined in the Electrical Characteristics table. The voltage on the output in this stage can not be regulated and will be V_OUT = I_LIMIT × R_LOAD. The pass transistor integrated into the LDO will dissipate power, (V_IN - V_OUT) × I_LIMIT, until the device enters thermal shutdown. In thermal shutdown the device will enter the SLEEP / POWER OFF state which means that the LDO will then be disabled and shut off.

5.3.4.1 Boost Thermal Shutdown

An internal thermal shutdown mode is implemented in the boost converter that shuts down the device if the typical junction temperature of 105°C is exceeded. If the device is in thermal shutdown mode, the main switch of the boost is open and the device enters the SLEEP / POWER OFF state.

5.3.4.2 Boost Load Disconnect

When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters by eliminating any DC content (see Section 5.3.5.1 for more information regarding the H-bridge states). The disconnection of the load is done with the H-Bridge and can be seen in the next figure (Figure 5-11).

Figure 5-11 Boost Load Disconnect

An advantage to this topology for disconnecting the load is that the boost output capacitor is charged to approximately the SYS voltage level, specifically V_SYS - V_DIODE(BST), when the boost is disabled. This design ensures that there is not a large in-rush current into the boost output capacitor when the boost is enabled. The boost operation efficiency is also increased because there is no load disconnect switch in the boost output path. A load disconnect switch would decrease efficiency because of the resistance that it would introduce.

5.3.5.1 H-Bridge Switch Control

The H-Bridge switches are controlled by the MSP430 core for system operation - specifically to control charge polarity on the LCD shutters. Depending on the state of the signals from the MSP430 core, the H-Bridge will be put into 4 different states. These states are:

• OPEN: All Switches Opened
• CHARGE+: Boost Output Voltage Present on Pins LCLP or LCRP
• CHARGE-: Boost Output Voltage Present on Pins LCLN or LCRN
• GROUNDED: High side switches are opened and low side switches are closed

Figure 5-12 H-Bridge States

Figure 5-13 H-Bridge States from Oscilloscope

5.3.6.1 SLEEP / Power Control Pin Function

The internal SLEEP signal between the power management device and the MSP430 can be used to control the power down behavior of the device. This has multiple practical applications such as a watchdog implementation for the communication between the sender (TV) and the receiver (3D glasses) or different required system on and off times; typically when the push-button press timing for an off event is a few seconds in length, programmable by software in the system MCU.

If there is a requirement that the push-button press for system on and off events are different, the SLEEP signal must be set to a logic high value (V_SLEEP > V_IH(PMIC)) upon system startup. This implementation allows the device to power down the system on the falling edge of the SLEEP signal
(when: V_SLEEP < V_IL(PMIC)).

Figure 5-14 SLEEP Signal to Force System Power Off

5.3.6.2 COMP Pin Functionality

The COMP pin is used to output a scaled down voltage level related to the battery voltage for input to the comparator of the MSP430. Applications for this COMP feature could be to generate an interrupt on the MSP430 when the battery voltage drops under a threshold and the device can then be shut down or indicate to the end user with an LED that the battery requires charging.

Figure 5-15 COMP Pin Internal Connection

Using the designed values in Table 5-4 or Table 5-5, the voltage on the COMP pin will be: V_COMP = 0.5 × V_VLDO + 300 mV. This ensures that the COMP pin voltage will be close to half of the LDO output voltage plus the LDO dropout voltage of the device. The COMP pin can also be used as an input to ADC channel A0 of the integrated MSP430 microcontroller. This is useful if greater measurement accuracy or increased functionality is desired from this function.

5.3.6.3 SW_SEL Pin Functionality

The SW_SEL pin is used to select what type of switch is connected to the SWITCH pin of the device. Selection between a push-button and a slider switch can be made based on the state of this pin.

When the push button switch type is selected, the device will debounce the SWITCH input with a 32-ms timer for both the ON and OFF events and either power on or off the device. Using the push-button switch function, the ON and OFF timings are equal; t_ON = t_OFF. If the system requirements are such that the on and off timings should be different, t_ON ≠ t_OFF, then refer to the following section for the correct system setup: Section 6.2.1.2.2.When the slider switch operation is selected, the SWITCH pin must be externally pulled up to the SYS voltage with a resistor and the output connected to the slider switch. When the SWITCH pin is pulled to ground, the device will turn on and enter the power up sequence.

5.3.6.4 SWITCH Pin

The SWITCH pin behavior is defined by the SW_SEL pin (Section 5.3.6.3) which defines the type of switch that is connected to the system; either a slider switch or push-button.

5.3.6.5 Slider Switch Behavior

If a slider switch is connected in the system then the system power state and VLDO output (which powers the internal MSP430) is defined by the state of the slider switch. If the slider is in the off position than the SWITCH pin should be connected to the SYS pin. If the slider is in the on position than the SWITCH pin should be connected to ground. Figure 5-16 details the system operation using the slider switch configuration.

Figure 5-16 SWITCH, Slider Power On-Off Behavior

5.3.6.6 Push-Button Switch Behavior

The system is powered on or off by a push-button press after a press that is greater than 32 ms. The following figures (Figure 5-17 and Figure 5-18) show the system behavior and the expected VLDO output during the normal push-button operation where the ON and OFF press timings are the same value,
t_ON = t_OFF.

Figure 5-17 SWITCH, Push-button Power On Behavior

Figure 5-18 SWITCH, Push-Button Power Off Behavior

5.5.1.1 MSP430 Recommended Operating Conditions

NOTE:

Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC of 2.2 V.

Figure 5-19 Safe Operating Area

5.5.1.2 Active Mode Supply Current Into V_CC Excluding External Current

5.5.1.3 Typical Characteristics, Active Mode Supply Current (Into V_CC)

Figure 5-20 Active Mode Current vs V_CC, T_A = 25°C

Figure 5-21 Active Mode Current vs DCO Frequency

5.5.1.4 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

1. All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.

5.5.1.5 Typical Characteristics, Low-Power Mode Supply Currents

Figure 5-22 LPM3 Current vs Temperature

Figure 5-23 LPM4 Current vs Temperature

5.5.1.6 Schmitt-Trigger Inputs, Ports Px

5.5.1.7 Leakage Current, Ports Px

5.5.1.8 Outputs, Ports Px

5.5.1.9 Output Frequency, Ports Px

5.5.1.10 Typical Characteristics, Outputs

Figure 5-24 Typical Low-Level Output Current vs Low-Level Output Voltage

Figure 5-26 Typical High-Level Output Current vs High-Level Output Voltage

Figure 5-25 Typical Low-Level Output Current vs Low-Level Output Voltage

Figure 5-27 Typical High-Level Output Current vs High-Level Output Voltage

5.5.1.11 Pin-Oscillator Frequency – Ports Px

5.5.1.12 Typical Characteristics, Pin-Oscillator Frequency

One output active at a time.

Figure 5-28 Typical Oscillating Frequency vs Load Capacitance

One output active at a time.

Figure 5-29 Typical Oscillating Frequency vs Load Capacitance

5.5.1.13 POR/Brownout Reset (BOR)⁽¹⁾

Figure 5-30 POR/Brownout Reset (BOR) vs Supply Voltage

5.5.1.14 Typical Characteristics, POR/Brownout Reset (BOR)

Figure 5-31 V_CC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal

Figure 5-32 V_CC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

5.5.1.15 DCO Frequency

5.5.1.16 Calibrated DCO Frequencies, Tolerance

5.5.1.17 Wake-Up From Lower-Power Modes (LPM3/4)

5.5.1.18 Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4

Figure 5-33 DCO Wake-Up Time From LPM3 vs DCO Frequency

5.5.1.19 Crystal Oscillator, XT1, Low-Frequency Mode

5.5.1.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

5.5.1.21 Timer_A

5.5.1.22 USCI (UART Mode)

5.5.1.23 USCI (SPI Master Mode)

Figure 5-34 SPI Master Mode, CKPH = 0

Figure 5-35 SPI Master Mode, CKPH = 1

5.5.1.24 USCI (SPI Slave Mode)

Figure 5-36 SPI Slave Mode, CKPH = 0

Figure 5-37 SPI Slave Mode, CKPH = 1

5.5.1.25 USCI (I²C Mode)

Figure 5-38 I²C Mode Timing

5.5.1.26 Comparator_A+

5.5.1.27 Typical Characteristics – Comparator_A+

Figure 5-39 V_(RefVT) vs Temperature, V_CC = 3 V

Figure 5-41 Short Resistance vs V_IN/V_CC

Figure 5-40 V_(RefVT) vs Temperature, V_CC = 2.2 V

5.5.1.28 10-Bit ADC, Power Supply and Input Range Conditions

1. The leakage current is defined in the leakage current table with Px.y/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter I_ADC10.
4. The internal reference current is supplied via terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

5.5.1.29 10-Bit ADC, Built-In Voltage Reference

5.5.1.30 10-Bit ADC, External Reference

1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

5.5.1.31 10-Bit ADC, Timing Parameters

5.5.1.32 10-Bit ADC, Linearity Parameters

5.5.1.33 10-Bit ADC, Temperature Sensor and Built-In V_MID

5.5.1.34 Flash Memory

5.5.1.35 RAM

5.5.1.36 JTAG and Spy-Bi-Wire Interface

5.5.1.37 JTAG Fuse

5.5.2.1 Description

The MSP430 integrated into the TPS65835 is from the MSP430x2xx family of ultralow-power microcontrollers. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1␣s. The list of the peripherals and modules included in this MSP430 are as follows:

• Up to 16 MHz CPU
• 16 kB Flash Memory
• 512 B RAM
• Basic Clock Module
  • Internal Frequencies up to 16 MHz with one Calibrated Frequency
  • Internal Very-Low-Power Low-Frequency (LF) Oscillator
  • 32 kHz Crystal Support
  • External Digital Clock Source
• 10-Bit ADC
  • 200-ksps Analog-to-Digital (A/D) Converter with Internal Reference, Sample-and-Hold, and Autoscan
• Comparator A+ (Comp_A+)
  • For Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion
• Timer0_A3 and Timer1_A3
  • Up to Two 16-Bit Timer_A with Three Capture/Compare Registers
• Watchdog WDT+
• USCI A0, Universal Serial Communication Interface
  • Enhanced UART Supporting Auto Baudrate Detection (LIN)
  • IrDA Encoder and Decoder
  • Synchronous SPI
  • I²C
• USCI B0, Universal Serial Communication Interface
  • Synchronous SPI
  • I²C
• JTAG / Spy-By-Wire

Figure 5-42 MSP430 Functional Block Diagram

5.5.2.2 Accessible MSP430 Pins

There are a number of internal pins connected between the MSP430 core and the power management core as well as external pins on the MSP430. Internal pins are not available externally but can be controlled by the MSP430 core in various ways. A table describing all available MSP430 pin functions (Table 5-7) along with a block diagram detailing the MSP430 core and the pin connectivity (see Figure 5-42) has been made available.

5.5.2.3 MSP430 Port Functions and Programming Options

This section details the programming options that are available for each of the pins that are accessible on the MSP430.

5.5.2.4 Operating Modes

The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM)
  • All clocks are active
• Low-power mode 0 (LPM0)
  • CPU is disabled
  • ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
  • CPU is disabled
  • ACLK and SMCLK remain active, MCLK is disabled
  • DCO's dc-generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
  • CPU is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc-generator remains enabled
  • ACLK remains active
• Low-power mode 3 (LPM3)
  • CPU is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc-generator is disabled
  • ACLK remains active
• Low-power mode 4 (LPM4)
  • CPU is disabled
  • ACLK is disabled
  • MCLK and SMCLK are disabled
  • DCO's dc-generator is disabled
  • Crystal oscillator is stopped

5.5.2.5 MSP430x2xx User's Guide

To view the user's guide for the MSP430 integrated into this device, see MSP430x2xx Family User's Guide. The list of peripherals found in this MSP430 is listed in the section: Section 5.5.2.1.