SWCS037I May   2008  – January 2015 TPS65920 , TPS65930

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Characteristics for ZCH Package
    5. 4.5 Minimum Voltages and Associated Currents
    6. 4.6 Digital I/O Electrical Characteristics
    7. 4.7 Timing Requirements and Switching Characteristics
      1. 4.7.1 Timing Parameters
      2. 4.7.2 Target Frequencies
      3. 4.7.3 I2C Timing
      4. 4.7.4 Audio Interface: TDM/I2S Protocol
        1. 4.7.4.1 I2S Right- and Left-Justified Data Format
        2. 4.7.4.2 TDM Data Format
      5. 4.7.5 JTAG Interfaces
  5. 5Detailed Description
    1. 5.1 Power Module
      1. 5.1.1 Power Providers
        1. 5.1.1.1  VDD1 DC-DC Regulator
          1. 5.1.1.1.1 VDD1 DC-DC Regulator Characteristics
          2. 5.1.1.1.2 External Components and Application Schematics
        2. 5.1.1.2  VDD2 DC-DC Regulator
          1. 5.1.1.2.1 VDD2 DC-DC Regulator Characteristics
          2. 5.1.1.2.2 External Components and Application Schematics
        3. 5.1.1.3  VIO DC-DC Regulator
          1. 5.1.1.3.1 VIO DC-DC Regulator Characteristics
          2. 5.1.1.3.2 External Components and Application Schematics
        4. 5.1.1.4  VDAC LDO Regulator
        5. 5.1.1.5  VPLL1 LDO Regulator
        6. 5.1.1.6  VMMC1 LDO Regulator
        7. 5.1.1.7  VAUX2 LDO Regulator
        8. 5.1.1.8  Output Load Conditions
        9. 5.1.1.9  Charge Pump
        10. 5.1.1.10 USB LDO Short-Circuit Protection Scheme
      2. 5.1.2 Power References
      3. 5.1.3 Power Control
        1. 5.1.3.1 Backup Battery Charger
        2. 5.1.3.2 Battery Monitoring and Threshold Detection
          1. 5.1.3.2.1 Power On/Power Off and Backup Conditions
        3. 5.1.3.3 VRRTC LDO Regulator
      4. 5.1.4 Power Consumption
      5. 5.1.5 Power Management
        1. 5.1.5.1 Boot Modes
        2. 5.1.5.2 Process Modes
          1. 5.1.5.2.1 MC021 Mode
        3. 5.1.5.3 Power-On Sequence
          1. 5.1.5.3.1 Timing Before Sequence_Start
          2. 5.1.5.3.2 Power-On Sequence
          3. 5.1.5.3.3 Power On in Slave_C021 Mode
        4. 5.1.5.4 Power-Off Sequence
          1. 5.1.5.4.1 Power-Off Sequence
    2. 5.2 Real-Time Clock and Embedded Power Controller
      1. 5.2.1 RTC
        1. 5.2.1.1 Backup Battery
      2. 5.2.2 EPC
    3. 5.3 USB Transceiver
      1. 5.3.1 Features
      2. 5.3.2 HS USB Port Timing
      3. 5.3.3 USB-CEA Carkit Port Timing
      4. 5.3.4 PHY Electrical Characteristics
        1. 5.3.4.1 HS Differential Receiver
        2. 5.3.4.2 HS Differential Transmitter
        3. 5.3.4.3 CEA/UART Driver
        4. 5.3.4.4 Pullup/Pulldown Resistors
      5. 5.3.5 OTG Electrical Characteristics
        1. 5.3.5.1 OTG VBUS Electrical Characteristics
        2. 5.3.5.2 OTG ID Electrical Characteristics
    4. 5.4 MADC
      1. 5.4.1 General Description
      2. 5.4.2 MADC Electrical Characteristics
      3. 5.4.3 Channel Voltage Input Range
        1. 5.4.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous)
    5. 5.5 LED Drivers
      1. 5.5.1 General Description
    6. 5.6 Keyboard
      1. 5.6.1 Keyboard Connection
    7. 5.7 Clock Specifications
      1. 5.7.1 Clock Features
      2. 5.7.2 Input Clock Specifications
        1. 5.7.2.1 Clock Source Requirements
        2. 5.7.2.2 HFCLKIN
        3. 5.7.2.3 32-kHz Input Clock
          1. 5.7.2.3.1 External Crystal Description
          2. 5.7.2.3.2 External Clock Description
      3. 5.7.3 Output Clock Specifications
        1. 5.7.3.1 32KCLKOUT Output Clock
        2. 5.7.3.2 HFCLKOUT Output Clock
        3. 5.7.3.3 Output Clock Stabilization Time
    8. 5.8 Debouncing Time
    9. 5.9 External Components
  6. 6Audio/Voice Module (TPS65930 Device Only)
    1. 6.1 Audio/Voice Downlink (RX) Module
      1. 6.1.1 Predriver for External Class-D Amplifier
        1. 6.1.1.1 Predriver Output Characteristics
        2. 6.1.1.2 External Components and Application Schematics
      2. 6.1.2 Vibrator H-Bridge
        1. 6.1.2.1 Vibrator H-Bridge Output Characteristics
        2. 6.1.2.2 External Components and Application Schematics
      3. 6.1.3 Carkit Output
      4. 6.1.4 Digital Audio Filter Module
      5. 6.1.5 Boost Stage
    2. 6.2 Audio Uplink (TX) Module
      1. 6.2.1 Microphone Bias Module
        1. 6.2.1.1 Analog Microphone Bias Module Characteristics
        2. 6.2.1.2 Silicon Microphone Module Characteristics
      2. 6.2.2 FM Radio/Auxiliary Input
        1. 6.2.2.1 External Components
      3. 6.2.3 Uplink Characteristics
      4. 6.2.4 Microphone Amplification Stage
      5. 6.2.5 Carkit Input
      6. 6.2.6 Digital Audio Filter Module
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device Nomenclature
    2. 7.2 Community Resources
    3. 7.3 Related Links
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Export Control Notice
    7. 7.7 Glossary
    8. 7.8 Additional Acronyms
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

Figure 3-1 shows the ball locations for the 139-ball plastic ball grid array (PBGA) package. Use this array with Table 3-1 to locate signal names and ball grid numbers.

3.1 Pin Diagram

swcs037-003.gifFigure 3-1 PBGA Bottom View

3.2 Pin Attributes

Table 3-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the table column headers:

Table 3-1 Pin Attributes

TPS65920 BALL(3) TPS65930 BALL(3) PIN
NAME(4)		 A/D
(5)		 TYPE(6) REFERENCE LEVEL
RL(7)		 PU(8) (kΩ) PD(8) (kΩ) BUFFER
STRENGTH
(mA)(9)
MIN TYP MAX MIN TYP MAX
H2 H2 ADCIN0 A I/O VINTANA1.OUT
F2 F2 ADCIN2 A I VINTANA2.OUT
M5 M5 PCHGAC A I VACCHARGER
N1 N1 VPRECH A O VPRECH
N5 N5 VBAT A Power VBAT
F7 F7 GPIO0/CD1 D I/O IO_1P8 75 100 202 59 100 144 8
JTAG.TDO D I/O IO_1P8 8
E7 E7 GPIO1 D I/O IO_1P8 75 100 202 59 100 144 2
JTAG.TMS D I IO_1P8
P2 P2 GPIO2 D I/O IO_1P8 156 220 450 59 100 144 2
TEST1 D I/O IO_1P8 2
P13 P13 GPIO15 D I/O IO_1P8 156 220 450 59 100 144 2
TEST2 D I/O IO_1P8 2
L5 L5 GPIO6 D I/O IO_1P8 75 100 202 59 100 144 2
PWM0 D O IO_1P8 4
TEST3 D I/O IO_1P8 2
J7 J7 GPIO7 D I/O IO_1P8 75 100 202 59 100 144 2
VIBRA.SYNC D I IO_1P8
PWM1 D O IO_1P8 4
TEST4 D I/O IO_1P8 2
D8 D8 SYSEN D Open drain/I IO_1P8 4.7 7.35 10 2
A4 A4 CLKEN D O IO_1P8 2
B13 B13 CLKREQ D I IO_1P8 60 100 146
C10 C10 INT1 D O IO_1P8 2
C8 C8 NRESPWRON D O IO_1P8 2
B9 B9 NRESWARM D I IO_1P8 2
D10 D10 PWRON D I VBAT
G5 G5 NSLEEP1 D I IO_1P8
E10 E10 CLK256FS(1) D O IO_1P8 2
E4 E4 VMODE1 D I IO_1P8
E8 E8 BOOT0 A/D I/O VBAT
D7 D7 BOOT1 A/D I/O VBAT
B8 B8 REGEN D Open drain VBAT 5.5 8 12 2
H4 H4 MSECURE D I IO_1P8
L13 L13 VREF A Power VREF
K13 K13 AGND A Power ground (GND) GND
B3 B3 N.C.
I2C.SR.SDA D I/O IO_1P8 2.5 3.4 12
C5 C5 VMODE2 D I IO_1P8 2
I2C.SR.SCL D I/O IO_1P8 2.5 3.4 12
C3 C3 I2C.CNTL.SDA D I/O IO_1P8 2.5 3.4 12
B4 B4 I2C.CNTL.SCL D I IO_1P8 2.5 3.4 12
See (2) H3 I2S.CLK D I/O IO_1P8 2
See (2) K2 I2S.SYNC D I/O IO_1P8 2
See (2) K4 I2S.DIN D I IO_1P8 2
See (2) K3 I2S.DOUT D O IO_1P8 2
See (2) D1 MIC.MAIN.P A I MICBIAS1.OUT
See (2) E1 MIC.MAIN.M A I MICBIAS1.OUT
A10 A10 VBAT.RIGHT A Power VBAT
See (2) A7 PreDriv.LEFT A O VINTANA2.OUT
VMID A Power VINTANA2.OUT
See (2) A8 PreDriv.RIGHT A O VINTANA2.OUT
ADCIN7 A I VINTANA2.OUT
See (2) G1 AUXR A I VINTANA2.OUT
See (2) E2 MICBIAS1.OUT A Power VINTANA2.OUT
VMIC1.OUT A Power VINTANA2.OUT
See (2) D2 MICBIAS.GND Power GND GND
G2 G2 AVSS1 A Power GND GND
L7 L7 AVSS2 A Power GND GND
N14 N14 AVSS3 A Power GND GND
C7 C7 AVSS4 A Power GND GND
M10 M10 32KCLKOUT D O IO_1P8
L14 L14 32KXIN A I IO_1P8
K14 K14 32KXOUT A O IO_1P8
A11 A11 HFCLKIN A I IO_1P8
M11 M11 HFCLKOUT D O IO_1P8
P8 P8 VBUS A Power VBUS
N10 N10 DP/UART3.RXD A I/O VBUS 2
P10 P10 DN/UART3.TXD A I/O VBUS 2
G6 G6 ID A I/O VBUS 2
K11 K11 UCLK D I IO_1P8 16
H12 H12 STP D I IO_1P8 75 100 202 59 100 144 16
GPIO9 D I/O IO_1P8 2
H11 H11 DIR D O IO_1P8 75 100 202 59 100 144 16
GPIO10 D I/O IO_1P8 2
J8 J8 NXT D O IO_1P8 75 100 202 59 100 144 16
GPIO11 D I/O IO_1P8 2
L10 L10 DATA0 D I/O IO_1P8 16
UART4.TXD D I IO_1P8
K10 K10 DATA1 D I/O IO_1P8 16
UART4.RXD D O IO_1P8 2
G11 G11 DATA2 D I/O IO_1P8 16
UART4.RTSI D I IO_1P8
G10 G10 DATA3 D I/O IO_1P8 60 100 140 60 100 140 16
UART4.CTSO D O IO_1P8 16
GPIO12 D I/O IO_1P8 75 100 202 59 100 144 16
E12 E12 DATA4 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO14 D I/O IO_1P8 2
G9 G9 DATA5 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO3 D I/O IO_1P8 2
G12 G12 DATA6 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO4 D I/O IO_1P8 2
E11 E11 DATA7 D I/O IO_1P8 75 100 202 59 100 144 16
GPIO5 D I/O IO_1P8 2
P14 P14 TEST.RESET A/D I VBAT 30 50 70
P1 P1 TESTV1 A I/O VBAT
A14 A14 TESTV2 A I/O VINTANA2.OUT
A1 A1 TEST D I IO_1P8 60 100 146
A13 A13 JTAG.TDI/ BERDATA D I IO_1P8
B14 B14 JTAG.TCK/
BERCLK		 D I IO_1P8
P7 P7 CP.IN A Power VBAT/VBUS
N7 N7 CP.CAPP A O CP.CAPP
N6 N6 CP.CAPM A O CP.CAPM
P5 P5 CP.GND A Power GND GND
N9 N9 VBAT.USB A Power VBAT
M8 M8 VUSB.3P1 A Power VUSB.3P1
L1 L1 VAUX12S.IN A Power VBAT
N2 N2 VAUX2.OUT A Power VAUX2.OUT
H14 H14 VPLLA3R.IN A Power VBAT
K12 K12 VRTC.OUT A Power VRTC.OUT
G14 G14 VPLL1.OUT A Power VPLL1.OUT
A2 A2 VMMC1.IN A Power VBAT
B1 B1 VMMC1.OUT A Power VMMC1.OUT
M7 M7 VINTUSB1P5.
OUT		 A Power VINTUSB1P5.OUT
N8 N8 VINTUSB1P8.
OUT		 A Power VINTUSB1P8.OUT
K1 K1 VDAC.IN A Power VBAT
L2 L2 VDAC.OUT A Power VDAC.OUT
H13 H13 VINT.IN A Power VBAT
H1 H1 VINTANA1.OUT A Power VINTANA1.OUT
J2 J2 VINTANA2.OUT A Power VINTANA2.OUT
A5 A5 VINTANA2.OUT A Power VINTANA2.OUT
J13 J13 VINTDIG.OUT A Power VINTDIG.OUT
D13 D13 VDD1.IN A Power VBAT
D12 D12 VDD1.IN A Power VBAT
D14 D14 VDD1.IN A Power VBAT
C11 C11 VDD1.SW A O VBAT
C12 C12 VDD1.SW A O VBAT
C13 C13 VDD1.SW A O VBAT
E14 E14 VDD1.FB A I
A12 A12 VDD1.GND A Power GND GND
B11 B11 VDD1.GND A Power GND GND
B12 B12 VDD1.GND A Power GND GND
M13 M13 VDD2.IN A Power VBAT
M12 M12 VDD2.IN A Power VBAT
N13 N13 VDD2.FB A I
N11 N11 VDD2.SW A O VBAT
P11 P11 VDD2.SW A O VBAT
N12 N12 VDD2.GND A Power GND GND
P12 P12 VDD2.GND A Power GND GND
M2 M2 VIO.IN A Power VBAT
M3 M3 VIO.IN A Power VBAT
M4 M4 VIO.FB A I
N4 N4 VIO.SW A O VBAT
P4 P4 VIO.SW A O VBAT
N3 N3 VIO.GND A Power GND GND
P3 P3 VIO.GND A Power GND GND
H9 H9 BKBAT A Power VBACK
B7 B7 IO.1P8 A Power IO_1P8
H10 H10 DGND A Power GND GND
F13 F13 LEDGND A Power GND GND
B10 B10 GPIO13 D I/O IO_1P8 75 100 202 59 100 144
LEDSYNC D I IO_1P8
E13 E13 LEDA A Open drain VBAT
VIBRA.P A Open drain VBAT
G13 G13 LEDB A Open drain VBAT
VIBRA.M A Open drain VBAT
G4 G4 KPD.C0 D Open drain IO_1P8
G3 G3 KPD.C1 D Open drain IO_1P8
E5 E5 KPD.C2 D Open drain IO_1P8
B2 B2 KPD.C3 D Open drain IO_1P8
E3 E3 KPD.C4 D Open drain IO_1P8
D5 D5 KPD.C5 D Open drain IO_1P8
K7 K7 KPD.R0 D I IO_1P8 8 10 12
H5 H5 KPD.R1 D I IO_1P8 8 10 12
K5 K5 KPD.R2 D I IO_1P8 8 10 12
H6 H6 KPD.R3 D I IO_1P8 8 10 12
K8 K8 KPD.R4 D I IO_1P8 8 10 12
L8 L8 KPD.R5 D I IO_1P8 8 10 12
(1) To avoid reflection on this pin as a result of impedance mismatch, a serial resistance of 33 Ω must be added. This clock output is available in TPS65920 also. Can be used as a clock source, if required.
(2) Balls A7, A8, D1, D2, E1, E2, G1, H3, K2, K3, and K4 are present on TPS65920 package. However, there is no function associated with these pins. These can be left floating.
(3) Ball: Ball number(s) associated with each signal(s)
(4) Pin Name: The names of all the signals that are multiplexed on each ball
(5) A/D: Analog or digital signal
(6) Type: The terminal type when a particular signal is multiplexed on the terminal:
  • I = Input
  • O = Output
(7) Reference Level: See the power module chapter for values.
(8) PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled by software.
(9) Buffer Strength: Drive strength of the associated output buffer

3.3 Signal Descriptions

Table 3-2 describes the signals on the TPS65920 and TPS65930 devices; some signals are available on multiple pins.

Table 3-2 Signal Description

MODULE SIGNAL
NAME		 DESCRIPTION TYPE TPS65920 BALL TPS65930 BALL DEFAULT CONFIGURATION AFTER RESET RELEASED FEATURES
NOT USED (1)
SIGNAL TYPE INTERNAL PULL OR NOT
ADC ADCIN0 Battery type I/O H2 H2 ADCIN0 GND
ADCIN2 General-purpose ADC input I F2 F2 ADCIN2 I GND
Charger PCHGAC AC precharge sense signal. Also used for EEPROM. I M5 M5 PCHGAC I GND
VPRECH Precharge regulator output O N1 N1 VPRECH O Cap to GND(2)
VBAT Battery voltage sensing Power N5 N5 VBAT Power VBAT
GPIOs/
JTAG		 GPIO0/CD1 GPIO0/card detection 1 I/O F7 F7 GPIO0 I PD Floating
JTAG.TDO JTAG test data output I/O
GPIO1 GPIO1 I/O E7 E7 GPIO1 I PD Floating
JTAG.TMS JTAG test mode state I
GPIO2 GPIO2 I/O P2 P2 GPIO2 I PD Floating
TEST1 TEST1 pin used in test mode only I/O
GPIO15 GPIO15 I/O P13 P13 GPIO15 I PD Floating
TEST2 TEST2 pin used in test mode only I/O
GPIO6 GPIO6 I/O L5 L5 GPIO6 I PD Floating
PWM0 Pulse width driver 0 O
TEST3 TEST3 pin used in test mode only (controlled by JTAG) I/O
GPIO7 GPIO7 I/O J7 J7 GPIO7 I PD Floating
VIBRA.SYNC Vibrator on-off synchronization I
PWM1 Pulse width driver O
TEST4 TEST4 pin used in test mode only (controlled by JTAG) I/O
CONTROL SYSEN System enable output Open drain/I D8 D8 SYSEN OD PU Floating
CLKEN Clock enable O A4 A4 CLKEN O Floating
CLKREQ Clock request I B13 B13 CLKREQ I PD GND
INT1 Output interrupt line 1 O C10 C10 INT1 O Floating
NRESPWRON Output control the NRESPWRON of the application processor O C8 C8 NRESPWRON O Floating
NRESWARM Input; detect user action on the reset button I B9 B9 NRESWARM I GND
PWRON Input; detect a control command to start or stop the system I D10 D10 PWRON I VBAT
NSLEEP1 Sleep request from device 1 I G5 G5 NSLEEP1 I GND
CLK256FS O E10 E10 CLK256FS O Floating
VMODE1 Digital voltage scaling linked with VDD1 I E4 E4 VMODE1 I GND
BOOT0 Boot pin 0 I E8 E8 BOOT0 I PD N/A
BOOT1 Boot pin 1 I D7 D7 BOOT1 I PD N/A
REGEN Enable signal for external LDO Open drain B8 B8 REGEN OD PU Floating
MSECURE Security and digital rights management I H4 H4 MSECURE I N/A
VREF VREF Reference voltage Power L13 L13 VREF Power N/A
AGND Analog ground for reference voltage Power GND K13 K13 AGND Power GND GND
I2C
Smart
Reflex		 N.C. Not connected B3 B3 Signal not functional(3) Floating
I2C.SR.SDA SmartReflex I2C data I/O
VMODE2 Digital voltage scaling linked with VDD2 I C5 C5 VMODE2 I GND
I2C.SR.SCL SmartReflex I2C data I/O
I2C I2C.CNTL.SDA General-purpose I2C data I/O C3 C3 I2C.CNTL.SDA I/O PU N/A
I2C.CNTL.SCL General-purpose I2C clock I/O B4 B4 I2C.CNTL.SCL I/O PU N/A
TDM I2S.CLK Clock signal (audio port) I/O H3 I2S.CLK I/O Floating
I2S.SYNC Synchronization signal (audio port) I/O K2 I2S.SYNC I/O Floating
I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND
I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating
ANA.MIC MIC.MAIN.P Main microphone left input (P) I D1 MIC.MAIN.P I Cap to GND
MIC.MAIN.M Main microphone left input (M) I E1 MIC.MAIN.M I Cap to GND
Hands-Free VBAT.RIGHT Battery voltage input Power A10 A10 VBAT.RIGHT Power VBAT
Headset PreDriv.LEFT Predriver output left P for external class-D amplifier O A7 VMID Power Floating
VMID Power
PreDriv.RIGHT Predriver output right P for external class-D amplifier O A8 ADCIN7 I GND
ADCIN7 General-purpose ADC input 7 I
AUX Input AUXR Auxiliary audio input right I G1 AUXR I Cap to GND
VMIC BIAS MICBIAS1.
OUT		 Analog microphone bias 1 Power E2 MICBIAS1.OUT Power Floating
VMIC1.OUT Digital microphone power supply 1 Power
MICBIAS.GND Dedicated ground for microphones Power GND D2 MICBIAS.GND Power GND GND
AVSS1 Analog ground Power GND G2 G2 AVSS1 Power GND GND
AVSS2 L7 L7 AVSS2
AVSS3 N14 N14 AVSS3
AVSS4 C7 C7 AVSS4
CLOCK 32KCLKOUT Buffered output of the 32-kHz digital clock O M10 M10 32KCLKOUT O Floating
32KXIN Input of the 32-kHz oscillator I L14 L14 32KXIN I N/A
32KXOUT Output of the 32-kHz oscillator O K14 K14 32KXOUT O Floating
HFCLKIN Input of the digital (or sine) HS clock I A11 A11 HFCLKIN I N/A
HFCLKOUT HS clock output O M11 M11 HFCLKOUT O Floating
USB PHY VBUS VBUS power rail Power P8 P8 VBUS Power N/A
DP/ UART3.RXD USB data P/USB carkit receive data/universal asynchronous receiver/transmitter (UART)3 receive data I/O N10 N10 DP/UART3.RXD I/O N/A
DN/ UART3.TXD USB data N/USB carkit transmit data/UART3 transmit data I/O P10 P10 DN/UART3.TXD I/O N/A
ID USB ID I/O G6 G6 ID I/O Connected to VRUSB3V1
ULPI UCLK HS USB clock I K11 K11 UCLK O Floating
STP HS USB stop I H12 H12 STP I PU Floating
GPIO9 GPIO9 I/O
DIR HS USB direction O H11 H11 DIR O Floating
GPIO10 GPIO10 I/O
NXT HS USB next O J8 J8 NXT O Floating
GPIO11 GPIO11 I/O
DATA0 HS USB Data0 I/O L10 L10 DATA0 O Floating
UART4.TXD UART4.TXD I
DATA1 HS USB Data1 I/O K10 K10 DATA1 O Floating
UART4.RXD UART4.RXD O
DATA2 HS USB Data2 I/O G11 G11 DATA2 O Floating
UART4.RTSI UART4.RTSI I
DATA3 HS USB Data3 I/O G10 G10 DATA3 O Floating
UART4.CTSO UART4.CTSO O
GPIO12 GPIO12 I/O
DATA4 HS USB Data4 I/O E12 E12 DATA4 O Floating
GPIO14 GPIO14 I/O
DATA5 HS USB Data5 I/O G9 G9 DATA5 O Floating
GPIO3 GPIO3 I/O
DATA6 HS USB Data6 I/O G12 G12 DATA6 O Floating
GPIO4 GPIO4 I/O
DATA7 HS USB Data7 I/O E11 E11 DATA7 O Floating
GPIO5 GPIO5 I/O
TEST TEST.RESET Reset T2 device (except power state-machine) I P14 P14 TEST.RESET I PD GND
TESTV1 Analog test I/O P1 P1 TESTV1 I/O Floating
TESTV2 Analog test I/O A14 A14 TESTV2 I/O Floating
TEST Selection between JTAG mode and application mode for JTAG/GPIOs (with PU or PD) I A1 A1 TEST I PD Floating
JTAG.TDI/ BERDATA JTAG.TDI/BERDATA I A13 A13 JTAG.TDI/ BERDATA I GND
JTAG.TCK/ BERCLK JTAG.TCK/BERCLK I B14 B14 JTAG.TCK/ BERCLK I GND
USB CP CP.IN Charge pump input voltage Power P7 P7 CP.IN Power VBAT
CP.CAPP Charge pump flying capacitor P O N7 N7 CP.CAPP O Floating
CP.CAPM Charge pump flying capacitor M O N6 N6 CP.CAPM O Floating
CP.GND Charge pump ground Power GND P5 P5 CP.GND Power GND GND
VBAT.USB VBAT.USB USB LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT Power N9 N9 VBAT.USB Power VBAT
USB.LDO VUSB.3P1 USB LDO output Power M8 M8 VUSB.3P1 Power N/A
VAUX1 VAUX12S.IN VAUX1/VAUX2/VSIM LDO input voltage Power L1 L1 VAUX12S.IN Power VBAT
VAUX2 VAUX2.OUT VAUX2 LDO output voltage Power N2 N2 VAUX2.OUT Power Floating
VPLLA3R VPLLA3R.IN Input for VPLL1, VPLL2, VAUX3, and VRTC LDOs Power H14 H14 VPLLA3R.IN Power VBAT
VRTC VRTC.OUT VRTC internal LDO output (internal use only) Power K12 K12 VRTC.OUT Power N/A
VPLL1 VPLL1.OUT LDO output voltage Power G14 G14 VPLL1.OUT Power Floating
VMMC1 VMMC1.IN VMMC1 LDO input voltage Power A2 A2 VMMC1.IN Power VBAT
VMMC1.OUT VMMC1 LDO output voltage Power B1 B1 VMMC1.OUT Power Floating
VINTUSB1
P5		 VINTUSB1P5.
OUT		 VINTUSB1P5 internal LDO output (internal use only) Power M7 M7 VINTUSB1P5. OUT Power Floating
VINTUSB1
P8		 VINTUSB1P8.
OUT		 VINTUSB1P8 internal LDO output (internal use only) Power N8 N8 VINTUSB1P8. OUT Power Floating
Video DAC VDAC.IN Input for VDAC, VINTANA1, and VINTANA2 LDOs Power K1 K1 VDAC.IN Power VBAT
VDAC.OUT Output voltage of the regulator Power L2 L2 VDAC.OUT Power Floating
VINT VINT.IN Input for VINTDIG LDO Power H13 H13 VINT.IN Power VBAT
VINTANA1 VINTANA1.
OUT		 VINTANA1 internal LDO output (internal use only) Power H1 H1 VINTANA1.OUT Power N/A
VINTANA2 VINTANA2.
OUT		 VINTANA2 internal LDO output (internal use only) Power J2 J2 VINTANA2.OUT Power N/A
VINTANA2.
OUT		 VINTANA2 internal LDO output (internal use only) Power A5 A5 VINTANA2.OUT Power N/A
VINTDIG VINTDIG.OUT VINTDIG internal LDO output (internal use only) Power J13 J13 VINTDIG.OUT Power N/A
VDD1 VDD1.IN VDD1 DC-DC input voltage Power D13 D13 VDD1.IN Power VBAT
VDD1.IN VDD1 DC-DC input voltage Power D12 D12 VDD1.IN Power VBAT
VDD1.IN VDD1 DC-DC input voltage Power D14 D14 VDD1.IN Power VBAT
VDD1.SW VDD1 DC-DC switch O C11 C11 VDD1.SW O Floating
VDD1.SW VDD1 DC-DC switch O C12 C12 VDD1.SW O Floating
VDD1.SW VDD1 DC-DC switch O C13 C13 VDD1.SW O Floating
VDD1.FB VDD1 DC-DC output voltage (feedback) I E14 E14 VDD1.FB I GND
VDD1.GND VDD1 DC-DC ground Power GND A12 A12 VDD1.GND Power GND GND
VDD1.GND VDD1 DC-DC ground Power GND B11 B11 VDD1.GND Power GND GND
VDD1.GND VDD1 DC-DC ground Power GND B12 B12 VDD1.GND Power GND GND
VDD2 VDD2.IN VDD2 DC-DC input voltage Power M13 M13 VDD2.IN Power VBAT
VDD2.IN VDD2 DC-DC input voltage Power M12 M12 VDD2.IN Power VBAT
VDD2.FB VDD2 DC-DC output voltage (feedback) I N13 N13 VDD2.FB I GND
VDD2.SW VDD2 DC-DC switch O N11 N11 VDD2.SW O Floating
VDD2.SW VDD2 DC-DC switch O P11 P11 VDD2.SW O Floating
VDD2.GND VDD2 DC-DC ground Power GND N12 N12 VDD2.GND Power GND GND
VDD2.GND VDD2 DC-DC ground Power GND P12 P12 VDD2.GND Power GND GND
VIO VIO.IN VIO DC-DC input voltage Power M2 M2 VIO.IN Power VBAT
VIO.IN VIO DC-DC input voltage Power M3 M3 VIO.IN Power VBAT
VIO.FB VIO DC-DC output voltage (feedback) I M4 M4 VIO.FB I GND
VIO.SW VIO DC-DC switch O N4 N4 VIO.SW O Floating
VIO.SW VIO DC-DC switch O P4 P4 VIO.SW O Floating
VIO.GND VIO DC-DC ground Power GND N3 N3 VIO.GND Power GND GND
VIO.GND VIO DC-DC ground Power GND P3 P3 VIO.GND Power GND GND
Backup
battery		 BKBAT Backup battery Power H9 H9 BKBAT Power GND
Digital VDD IO.1P8 TPS65920/TPS65930 device I/O input Power B7 B7 IO.1P8 Power N/A
Digital ground DGND Digital ground Power GND H10 H10 DGND Power GND GND
LED driver LEDGND LED driver ground Power GND F13 F13 LEDGND Power GND GND
GPIO13 GPIO13 I/O B10 B10 GPIO13 I PD Floating
LEDSYNC LED synchronization input I
LEDA LED leg A Open drain E13 E13 Signal not functional(3) Floating
VIBRA.P H-bridge vibrator P
LEDB LED leg B Open drain G13 G13 Signal not functional(3) Floating
VIBRA.M H-bridge vibrator M
Keypad KPD.C0 Keypad column 0 Open drain G4 G4 KPD.C0 OD Floating
KPD.C1 Keypad column 1 Open drain G3 G3 KPD.C1 OD Floating
KPD.C2 Keypad column 2 Open drain E5 E5 KPD.C2 OD Floating
KPD.C3 Keypad column 3 Open drain B2 B2 KPD.C3 OD Floating
KPD.C4 Keypad column 4 Open drain E3 E3 KPD.C4 OD Floating
KPD.C5 Keypad column 5 Open drain D5 D5 KPD.C5 OD Floating
KPD.R0 Keypad row 0 I K7 K7 KPD.R0 I PU Floating
KPD.R1 Keypad row 1 I H5 H5 KPD.R1 I PU Floating
KPD.R2 Keypad row 2 I K5 K5 KPD.R2 I PU Floating
KPD.R3 Keypad row 3 I H6 H6 KPD.R3 I PU Floating
KPD.R4 Keypad row 4 I K8 K8 KPD.R4 I PU Floating
KPD.R5 Keypad row 5 I L8 L8 KPD.R5 I PU Floating
  1. This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all functions on the muxed pin are used. But even if a function is not used, the Default Configuration After Reset Released column still applies.
    Connection criteria:
    • Analog pins:
      • For input: GND
      • For output: Floating (except VPRECH is connected to GND)
      • For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor)
    • Digital pins:
      • For input: GND (except keypad and STP are left floating)
      • For input and pullup: Floating
      • For output: Floating
      • For I/O and pullup: Floating

    N/A (not applicable): When the associated feature is mandatory for correct functioning of the TPS65920/TPS65930 device
  2. The signal VPRECH must be connected to the CPRECH capacitor to GND.
  3. Signal not functional indicates that no signal is presented on the pad after a release reset.