SLVSE83B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in Section 8.6.2, and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM.
After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion.
The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance.