The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal.

The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present.

The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin.

When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system.

The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal.

An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals.

The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits.

Figure 8-10 shows the Power-Good generation block diagram, and Figure 8-11 shows the Power-Good waveforms.

The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault:

• BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON
• New voltage level must not be set before the start-up has finished
• New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed

The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails:

• For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin
• For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V
• For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in SLVSE83-TPS65943-Q1 Power Management IC (PMIC) With 5 Bucks and 4 LDOs for Automotive Applications TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-Relevant Automotive Applications TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-Relevant Automotive Applications Features Features Applications Applications Description Description Table of Contents Table of Contents Revision History Revision History Description (continued) Description (continued) Pin Configuration and Functions Pin Configuration and Functions Digital Signal Descriptions Digital Signal Descriptions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) Low Noise Low Drop-Out Regulator (LDO4) Low Noise Low Drop-Out Regulator (LDO4) Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators Reference Generator (BandGap) Reference Generator (BandGap) Monitoring Functions Monitoring Functions Clocks, Oscillators, and PLL Clocks, Oscillators, and PLL Thermal Monitoring and Shutdown Thermal Monitoring and Shutdown System Control Thresholds System Control Thresholds Current Consumption Current Consumption Backup Battery Charger Backup Battery Charger Digital Input Signal Parameters Digital Input Signal Parameters Digital Output Signal Parameters Digital Output Signal Parameters I/O Pullup and Pulldown Resistance I/O Pullup and Pulldown Resistance I2C Interface I2C Interface Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description System Supply Voltage Monitor System Supply Voltage Monitor Power Resources (Bucks and LDOs) Power Resources (Bucks and LDOs) Buck Regulators Buck Regulators BUCK Regulator Overview BUCK Regulator Overview Multi-Phase Operation and Phase-Adding or Shedding Multi-Phase Operation and Phase-Adding or Shedding Transition Between PWM and PFM Modes Transition Between PWM and PFM Modes Multi-Phase BUCK Regulator Configurations Multi-Phase BUCK Regulator Configurations Spread-Spectrum Mode Spread-Spectrum Mode Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support BUCK Output Voltage Setting BUCK Output Voltage Setting BUCK Regulator Current Limit BUCK Regulator Current Limit SW_Bx Short-to-Ground Detection SW_Bx Short-to-Ground Detection Sync Clock Functionality Sync Clock Functionality Low Dropout Regulators (LDOs) Low Dropout Regulators (LDOs) LDOVINT LDOVINT LDOVRTC LDOVRTC LDO1, LDO2, and LDO3 LDO1, LDO2, and LDO3 Low-Noise LDO (LDO4) Low-Noise LDO (LDO4) Output Voltage Monitor and PGOOD Generation Output Voltage Monitor and PGOOD Generation Thermal Monitoring Thermal Monitoring Thermal Warning Function Thermal Warning Function Thermal Shutdown Thermal Shutdown Backup Supply Power-Path Backup Supply Power-Path General-Purpose I/Os (GPIO Pins) General-Purpose I/Os (GPIO Pins) nINT, EN_DRV, and nRSTOUT Pins nINT, EN_DRV, and nRSTOUT Pins Interrupts Interrupts RTC RTC General Description General Description Time Calendar Registers Time Calendar Registers TC Registers Read Access TC Registers Read Access TC Registers Write Access TC Registers Write Access RTC Alarm RTC Alarm RTC Interrupts RTC Interrupts RTC 32-kHz Oscillator Drift Compensation RTC 32-kHz Oscillator Drift Compensation Watchdog (WDOG) Watchdog (WDOG) Watchdog Fail Counter and Status Watchdog Fail Counter and Status Watchdog Start-Up and Configuration Watchdog Start-Up and Configuration MCU to Watchdog Synchronization MCU to Watchdog Synchronization Watchdog Disable Function Watchdog Disable Function Watchdog Sequence Watchdog Sequence Watchdog Trigger Mode Watchdog Trigger Mode WatchDog Flow Chart and Timing Diagrams in Trigger Mode WatchDog Flow Chart and Timing Diagrams in Trigger Mode 81ad66eb8a1b3631db7e13085999180a3e0c9e1f.svg 81ad66eb8a1b3631db7e13085999180a3e0c9e1f.svg Watchdog Question-Answer Mode Watchdog Question-Answer Mode Watchdog Q&A Related Definitions Watchdog Q&A Related Definitions Question Generation Question Generation Answer Comparison Answer Comparison Sequence of the 2-bit Watchdog Answer Counter Sequence of the 2-bit Watchdog Answer Counter Watchdog Sequence Events and Status Updates Watchdog Sequence Events and Status Updates Watchdog Q&A Sequence Scenarios Watchdog Q&A Sequence Scenarios Error Signal Monitor (ESM) Error Signal Monitor (ESM) ESM Error-Handling Procedure ESM Error-Handling Procedure Level Mode Level Mode PWM Mode PWM Mode Good-Events and Bad-Events Good-Events and Bad-Events ESM Error-Counter ESM Error-Counter ESM Start-Up in PWM Mode ESM Start-Up in PWM Mode ESM Flow Chart and Timing Diagrams in PWM Mode ESM Flow Chart and Timing Diagrams in PWM Mode Device Functional Modes Device Functional Modes Device State Machine Device State Machine Fixed Device Power FSM Fixed Device Power FSM Register Resets and NVM Read at INIT State Register Resets and NVM Read at INIT State Pre-Configurable Mission States Pre-Configurable Mission States PFSM Commands PFSM Commands REG_WRITE_IMM Command REG_WRITE_IMM Command REG_WRITE_MASK_IMM Command REG_WRITE_MASK_IMM Command REG_WRITE_MASK_PAGE0_IMM Command REG_WRITE_MASK_PAGE0_IMM Command REG_WRITE_BIT_PAGE0_IMM Command REG_WRITE_BIT_PAGE0_IMM Command REG_WRITE_WIN_PAGE0_IMM Command REG_WRITE_WIN_PAGE0_IMM Command REG_WRITE_VOUT_IMM Command REG_WRITE_VOUT_IMM Command REG_WRITE_VCTRL_IMM Command REG_WRITE_VCTRL_IMM Command REG_WRITE_MASK_SREG Command REG_WRITE_MASK_SREG Command SREG_READ_REG Command SREG_READ_REG Command SREG_WRITE_IMM Command SREG_WRITE_IMM Command WAIT Command WAIT Command DELAY_IMM Command DELAY_IMM Command DELAY_SREG Command DELAY_SREG Command TRIG_SET Command TRIG_SET Command TRIG_MASK Command TRIG_MASK Command END Command END Command Configuration Memory Organization and Sequence Execution Configuration Memory Organization and Sequence Execution Mission State Configuration Mission State Configuration Pre-Configured Hardware Transitions Pre-Configured Hardware Transitions ON Requests ON Requests OFF Requests OFF Requests NSLEEP1 and NSLEEP2 Functions NSLEEP1 and NSLEEP2 Functions WKUP1 and WKUP2 Functions WKUP1 and WKUP2 Functions LP_WKUP Pins for Waking Up from LP STANDBY LP_WKUP Pins for Waking Up from LP STANDBY Error Handling Operations Error Handling Operations Power Rail Output Error Power Rail Output Error Catastrophic Error Catastrophic Error Watchdog (WDOG) Error Watchdog (WDOG) Error Warnings Warnings Device Start-up Timing Device Start-up Timing Power Sequences Power Sequences First Supply Detection First Supply Detection Register Power Domains and Reset Levels Register Power Domains and Reset Levels Multi-PMIC Synchronization Multi-PMIC Synchronization SPMI Interface System Setup SPMI Interface System Setup Transmission Protocol and CRC Transmission Protocol and CRC Operation with Transmission Errors Operation with Transmission Errors Transmitted Information Transmitted Information SPMI Target Device Communication to SPMI Controller Device SPMI Target Device Communication to SPMI Controller Device Incomplete Communication from SPMI Target Device to SPMI Controller Device Incomplete Communication from SPMI Target Device to SPMI Controller Device SPMI-BIST Overview SPMI-BIST Overview SPMI Bus during Boot BIST and RUNTIME BIST SPMI Bus during Boot BIST and RUNTIME BIST Periodic Checking of the SPMI Periodic Checking of the SPMI SPMI Message Priorities SPMI Message Priorities Control Interfaces Control Interfaces CRC Calculation for I2C and SPI Interface Protocols CRC Calculation for I2C and SPI Interface Protocols I2C-Compatible Interface I2C-Compatible Interface Data Validity Data Validity Start and Stop Conditions Start and Stop Conditions Transferring Data Transferring Data Auto-Increment Feature Auto-Increment Feature Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) Configurable Registers Configurable Registers Register Page Partitioning Register Page Partitioning CRC Protection for Configuration, Control, and Test Registers CRC Protection for Configuration, Control, and Test Registers CRC Protection for User Registers CRC Protection for User Registers Register Write Protection Register Write Protection Watchdog and ESM Configuration Registers Watchdog and ESM Configuration Registers User Registers User Registers Register Maps Register Maps TPS6593-Q1 Registers TPS6593-Q1 Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application Typical Application Powering a Processor Powering a Processor Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure VCCA VCCA Internal LDOs Internal LDOs Crystal Oscillator Crystal Oscillator Buck Input Capacitors Buck Input Capacitors Buck Output Capacitors Buck Output Capacitors Buck Inductors Buck Inductors LDO Input Capacitors LDO Input Capacitors LDO Output Capacitors LDO Output Capacitors Digital Signal Connections Digital Signal Connections Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support Device Support Device Support Third-Party Products Disclaimer Third-Party Products Disclaimer Device Nomenclature Device Nomenclature Documentation Support Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-Relevant Automotive Applications TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-Relevant Automotive Applications TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-Relevant Automotive ApplicationsTPS6593-Q1 Features A 20220110 Added Functional Safety-Compliant targetedyes B 20230522 Changed the device status from Advance Information to Production Datayes Qualified for automotive applications AEC-Q100 qualified with the following results: Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Functional Safety-Compliant Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Low-power consumption 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode Five step-down switched-mode power supply (BUCK) regulators: 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input Three low-dropout (LDO) linear regulators with configurable bypass mode 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection One low-dropout (LDO) linear regulator with low-noise performance 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection Configurable power sequence control in non-volatile memory (NVM): Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors 32-kHz crystal oscillator with option to output a buffered 32-kHz clock output Real-time clock (RTC) with alarm and periodic wake-up mechanism One SPI or two I2C control interfaces, with second I2C interface dedicated for Q&A watchdog communication Package option: 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch Features A 20220110 Added Functional Safety-Compliant targetedyes B 20230522 Changed the device status from Advance Information to Production Datayes A 20220110 Added Functional Safety-Compliant targetedyes B 20230522 Changed the device status from Advance Information to Production Datayes A 20220110 Added Functional Safety-Compliant targetedyes A20220110Added Functional Safety-Compliant targetedyes yes B 20230522 Changed the device status from Advance Information to Production Datayes B20230522 Changed the device status from Advance Information to Production Datayes yes Qualified for automotive applications AEC-Q100 qualified with the following results: Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Functional Safety-Compliant Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Low-power consumption 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode Five step-down switched-mode power supply (BUCK) regulators: 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input Three low-dropout (LDO) linear regulators with configurable bypass mode 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection One low-dropout (LDO) linear regulator with low-noise performance 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection Configurable power sequence control in non-volatile memory (NVM): Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors 32-kHz crystal oscillator with option to output a buffered 32-kHz clock output Real-time clock (RTC) with alarm and periodic wake-up mechanism One SPI or two I2C control interfaces, with second I2C interface dedicated for Q&A watchdog communication Package option: 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch Qualified for automotive applications AEC-Q100 qualified with the following results: Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Functional Safety-Compliant Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Low-power consumption 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode Five step-down switched-mode power supply (BUCK) regulators: 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input Three low-dropout (LDO) linear regulators with configurable bypass mode 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection One low-dropout (LDO) linear regulator with low-noise performance 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection Configurable power sequence control in non-volatile memory (NVM): Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors 32-kHz crystal oscillator with option to output a buffered 32-kHz clock output Real-time clock (RTC) with alarm and periodic wake-up mechanism One SPI or two I2C control interfaces, with second I2C interface dedicated for Q&A watchdog communication Package option: 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch Qualified for automotive applications AEC-Q100 qualified with the following results: Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Functional Safety-Compliant Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Low-power consumption 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode Five step-down switched-mode power supply (BUCK) regulators: 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input Three low-dropout (LDO) linear regulators with configurable bypass mode 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection One low-dropout (LDO) linear regulator with low-noise performance 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection Configurable power sequence control in non-volatile memory (NVM): Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors 32-kHz crystal oscillator with option to output a buffered 32-kHz clock output Real-time clock (RTC) with alarm and periodic wake-up mechanism One SPI or two I2C control interfaces, with second I2C interface dedicated for Q&A watchdog communication Package option: 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch Qualified for automotive applicationsAEC-Q100 qualified with the following results: Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Device operates from 3 V to 5.5 V input supply Device temperature grade 1: –40°C to +125°C ambient operating temperature range Device HBM classification level 2 Device CDM classification level C4A Device operates from 3 V to 5.5 V input supplyDevice temperature grade 1: –40°C to +125°C ambient operating temperature rangeDevice HBM classification level 2Device CDM classification level C4AFunctional Safety-Compliant Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Developed for functional safety applications Documentation to aid ISO26262 and IEC61508 system design available upon product release Systematic capability up to ASIL-D and SIL-3 Hardware integrity up to ASIL-B and SIL-2 Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply rails Watchdog with selectable trigger / Q&A mode Two error signal monitors (ESMs) with selectable level / PWM mode Thermal monitoring with high temperature warning and thermal shutdown Bit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM) Developed for functional safety applicationsDocumentation to aid ISO26262 and IEC61508 system design available upon product releaseSystematic capability up to ASIL-D and SIL-3Hardware integrity up to ASIL-B and SIL-2 ASIL-BSIL-2Input supply voltage monitor Under/overvoltage monitors and over-current monitors on all output supply railsWatchdog with selectable trigger / Q&A modeTwo error signal monitors (ESMs) with selectable level / PWM modeThermal monitoring with high temperature warning and thermal shutdownBit-integrity (CRC) error detection on internal configuration registers and non-volatile memory (NVM)Low-power consumption 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode 2 μA typical shutdown current 7 μA typical in back up supply only mode 20 μA typical in low power standby mode 2 μA typical shutdown current7 μA typical in back up supply only mode20 μA typical in low power standby modeFive step-down switched-mode power supply (BUCK) regulators: 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV steps One with 4 A, three with 3.5 A, and one with 2 A output current capability Flexible multi-phase capability for four BUCKs: up to 14 A output current from a single rail Short-circuit and over-current protection Internal soft-start for in-rush current limitation 2.2 MHz / 4.4 MHz switching frequency Ability to synchronize to external clock input 0.3 V to 3.34 V output voltage range in 5, 10, or 20-mV stepsOne with 4 A, three with 3.5 A, and one with 2 A output current capabilityFlexible multi-phase capability for four BUCKs: up to 14 A output current from a single railShort-circuit and over-current protectionInternal soft-start for in-rush current limitation2.2 MHz / 4.4 MHz switching frequencyAbility to synchronize to external clock inputThree low-dropout (LDO) linear regulators with configurable bypass mode 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode 1.7 V to 3.3 V output voltage range in bypass mode 500 mA output current capability with short-circuit and over-current protection 0.6 V to 3.3 V output voltage range with 50-mV steps in linear regulation mode1.7 V to 3.3 V output voltage range in bypass mode500 mA output current capability with short-circuit and over-current protectionOne low-dropout (LDO) linear regulator with low-noise performance 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection 1.2 V to 3.3 V output voltage range in 25-mV steps 300 mA output current capability with short-circuit and over-current protection 1.2 V to 3.3 V output voltage range in 25-mV steps300 mA output current capability with short-circuit and over-current protectionConfigurable power sequence control in non-volatile memory (NVM): Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors Configurable power-up and power-down sequences between power states Digital output signals can be included in the power sequences Digital input signals can be used to trigger power sequence transitions Configurable handling of safety-relevant errors Configurable power-up and power-down sequences between power statesDigital output signals can be included in the power sequencesDigital input signals can be used to trigger power sequence transitionsConfigurable handling of safety-relevant errors32-kHz crystal oscillator with option to output a buffered 32-kHz clock outputReal-time clock (RTC) with alarm and periodic wake-up mechanism One SPI or two I2C control interfaces, with second I2C interface dedicated for Q&A watchdog communication One two 2, with second I2C interface dedicated for Q&A watchdog communication2Package option: 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch Applications Automotive infotainment and digital cluster, navigation systems, telematics, body electronics and lighting Advanced driver assistance system (ADAS) Industrial control and automation Applications Automotive infotainment and digital cluster, navigation systems, telematics, body electronics and lighting Advanced driver assistance system (ADAS) Industrial control and automation Automotive infotainment and digital cluster, navigation systems, telematics, body electronics and lighting Advanced driver assistance system (ADAS) Industrial control and automation Automotive infotainment and digital cluster, navigation systems, telematics, body electronics and lighting Advanced driver assistance system (ADAS) Industrial control and automation Automotive infotainment and digital cluster, navigation systems, telematics, body electronics and lighting Automotive infotainment and digital clusternavigation systemstelematicsbody electronics and lighting Advanced driver assistance system (ADAS) Advanced driver assistance system (ADAS) Industrial control and automation Industrial control and automation Description The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. Device Information Table PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm See the orderable addendum at the end of the data sheet for all available packages. Functional Diagram Description The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. Device Information Table PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm See the orderable addendum at the end of the data sheet for all available packages. The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. Device Information Table PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm See the orderable addendum at the end of the data sheet for all available packages. The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current.TPS6593-Q1four3.5one Device Information Table PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm Device Information Table PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE PACKAGE BODY SIZE (NOM) PART NUMBER#GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTE #GUID-2C542363-FF8E-4FDC-AC0E-86D9A484F711/DEVINFONOTEPACKAGEBODY SIZE (NOM) TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm TPS6593-Q1 TPS6593-Q1VQFNP (56)8.00 mm × 8.00 mm See the orderable addendum at the end of the data sheet for all available packages. See the orderable addendum at the end of the data sheet for all available packages. Functional Diagram Functional Diagram Functional Diagram Functional Diagram Functional Diagram Table of Contents yes Table of Contents yes yes yes Revision History yes July 2022 September 2023 A B Revision History yes July 2022 September 2023 A B yes July 2022 September 2023 A B yesJuly 2022September 2023AB Description (continued) All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. Description (continued) All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance.500Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. 2The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state.The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply.TPS6593-Q1The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.TPS6593-Q1The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU.TPS6593-Q1 Pin Configuration and Functions A 20220527 Change pin 52 from N.C into GND.yes shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) Pin Attributes PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — Default option before NVM settings are loaded into the device. Digital Signal Descriptions Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Configurable function through NVM register setting. PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown. When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell. PP = Push-pull, OD = Open-drain. Deglitch time is only applicable when option is enabled. NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Pin Configuration and Functions A 20220527 Change pin 52 from N.C into GND.yes A 20220527 Change pin 52 from N.C into GND.yes A 20220527 Change pin 52 from N.C into GND.yes A20220527Change pin 52 from N.C into GND.yes yes shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) Pin Attributes PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — Default option before NVM settings are loaded into the device. shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View) Pin Attributes PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — Default option before NVM settings are loaded into the device. Pin Attributes PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — Pin Attributes PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — PIN I/O DESCRIPTION CONNECTION IF NOT USED NAME NO. PIN I/O DESCRIPTION CONNECTION IF NOT USED PINI/ODESCRIPTIONCONNECTION IF NOT USED NAME NO. NAMENO. STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B5 35 I Power input for BUCK5 VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B5 34 O Switch node of BUCK5 Floating LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO4 7 O LDO4 output voltage Floating LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KOUT 39 O 32-KHz crystal oscillator output Floating SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground GND 52 — Analog ground — nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — REFGND1 5 — System reference ground — REFGND2 6 — System reference ground — VBACKUP 36 I Backup power source input pin Ground VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — STEP-DOWN CONVERTERS (BUCKs) STEP-DOWN CONVERTERS (BUCKs) FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B122IOutput voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration.Ground FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground FB_B221IOutput voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration.Ground FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground FB_B349IOutput voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration.Ground FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground FB_B450IOutput voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration.Ground FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground FB_B537IOutput voltage-sense (feedback) input for BUCK5Ground PVIN_B1 26 I Power input for BUCK1 VCCA PVIN_B126IPower input for BUCK1VCCA PVIN_B2 17 I Power input for BUCK2 VCCA PVIN_B217IPower input for BUCK2VCCA PVIN_B3 45 I Power input for BUCK3 VCCA PVIN_B345IPower input for BUCK3VCCA PVIN_B4 54 I Power input for BUCK4 VCCA PVIN_B454IPower input for BUCK4VCCA PVIN_B5 35 I Power input for BUCK5 VCCA PVIN_B535IPower input for BUCK5VCCA SW_B1 27 O Switch node of BUCK1 Floating SW_B127OSwitch node of BUCK1Floating SW_B1 28 O Switch node of BUCK1 Floating SW_B128OSwitch node of BUCK1Floating SW_B2 15 O Switch node of BUCK2 Floating SW_B215OSwitch node of BUCK2Floating SW_B2 16 O Switch node of BUCK2 Floating SW_B216OSwitch node of BUCK2Floating SW_B3 43 O Switch node of BUCK3 Floating SW_B343OSwitch node of BUCK3Floating SW_B3 44 O Switch node of BUCK3 Floating SW_B344OSwitch node of BUCK3Floating SW_B4 55 O Switch node of BUCK4 Floating SW_B455OSwitch node of BUCK4Floating SW_B4 56 O Switch node of BUCK4 Floating SW_B456OSwitch node of BUCK4Floating SW_B5 34 O Switch node of BUCK5 Floating SW_B534OSwitch node of BUCK5Floating LOW-DROPOUT REGULATORS LOW-DROPOUT REGULATORS PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA PVIN_LDO310IPower input voltage for LDO3 regulatorVCCA PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA PVIN_LDO48IPower input voltage for LDO4 regulatorVCCA PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA PVIN_LDO1212IPower input voltage for LDO1 and LDO2 regulatorVCCA VOUT_LDO1 13 O LDO1 output voltage Floating VOUT_LDO113OLDO1 output voltageFloating VOUT_LDO2 11 O LDO2 output voltage Floating VOUT_LDO211OLDO2 output voltageFloating VOUT_LDO3 9 O LDO3 output voltage Floating VOUT_LDO39OLDO3 output voltageFloating VOUT_LDO4 7 O LDO4 output voltage Floating VOUT_LDO47OLDO4 output voltageFloating LOW-DROPOUT REGULATORS (INTERNAL) LOW-DROPOUT REGULATORS (INTERNAL) VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVINT2OLDOVINT output for connecting to the filtering capacitor. Not for external loading.— VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. — VOUT_LDOVRTC3OLDOVRTC output for connecting to the filtering capacitor. Not for external loading.— CRYSTAL OSCILLATOR CRYSTAL OSCILLATOR OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating OSC32KCAP40OFiltering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor.Floating OSC32KIN 38 I 32-KHz crystal oscillator input Ground OSC32KIN38I32-KHz crystal oscillator inputGround OSC32KOUT 39 O 32-KHz crystal oscillator output Floating OSC32KOUT39O32-KHz crystal oscillator outputFloating SYSTEM CONTROL SYSTEM CONTROL AMUXOUT 1 O Buffered bandgap output Floating AMUXOUT1OBuffered bandgap outputFloating EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating EN_DRV29OEnable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0').Floating GPIO1 32 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO132I/OPrimary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground IAlternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up).2Ground I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground IAlternative function: CS_SPI, which is the SPI chip enable signal.Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating OAlternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low).Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO2 33 I/O Primary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO233I/OPrimary function: General-purpose input and output When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground I/OAlternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up).2Ground O Alternative function: SDO_SPI, which is the SPI output data signal. Floating OAlternative function: SDO_SPI, which is the SPI output data signal.Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground IAlternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode.Ground I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO3 46 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO346I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating IAlternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low).Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating OAlternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground IAlternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states.Ground GPIO4 47 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO447I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating OAlternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground IAlternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states.Ground GPIO5 23 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO523I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating I/OAlternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO6 24 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO624I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating I/OAlternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO7 18 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO718I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating IAlternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low).Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO8 41 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO841I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating OAlternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device.Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating IAlternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function.Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating OAlternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO9 19 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO919I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating OAlternative function: PGOOD, which is the indication signal for valid regulator output voltages and currentsFloating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating OAlternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK.Floating I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating IAlternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO10 42 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO1042I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating IAlternative function: SYNCCLKIN, which is the external switching clock input for BUCK.Floating O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating OAlternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK.Floating O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating OAlternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock.Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GPIO11 53 I/O Primary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator. Input: Ground Output: Floating GPIO1153I/OPrimary function: General-purpose input and output. When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.Input: Ground Output: Floating I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground IAlternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode.Ground O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating OAlternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low).Floating I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground IAlternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low).Ground I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground IAlternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states.Ground GND 52 — Analog ground — GND52—Analog ground— nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating nINT14OMaskable interrupt output request to the host processor (Active Low)Floating nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating nPWRON/ENABLE20INPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarityFloating I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground INPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the deviceGround nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating nRSTOUT25OMCU reset or power on reset output (Active Low)Floating SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground SCL_I2C1/SCK_SPI31IIf SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup)2Ground I If I2C is the default interface: CLK_SPI - SPI clock signal Ground IIf I2C is the default interface: CLK_SPI - SPI clock signal2Ground SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground SDA_I2C1/SDI_SPI30I/OIf SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup)2Ground I If I2C is the default interface: SDI_SPI - SPI input data signal Ground IIf I2C is the default interface: SDI_SPI - SPI input data signal2Ground POWER SUPPLIES AND REFERENCE GROUNDS POWER SUPPLIES AND REFERENCE GROUNDS GND 51 I Analog ground — GND51IAnalog ground— PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. — PGND/ThermalPad——Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias.— REFGND1 5 — System reference ground — REFGND15—System reference ground— REFGND2 6 — System reference ground — REFGND26—System reference ground— VBACKUP 36 I Backup power source input pin Ground VBACKUP36IBackup power source input pinGround VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks — VCCA4IAnalog input voltage for the internal LDOs and other internal blocks— VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage — VIO_IN48IDigital supply input for GPIOs and I/O supply voltage— Default option before NVM settings are loaded into the device. Default option before NVM settings are loaded into the device. Digital Signal Descriptions Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Configurable function through NVM register setting. PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown. When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell. PP = Push-pull, OD = Open-drain. Deglitch time is only applicable when option is enabled. NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Digital Signal Descriptions Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Configurable function through NVM register setting. PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown. When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell. PP = Push-pull, OD = Open-drain. Deglitch time is only applicable when option is enabled. NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Configurable function through NVM register setting. PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown. When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell. PP = Push-pull, OD = Open-drain. Deglitch time is only applicable when option is enabled. NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Signal Descriptions SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 Control Register Bits SIGNAL NAMEI/OThreshold LevelINPUT TYPE SELECTIONOUTPUT TYPE SELECTIONInternal PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556RECOMMENDED EXTERNAL PU/PD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE826556Control Register Bits Power Domain DEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 Power Domain Push-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 Power DomainDEGLITCH TIME#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE829213Power DomainPush-pull/Open-drain#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE8284784 nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN nINT Output VOL(nINT) VCCA OD None PU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL nPWRON (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(VCCA), VIH(VCCA) IL(VCCA),IH(VCCA)VRTC50 ms400 kΩ PU to VCCANoneNPWRON_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(VCCA), VIH(VCCA) VRTC 8 µs 400 kΩ SPU to VCCA, or 400 kΩ SPD to GND None NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL ENABLE (Selectable function of nPWRON/ENABLE pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(VCCA), VIH(VCCA) IL(VCCA),IH(VCCA)VRTC8 µs400 kΩ SPU to VCCA, or 400 kΩ SPD to GNDNoneNPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL EN_DRV Output VOL(EN_DRV) VCCA/ PVIN_B1 PP 10 kΩ High-side to VCCA None ENABLE_DRV EN_DRVOutputVOL(EN_DRV) OL(EN_DRV)VCCA/ PVIN_B1PP10 kΩ High-side to VCCANoneENABLE_DRV SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTHigh-speed mode: 10 ns All other modes: 50 nsNonePU to VIOI2C or SPI selection from NVM-configuration #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354Input/outputVIL(DIG), VIH(DIG), VOL(VIO)_20mA IL(DIG),IH(DIG),OL(VIO)_20mAVINTHigh-speed mode: 10 ns All other modes: 50 nsVIOODNonePU to VIOI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C1_HS#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT High-speed mode: 10 ns All other modes: 50 ns None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL SCL_I2C2 (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTHigh-speed mode: 10 ns All other modes: 50 nsNonePU to VIOI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO1_SEL#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA VINT High-speed mode: 10 ns All other modes: 50 ns VIO OD None PU to VIO I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL SDA_I2C2 (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354Input/outputVIL(DIG), VIH(DIG), VOL(VIO)_20mA IL(DIG),IH(DIG),OL(VIO)_20mAVINTHigh-speed mode: 10 ns All other modes: 50 nsVIOODNonePU to VIOI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F I2C2_HS GPIO2_SEL#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTNoneNoneNoneI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTNoneNoneNoneI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL CS_SPI (Selectable function of GPIO1)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTNoneNoneNoneI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO1_SEL#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO)_20mA, VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ None None I2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL SDO_SPI (Selectable function of GPIO2)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354OutputVOL(VIO)_20mA, VOH(VIO) OL(VIO)_20mA,OH(VIO)VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 / HiZ#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470NoneNoneI2C or SPI selection from NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO2_SEL#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN SCLK_SPMI (Configurable function of GPIO5)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354Output for SPMI controller device, input for SPMI peripheral deviceVIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) IL(DIG),IH(DIG),OL(DIG)_20mA,OH(DIG)VINTNoneVINTPP400 kΩ PD to GNDNone NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO5_SEL GPIO5_PU_PD_EN#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN SDATA_SPMI (Configurable function of GPIO6)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354Input/outputVIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) IL(DIG),IH(DIG),OL(DIG)_20mA,OH(DIG)VINTNoneVINTPP / HiZ400 kΩ PD to GNDNone NVM-configuration#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F GPIO6_SEL GPIO6_PU_PD_EN#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/GUID-9CA8DBD9-8831-4C77-B917-96043C6C2C2F nINT Output VOL(nINT) VCCA OD None PU to VCCA nINTOutputVOL(nINT) OL(nINT)VCCAODNonePU to VCCA nRSTOUT Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) NRSTOUT_OD nRSTOUTOutputVOL(nRSTOUT) OL(nRSTOUT)VCCA/ VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82847010 kΩ Pull-Up to VIO if configured as Push-PullPU to VIO if Open-drain (driven low if no VINT)NRSTOUT_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(nRSTOUT) VCCA/ VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain (driven low if no VINT) GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD nRSTOUT_SoC (Configurable function of GPIO1 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354OutputVOL(nRSTOUT) OL(nRSTOUT)VCCA/ VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82847010 kΩ Pull-Up to VIO if configured as Push-PullPU to VIO if Open-drain (driven low if no VINT)GPIO1_SEL GPIO1_OD GPIO11_SEL GPIO11_OD PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD None PU to VIO if Open-drain GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x PGOOD (Configurable function of GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354OutputVOL(VIO), VOH(VIO) OL(VIO),OH(VIO)VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470NonePU to VIO if Open-drainGPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL nERR_MCU (Configurable function of GPIO7)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINT8 µs400 kΩ PD to GNDNoneGPIO7_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL nERR_SoC (Configurable function of GPIO3)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VRTC15 µs400 kΩ PD to GNDNoneGPIO3_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL GPIO9_SEL DISABLE_WDOG (Configurable function of GPIO8 and GPIO9)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINT30 µs400 kΩ PD to GNDPU to VIOGPIO8_SEL GPIO9_SEL TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN TRIG_WDOG (Configurable function of GPIO2 and GPIO11)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINT30 µs400 kΩ SPD to GNDNoneGPIO2_SEL GPIO2_PU_PD_EN GPIO11_SEL GPIO11_PU_PD_EN nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP1 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)GPIO3 or 4: VRTC other GPIOs: VINT8 µsGPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIONoneGPIOn_SEL GPIOn_PU_PD_EN NSLEEP1B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) GPIO3 or 4: VRTC other GPIOs: VINT 8 µs GPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIO None GPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B nSLEEP2 (Configurable function of all GPIO pins)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)GPIO3 or 4: VRTC other GPIOs: VINT8 µsGPIO3 or 4: 400 kΩ SPU to VRTC GPIO5 or 6: 400 kΩ SPU to VINT all other GPIOs: 400 kΩ SPU to VIONoneGPIOn_SEL GPIOn_PU_PD_EN NSLEEP2B WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP1 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINT8 µsGPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GNDNoneGPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT 8 µs GPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GND None GPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL WKUP2 (Configurable function of all GPIO pins except GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINT8 µsGPIO5 or 6: 400 kΩ SPU to VINT or 400 kΩ SPD to GND all other GPIOs: 400 kΩ SPU to VIO or 400 kΩ SPD to GNDNoneGPIOn_SEL GPIOn_DEGLITCH_EN GPIOn_PU_PD_EN GPIOn_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP1 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VRTC8 µs, no deglitch in LP_STANDBY state400 kΩ SPU to VRTC, or 400 kΩ SPD to GNDNoneGPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VRTC 8 µs, no deglitch in LP_STANDBY state 400 kΩ SPU to VRTC, or 400 kΩ SPD to GND None GPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL LP_WKUP2 (Configurable function of GPIO3 and GPIO4)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VRTC8 µs, no deglitch in LP_STANDBY state400 kΩ SPU to VRTC, or 400 kΩ SPD to GNDNoneGPIO3,4_SEL GPIO3,4_DEGLITCH_EN GPIO3,4_PU_PD_EN GPIO3,4_PU_SEL GPIO1 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO1Input/outputVIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) IL(DIG),IH(DIG),OL(VIO)_20mA,OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO1_DIRInput: GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL Output: GPIO1_OD GPIO2 Input/output VIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO2Input/outputVIL(DIG), VIH(DIG), VOL(VIO)_20mA, VOH(VIO) IL(DIG),IH(DIG),OL(VIO)_20mA,OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO2_DIRInput: GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL Output: GPIO2_OD GPIO3 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO3Input/outputVIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) IL(DIG),IH(DIG),OL(DIG),OH(DIG)VRTC8 µsVINTPP or OD400 kΩ SPU to VINT, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO3_DIRInput: GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL Output: GPIO3_OD GPIO4 Input/output VIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO4Input/outputVIL(DIG), VIH(DIG), VOL(DIG), VOH(DIG) IL(DIG),IH(DIG),OL(DIG),OH(DIG)VRTC8 µsVINTPP or OD400 kΩ SPU to VINT, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO4_DIRInput: GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL Output: GPIO4_OD GPIO5 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO5Input/outputVIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) IL(DIG),IH(DIG),OL(DIG)_20mA,OH(DIG)VINT8 µsVINTPP or OD400 kΩ SPU to VINT, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO5_DIRInput: GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL Output: GPIO5_OD GPIO6 Input/output VIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO6Input/outputVIL(DIG), VIH(DIG), VOL(DIG)_20mA, VOH(DIG) IL(DIG),IH(DIG),OL(DIG)_20mA,OH(DIG)VINT8 µsVINTPP or OD400 kΩ SPU to VINT, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO6_DIRInput: GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL Output: GPIO6_OD GPIO7 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO7Input/outputVIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) IL(DIG),IH(DIG),OL(VIO),OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO7_DIRInput: GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL Output: GPIO7_OD GPIO8 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO8Input/outputVIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) IL(DIG),IH(DIG),OL(VIO),OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO8_DIRInput: GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL Output: GPIO8_OD GPIO9 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO P#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO9Input/outputVIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) IL(DIG),IH(DIG),OL(VIO),OH(VIO)VINT8 µsVIOP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470P or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO9_DIRInput: GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL Output: GPIO9_OD GPIO10 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO10Input/outputVIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) IL(DIG),IH(DIG),OL(VIO),OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO10_DIRInput: GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL Output: GPIO10_OD GPIO11 Input/output VIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) VINT 8 µs VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD 400 kΩ SPU to VIO, or 400 kΩ SPD to GND PU to VIO if Open-drain GPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD GPIO11Input/outputVIL(DIG), VIH(DIG), VOL(VIO), VOH(VIO) IL(DIG),IH(DIG),OL(VIO),OH(VIO)VINT8 µsVIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 or OD#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470400 kΩ SPU to VIO, or 400 kΩ SPD to GNDPU to VIO if Open-drainGPIO11_DIRInput: GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL Output: GPIO11_OD SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Input VIL(DIG), VIH(DIG) VINT None 400 kΩ SPD to GND None GPIO10_SELGPIO10_PU_PD_EN SYNCCLKIN (Configurable function of GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354InputVIL(DIG), VIH(DIG) IL(DIG),IH(DIG)VINTNone400 kΩ SPD to GNDNoneGPIO10_SELGPIO10_PU_PD_EN SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output VOL(VIO), VOH(VIO) VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO8_SELGPIO9_SELGPIO10_SEL SYNCCLKOUT (Configurable function of GPIO8, GPIO9, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354OutputVOL(VIO), VOH(VIO) OL(VIO),OH(VIO)VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470NoneNoneGPIO8_SELGPIO9_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 Output GPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) GPIO3 or 4: VRTC GPIO8 or 10: VIO PP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 None None GPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL CLK32KOUT (Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE82354OutputGPIO3 or 4: VOL(DIG), VOH(DIG) GPIO8 or 10: VOL(VIO), VOH(VIO) OL(DIG),OH(DIG)OL(VIO),OH(VIO)GPIO3 or 4: VRTC GPIO8 or 10: VIOPP#GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470 #GUID-78BBC6BF-2013-4FCF-A8D2-E74BFAE636F7/SLVSE828470NoneNoneGPIO3_SELGPIO4_SELGPIO8_SELGPIO10_SEL Configurable function through NVM register setting. PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown. When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell. PP = Push-pull, OD = Open-drain. Deglitch time is only applicable when option is enabled. NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Configurable function through NVM register setting.PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown.When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell.PP = Push-pull, OD = Open-drain.Deglitch time is only applicable when option is enabled.NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation. Specifications A 20220110 Section 8.8 Specifications - BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators: Change typical value for parameter 4.112 (from 300-mA to 420-mA), parameter 4.113 (from 200-mA to 100-mA), parameter 4.122 (from 250-mA to 370-mA), parameter 4.123 (from 150-mA to 30-mA), parameter 4.131 (from 400-mA to 310-mA), parameter 4.132 (from 170-mA to 290-mA), parameter 4.133 (from 230-mA to 20-mA), parameter 4.151 (from 335-mA to 290-mA), parameter 4.152 (from 150-mA to 230-mA), parameter 4.153 (from 185-mA to 50-mA) yes Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted).  Voltage level is with reference to the thermal/ground pad of the device.#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE POS MIN MAX UNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8 V.  VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature. ESD Ratings POS VALUE UNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS MIN NOM MAX UNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface after device start-up. Additional cooling strategies may be necessary to keep junction temperature at recommended limits. The input buffer of a fail-safe GPIO pin is isolated from its input signal.  Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application report. General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) Over operating free-air temperature range (unless otherwise noted).  Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Low Noise Low Drop-Out Regulator (LDO4) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature. Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current. SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN. The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output. Reference Generator (BandGap) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs Monitoring Functions
  Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software. Interrupt status signal is input signal for PGOOD deglitch logic. Clocks, Oscillators, and PLL Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance. External capacitors must be used if crystal load capacitance > 6 pF. Thermal Monitoring and Shutdown Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs System Control Thresholds Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms Current Consumption Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA Backup Battery Charger Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV.  When VCCA-VBACKUP is ≤ 200mV, the charger remains fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.  Digital Input Signal Parameters Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not available. Digital Output Signal Parameters
  Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs I/O Pullup and Pulldown Resistance Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ I²C Interface Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 Serial Peripheral Interface (SPI) These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted). POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns Typical Characteristics Quiescent Current vs Input Voltage TA = 25°C Standby Current with VCCA Monitor TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C Specifications A 20220110 Section 8.8 Specifications - BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators: Change typical value for parameter 4.112 (from 300-mA to 420-mA), parameter 4.113 (from 200-mA to 100-mA), parameter 4.122 (from 250-mA to 370-mA), parameter 4.123 (from 150-mA to 30-mA), parameter 4.131 (from 400-mA to 310-mA), parameter 4.132 (from 170-mA to 290-mA), parameter 4.133 (from 230-mA to 20-mA), parameter 4.151 (from 335-mA to 290-mA), parameter 4.152 (from 150-mA to 230-mA), parameter 4.153 (from 185-mA to 50-mA) yes A 20220110 Section 8.8 Specifications - BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators: Change typical value for parameter 4.112 (from 300-mA to 420-mA), parameter 4.113 (from 200-mA to 100-mA), parameter 4.122 (from 250-mA to 370-mA), parameter 4.123 (from 150-mA to 30-mA), parameter 4.131 (from 400-mA to 310-mA), parameter 4.132 (from 170-mA to 290-mA), parameter 4.133 (from 230-mA to 20-mA), parameter 4.151 (from 335-mA to 290-mA), parameter 4.152 (from 150-mA to 230-mA), parameter 4.153 (from 185-mA to 50-mA) yes A 20220110 Section 8.8 Specifications - BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators: Change typical value for parameter 4.112 (from 300-mA to 420-mA), parameter 4.113 (from 200-mA to 100-mA), parameter 4.122 (from 250-mA to 370-mA), parameter 4.123 (from 150-mA to 30-mA), parameter 4.131 (from 400-mA to 310-mA), parameter 4.132 (from 170-mA to 290-mA), parameter 4.133 (from 230-mA to 20-mA), parameter 4.151 (from 335-mA to 290-mA), parameter 4.152 (from 150-mA to 230-mA), parameter 4.153 (from 185-mA to 50-mA) yes A20220110Section 8.8 Specifications - BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators: Change typical value for parameter 4.112 (from 300-mA to 420-mA), parameter 4.113 (from 200-mA to 100-mA), parameter 4.122 (from 250-mA to 370-mA), parameter 4.123 (from 150-mA to 30-mA), parameter 4.131 (from 400-mA to 310-mA), parameter 4.132 (from 170-mA to 290-mA), parameter 4.133 (from 230-mA to 20-mA), parameter 4.151 (from 335-mA to 290-mA), parameter 4.152 (from 150-mA to 230-mA), parameter 4.153 (from 185-mA to 50-mA) yes yes Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted).  Voltage level is with reference to the thermal/ground pad of the device.#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE POS MIN MAX UNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8 V.  VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature. Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted).  Voltage level is with reference to the thermal/ground pad of the device.#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE POS MIN MAX UNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8 V.  VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature. Over operating free-air temperature range (unless otherwise noted).  Voltage level is with reference to the thermal/ground pad of the device.#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE POS MIN MAX UNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C Over operating free-air temperature range (unless otherwise noted).  Voltage level is with reference to the thermal/ground pad of the device.#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/ABSMAXNOTE POS MIN MAX UNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C POS MIN MAX UNIT POS MIN MAX UNIT POSMINMAXUNIT M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4d LDO1/2/3 regulators 350 mA M2.4e LDO4 regulators 210 mA M3 Junction temperature, TJ –45 160 °C M4 Storage temperature, Tstg –65 150 °C M1.3 Voltage on OV protected supply input pin  VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.3Voltage on OV protected supply input pin VCCA#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME–0.36V M1.4 Voltage on all buck supply voltage input pins PVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.4Voltage on all buck supply voltage input pinsPVIN_Bx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME–0.36V M1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.5 0.5 V M1.4aVoltage difference between supply input pinsBetween VCCA and each PVIN_Bx–0.50.5V M1.5a Voltage on all buck switch nodes SW_Bx pins –0.3 PVIN_Bx + 0.3 V, up to 6 V V M1.5aVoltage on all buck switch nodesSW_Bx pins–0.3PVIN_Bx + 0.3 V, up to 6 VV M1.5b SW_Bx pins, 10-ns transient –2 10 V M1.5bSW_Bx pins, 10-ns transient–210V M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V M1.6Voltage on all buck voltage sense nodesFB_Bx–0.34V M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME –0.3 6 V M1.7Voltage on all LDO supply voltage input pinsPVIN_LDOx#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161082/VCCAOVPTIME–0.36V M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 PVIN_LDOx + 0.3 V, up to 6 V V M1.8Voltage on all LDO output pinsVOUT_LDOx–0.3PVIN_LDOx + 0.3 V, up to 6 VV M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V M1.9Voltage on internal LDO output pinsVOUT_LDOVINT, VOUT_LDOVRTC–0.32V M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 VCCA + 0.3 V, up to 6 V V M1.10Voltage on I/O supply pinVIO_IN with respect to ground pad–0.3VCCA + 0.3 V, up to 6 VV M1.11 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO6 –0.3 6 V M1.11Voltage on logic pins (input or output) in VIO domainI2C and SPI pins, nRSTOUT, and nINT pins, and all GPIO output buffers except GPIO5 & GPIO62–0.36V M1.12 Voltage on logic pins (input or output) in LDOVINT domain GPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4 –0.3 6 V M1.12Voltage on logic pins (input or output) in LDOVINT domainGPIO5 & GPIO6, and all GPIO input buffers except GPIO3 & GPIO4–0.36V M1.13 Voltage on logic pins (input) in LDOVRTC domain GPIO3 & GPIO4 –0.3 6 V M1.13Voltage on logic pins (input) in LDOVRTC domainGPIO3 & GPIO4–0.36V M1.14 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE & EN_DRV –0.3 6 V M1.14Voltage on logic pins (input or output) in VCCA domainnPWRON/ENABLE & EN_DRV–0.36V M1.15 Voltage on analog mux output pin AMUXOUT –0.3 VCCA + 0.3 V, up to 6 V V M1.15Voltage on analog mux output pinAMUXOUT–0.3VCCA + 0.3 V, up to 6 VV M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V M1.16Voltage on back-up power supply inputVBACKUP–0.36V M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V M1.17Voltage on crystal oscillator pinsOSC32KIN, OSC32KOUT, & OSC32KCAP–0.32V M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V M1.18Voltage on REFGND pinsREFGND1 & REFGND2–0.30.3V M2.1a Voltage rise slew-rate on input supply pins VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs M2.1aVoltage rise slew-rate on input supply pinsVCCA, PVIN_Bx (voltage below 2.7 V)60mV/µs M2.1b VIO (only when VCCA < 2 V) 60 mV/µs M2.1bVIO (only when VCCA < 2 V)60mV/µs M2.3a Peak output current All pins other than power resources 20 mA M2.3aPeak output currentAll pins other than power resources20mA M2.3b Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase 5 A M2.3bBuck1/2/3/4 regulators: PVIN_Bx and SW_Bx per phase5A M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A M2.3c M2.3c Buck5 regulator: PVIN_B5 and SW_B5 Buck5 regulator: PVIN_B5 and SW_B5 3 3 A A M2.4a Average output current, 100 k hour, TJ = 125℃ GPIOx pins, source current 3 mA M2.4aAverage output current, 100 k hour, TJ = 125℃JGPIOx pins, source current3mA M2.4b GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current 8 mA M2.4bGPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT, and nRSTOUT pins, sink current8mA M2.4c GPIO3/4/7/8/9/10/11 pins, sink current 3 mA M2.4cGPIO3/4/7/8/9/10/11 pins, sink current3mA M2.4d LDO1/2/3 regulators 350 mA M2.4dLDO1/2/3 regulators350mA M2.4e LDO4 regulators 210 mA M2.4eLDO4 regulators210mA M3 Junction temperature, TJ –45 160 °C M3Junction temperature, TJ J–45160°C M4 Storage temperature, Tstg –65 150 °C M4Storage temperature, Tstg stg–65150°C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8 V.  VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.Absolute Maximum RatingsAbsolute Maximum RatingsRecommended Operating ConditionsRecommended Operating ConditionsAbsolute Maximum RatingsThe voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8 V.  VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature. ESD Ratings POS VALUE UNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. ESD Ratings POS VALUE UNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. POS VALUE UNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V POS VALUE UNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V POS VALUE UNIT POS VALUE UNIT POSVALUEUNIT M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V M5 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 ±2000 V M5V(ESD) (ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161083/HBM_AUTO5±2000V M6 V(ESD) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 ±500 V M6V(ESD) (ESD)Electrostatic dischargeCharged-device model (CDM), per AEC Q100-011±500V AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS MIN NOM MAX UNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface after device start-up. Additional cooling strategies may be necessary to keep junction temperature at recommended limits. The input buffer of a fail-safe GPIO pin is isolated from its input signal.  Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V. Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS MIN NOM MAX UNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface after device start-up. Additional cooling strategies may be necessary to keep junction temperature at recommended limits. The input buffer of a fail-safe GPIO pin is isolated from its input signal.  Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V. Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS MIN NOM MAX UNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS MIN NOM MAX UNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C POS MIN NOM MAX UNIT POS MIN NOM MAX UNIT POSMINNOMMAXUNIT R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.20 Junction temperature, TJ Operational –40 25 150 °C R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V R1.3Voltage on OV protected supply input pinVCCAVCCA_UV5.5V R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V R1.4Voltage on all buck supply input pinsPVIN_Bx2.85.5V R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V R1.4aVoltage difference between supply input pinsBetween VCCA and each PVIN_Bx–0.20.2V R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V R1.5Voltage on all buck switch nodesSW_Bx pins3.35.5V R1.6 Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 FB_Bx 0 VOUT_Bn,max V R1.6Voltage on all buck voltage sense nodes#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246FB_Bx0VOUT_Bn,max OUT_Bn,maxV R1.7a Voltage on all LDO supply voltage input pins PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V R1.7aVoltage on all LDO supply voltage input pinsPVIN_LDO12, PVIN_LDO31.23.3VCCAV R1.7b PVIN_LDO4 2.2 3.3 VCCA V R1.7bPVIN_LDO42.23.3VCCAV R1.8 Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 VOUT_LDOx 0 3.3 V R1.8Voltage on all LDO output pins#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSE8246VOUT_LDOx03.3V R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V R1.9Voltage on internal LDO output pinsVOUT_LDOVINT, VOUT_LDOVRTC1.651.95V R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V R1.10Voltage on reference ground pinsREFGNDx–0.30.3V R1.11 Voltage on I/O supply pin VVIO_IN = 1.8 V 1.7 1.8 1.9 V R1.11Voltage on I/O supply pinVVIO_IN = 1.8 VVIO_IN1.71.81.9V R1.12 VVIO_IN = 3.3 V 3.135 3.3 VCCA, up to 3.465V R1.12VVIO_IN = 3.3 VVIO_IN3.1353.3VCCA, up to 3.465V R1.13 Voltage on logic pins (input or output) in VIO domain I2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins 0 VVIO_IN VVIO_IN,max V R1.13Voltage on logic pins (input or output) in VIO domainI2C and SPI pins, nRSTOUT & nRSTOUT_SoC pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, GPIO10, and GPIO11 pins20VVIO_IN VIO_INVVIO_IN,max VIO_IN,maxV R1.14 Voltage on backup supply pin VBACKUP 0 Full Battery, up to 5.5V V R1.14Voltage on backup supply pinVBACKUP0Full Battery, up to 5.5VV R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 VOUT_LDOVRTC,max V R1.15Voltage on crystal oscillator pinsOSC32KIN, OSC32KOUT, OSC32KCAP0VOUT_LDOVRTC,max OUT_LDOVRTC,maxV R1.16 Voltage on logic pins (input or output) in LDOVRTC domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4 0 1.8 VOUT_LDOVRTC,max V R1.16Voltage on logic pins (input or output) in LDOVRTC domainWith fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO3 & GPIO4#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE01.8VOUT_LDOVRTC,max OUT_LDOVRTC,maxV R1.17 Voltage on logic pins (input or output) in LDOVINT domain With fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6 0 1.8 VOUT_LDOVINT,max V R1.17Voltage on logic pins (input or output) in LDOVINT domainWith fail-safe#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE: GPIO5 & GPIO6#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/ROC-FAILSAFE01.8VOUT_LDOVINT,max OUT_LDOVINT,maxV R1.18 Voltage on logic pins (input or output) in VCCA domain nPWRON/ENABLE, EN_DRV 0 VVCCA V R1.18Voltage on logic pins (input or output) in VCCA domainnPWRON/ENABLE, EN_DRV0VVCCA VCCAV R1.19 Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 –40 25 125 °C R1.19Operating free-air temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161084/SLVSCO49881–4025125°C R1.20 Junction temperature, TJ Operational –40 25 150 °C R1.20Junction temperature, TJ JOperational–4025150°C The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface after device start-up. Additional cooling strategies may be necessary to keep junction temperature at recommended limits. The input buffer of a fail-safe GPIO pin is isolated from its input signal.  Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V. The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface after device start-up.BUCK5Additional cooling strategies may be necessary to keep junction temperature at recommended limits.The input buffer of a fail-safe GPIO pin is isolated from its input signal.  Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT RWE (VQFNP) 56 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161085/APPNOTE_SPRA953 TPS6593-Q1 TPS6593-Q1UNIT RWE (VQFNP) RWE (VQFNP) 56 PINS 56 PINS RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 6.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W RθJA Junction-to-ambient thermal resistance 21.5 °C/W RθJA θJAJunction-to-ambient thermal resistance21.5°C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance9.5°C/W RθJB Junction-to-board thermal resistance 6.2 °C/W RθJB θJBJunction-to-board thermal resistance6.2°C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJT JTJunction-to-top characterization parameter0.1°C/W ψJB Junction-to-board characterization parameter 6.2 °C/W ψJB JBJunction-to-board characterization parameter6.2°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance0.7°C/W For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application report. Semiconductor and ICPackage Thermal Metrics application reportSemiconductor and ICPackage Thermal Metrics General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) Over operating free-air temperature range (unless otherwise noted).  Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) Over operating free-air temperature range (unless otherwise noted).  Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Over operating free-air temperature range (unless otherwise noted).  Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Over operating free-air temperature range (unless otherwise noted).  Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.18 Ripple From the internal charge pump 5 mVPP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Electrical Characteristics Electrical Characteristics 1.1a CIN(LDOn) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP Connected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 1.1aCIN(LDOn) IN(LDOn)Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-INCAPConnected from PVIN_LDOn to GND, Shared input tank capacitance (depending on platform requirements)12.2µF 1.1b COUT(LDOn) Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP Connected from VOUT_LDOn to GND 1 2.2 4 µF 1.1bCOUT(LDOn) OUT(LDOn)Output filtering effective capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-OUTCAPConnected from VOUT_LDOn to GND12.24µF 1.1c CESR (LDOn) Filtering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR 1 MHz ≤ f ≤ 10 MHz 20 mΩ 1.1cCESR (LDOn)ESRFiltering capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-ESR1 MHz ≤ f ≤ 10 MHz20mΩ 1.1d COUT_TOTAL (LDOn) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP 1 MHz ≤ f ≤ 10 MHz 20 µF 1.1dCOUT_TOTAL (LDOn)OUT_TOTALTotal capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVE82-GPLDO-TOTAL-CAP1 MHz ≤ f ≤ 10 MHz20µF 1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V 1.2aVIN(LDOn) IN(LDOn)LDO Input voltageLDO mode1.2VCCAV 1.2b VIN(LDOn)_bypass LDO Input voltage in bypass mode Bypass mode 1.7 VCCA, up to 3.6 V V 1.2bVIN(LDOn)_bypass IN(LDOn)_bypassLDO Input voltage in bypass modeBypass mode1.7VCCA, up to 3.6 VV 1.3 VOUT(LDOn) LDO output voltage configurable range LDO mode, with 50-mV steps 0.6 3.3 V 1.3VOUT(LDOn) OUT(LDOn)LDO output voltage configurable rangeLDO mode, with 50-mV steps0.63.3V 1.4a TDCOV(LDOn) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variations LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1V –1% 1% 1.4aTDCOV(LDOn) DCOV(LDOn)Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature variationsLDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) ≥ 1VIN(LDOn)OUT(LDOn)OUT(LDOn) –1%1% 1.4b LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1V –10 10 mV 1.4bLDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn) < 1VIN(LDOn)OUT(LDOn)OUT(LDOn) –1010mV 1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA 1.6IOUT(LDOn) OUT(LDOn)Output currentVIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max IN(LDOn)minIN(LDOn)IN(LDOn)max 500 500mA 1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA 1.7ISHORT(LDOn) SHORT(LDOn)LDO current limitationLDO mode and bypass mode7001800mA 1.8a IIN_RUSH(LDOn) LDO inrush current LDOn_BYPASS = 0 1500 mA 1.8aIIN_RUSH(LDOn) IN_RUSH(LDOn)LDO inrush currentLDOn_BYPASS = 01500mA LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn 1500 LDOx_BYPASS = 1, with maximum 50-µF load connected to VOUT_LDOn1500 1.11a RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00' 35 50 65 kΩ 1.11aRDIS(LDOn) DIS(LDOn)Pulldown discharge resistance at LDO outputActive only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '00'355065kΩ 1.11b RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01' 60 125 200 Ω 1.11bRDIS(LDOn) DIS(LDOn)Pulldown discharge resistance at LDO outputActive only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '01'60125200Ω 1.11c RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10' 120 250 400 Ω 1.11cRDIS(LDOn) DIS(LDOn)Pulldown discharge resistance at LDO outputActive only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '10'120250400Ω 1.11d RDIS(LDOn) Pulldown discharge resistance at LDO output Active only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11' 240 500 800 Ω 1.11dRDIS(LDOn) DIS(LDOn)Pulldown discharge resistance at LDO outputActive only when converter is disabled. Also applies to bypass mode. LDOn_PLDN = '11'240500800Ω 1.12a PSRRVIN(LDOn) Power supply ripple rejection from VIN(LDOn) f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 60 dB 1.12aPSRRVIN(LDOn) VIN(LDOn)Power supply ripple rejection from VIN(LDOn) IN(LDOn)f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mAIN(LDOx)OUTOUT60dB 1.12b f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 50 1.12bf = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mAIN(LDOx)OUTOUT50 1.12c f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 35 1.12cf = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mAIN(LDOx)OUTOUT35 1.12d f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mA 24 1.12df = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500 mAIN(LDOx)OUTOUT24 1.13 IQoff(LDOn) Quiescent current, off mode For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°C 2 µA 1.13IQoff(LDOn) Qoff(LDOn)Quiescent current, off modeFor LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V, TJ = 25°CIN(LDOn)J2µA 1.14a IQon(LDOn) Quiescent current, on mode LDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°C 78 µA 1.14aIQon(LDOn) Qon(LDOn)Quiescent current, on modeLDOn_BYPASS = 0, ILOAD = 0 mA ,  TJ = 25°CLOADJ78µA 1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68 1.14bLDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°CLOADJ68 1.15 TLDR(LDOn) Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µs 25 mV 1.15TLDR(LDOn) LDR(LDOn)Transient load regulation, ΔVOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOV OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161086/SLVSE82-GPLDO-UVOVLDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr = tf = 1 µsOUTOUTmaxrf25mV 1.16 TBYPASS_to_LDO(LDOn) Transient regulation due to Bypass Mode to Linear Mode Transition VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0 -2 mV 1.16TBYPASS_to_LDO(LDOn) BYPASS_to_LDO(LDOn)Transient regulation due to Bypass Mode to Linear Mode TransitionVIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit switches between 1 and 0IN(LDOn)OUTOUT(LDOn)max-2mV 1.17 VNOISE(LDOn) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 250 µVRMS 1.17VNOISE(LDOn) NOISE(LDOn)RMS Noise100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mAINOUTOUT250µVRMS RMS 1.18 Ripple From the internal charge pump 5 mVPP 1.18RippleFrom the internal charge pump5mVPP PP 1.19a RBYPASS(LDOn) Bypass resistance 3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1 200 mΩ 1.19aRBYPASS(LDOn) BYPASS(LDOn)Bypass resistance3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx  ≤ VCCA, IOUT = 500 mA, LDOx_BYPASS = 1IN(LDOn)OUT200mΩ 1.19c 1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1 250 1.19c1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA, LDOn_BYPASS = 1IN(LDOn)OUT250 1.20 VTH_RV_SC(LDOn) Threshold voltage for Short Circuit LDOn_EN = 0 140 150 160 mV 1.20VTH_RV_SC(LDOn) TH_RV_SC(LDOn)Threshold voltage for Short Circuit LDOn_EN = 0 140150160mV Timing Requirements Timing Requirements 19.1 ton(LDOn) Turn-on time Time between enable of the LDOn to within OV/UV monitor level 500 µs 19.1ton(LDOn) on(LDOn)Turn-on timeTime between enable of the LDOn to within OV/UV monitor level500µs 19.2a tramp(LDOn) Ramp-up slew rate VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 0 25 mV/µs 19.2atramp(LDOn) ramp(LDOn)Ramp-up slew rateVOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 025mV/µs 19.2b VOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 1 3 mV/µs 19.2bVOUT from 0.3 V to 90% of LDOn_VSET. LDOn_SLOW_RAMP = 13mV/µs 19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.3atdelay_OC(LDOn) delay_OC(LDOn)Over-current detection delayDetection signal delay when IOUT > ILIMOUT 35µs 19.3b tdeglitch_OC(LDOn) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.3btdeglitch_OC(LDOn) deglitch_OC(LDOn)Over-current detection signal deglitch timeDigital deglitch time for the over-current detection signal3844µs 19.4 tlatency_OC(LDOn) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs 19.4tlatency_OC(LDOn) latency_OC(LDOn)Over-current signal total latency timeTotal delay from Iout > ILIM to interrupt or PFSM triggerout79µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Input capacitors must be placed as close as possible to the device pins.When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.Ceramic capacitors recommendedLoad transient voltage must be considered when selecting UV/OV threshold levels for the LDO outputAdditional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Low Noise Low Drop-Out Regulator (LDO4) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Low Noise Low Drop-Out Regulator (LDO4) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs Electrical Characteristics Electrical Characteristics 2.1a CIN(LDO4) Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP Connected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements) 1 2.2 µF 2.1aCIN(LDO4) IN(LDO4)Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-INCAPConnected from PVIN_LDO4 to GND, Shared input tank capacitance (depending on platform requirements)12.2µF 2.1b COUT(LDO4) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP Connected from VOUT_LDO4 to GND 1 2.2 4 µF 2.1bCOUT(LDO4) OUT(LDO4)Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-OUTCAPConnected from VOUT_LDO4 to GND12.24µF 2.1c CESR(LDO4) Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 1 MHz ≤ f ≤ 10 MHz 20 mΩ 2.1cCESR(LDO4) ESR(LDO4)Input and output capacitor ESR#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE824390 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE8243901 MHz ≤ f ≤ 10 MHz20mΩ 2.1d COUT_TOTAL (LDO4) Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF 2.1dCOUT_TOTAL (LDO4) OUT_TOTAL(LDO4)Total capacitance at output (Local + POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161087/SLVSE82-LNLDO-TOTALCAP1 MHz ≤ f ≤ 10 MHz, fast ramp15µF 2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF 2.1e1 MHz ≤ f ≤ 10 MHz, slow ramp30µF 2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V 2.2VIN(LDO4) IN(LDO4)LDO Input voltage2.25.5V 2.3 VOUT(LDO4) LDO output voltage configurable range with 25-mV steps 1.2 3.3 V 2.3VOUT(LDO4) OUT(LDO4)LDO output voltage configurable rangewith 25-mV steps1.23.3V 2.5 TDCOV(LDO4) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1% 2.5TDCOV(LDO4) DCOV(LDO4)Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperatureVIN(LDO4) - VOUT(LDO4) > 300 mVIN(LDO4)OUT(LDO4)–1%1% 2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA 2.7IOUT(LDO4) OUT(LDO4)Output currentVIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max IN(LDO4)minIN(LDO4)IN(LDO4)max300mA 2.8 ISHORT(LDO4) LDO current limit 400 900 mA 2.8ISHORT(LDO4) SHORT(LDO4)LDO current limit400900mA 2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA 2.9IIN_RUSH(LDO4) IN_RUSH(LDO4)LDO inrush currentVIN = 3.3V when LDO is enabledIN650mA 2.13a PSRR(LDO4) Power supply ripple rejection f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 dB 2.13aPSRR(LDO4) (LDO4)Power supply ripple rejectionf = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mAIN(LDO4)OUTOUT70dB 2.13b f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 70 2.13bf = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mAIN(LDO4)OUTOUT70 2.13c f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 62 2.13cf = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mAIN(LDO4)OUTOUT62 2.13d f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mA 15 2.13df = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300 mAIN(LDO4)OUTOUT15 2.12a RDIS(LDO4) Pulldown discharge resistance at LDO output Active only when converter is disabled, LDO4_PLDN = '00' 35 50 65 kΩ 2.12aRDIS(LDO4) DIS(LDO4)Pulldown discharge resistance at LDO outputActive only when converter is disabled, LDO4_PLDN = '00'355065kΩ 2.12b Active only when converter is disabled, LDO4_PLDN = '01' 60 125 200 Ω 2.12bActive only when converter is disabled, LDO4_PLDN = '01'60125200Ω 2.12c Active only when converter is disabled, LDO4_PLDN = '10' 120 250 400 Ω 2.12cActive only when converter is disabled, LDO4_PLDN = '10'120250400Ω 2.12d Active only when converter is disabled, LDO4_PLDN= '11' 240 500 800 Ω 2.12dActive only when converter is disabled, LDO4_PLDN= '11'240500800Ω 2.14 IQoff(LDO4) Leakage current in off mode For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃ 2 µA 2.14IQoff(LDO4) Qoff(LDO4)Leakage current in off modeFor all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ = 25℃IN(LDO4)J 2µA 2.15 IQon(LDO4) Quiescent current ILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃ 40 µA 2.15IQon(LDO4) Qon(LDO4)Quiescent currentILOAD = 0 mA ,LDO4 under valid operating condition, TJ = 25℃LOAD, J 40µA 2.16 TLDR(LDO4) Transient load regulation, ΔVOUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF –25 25 mV 2.16TLDR(LDO4) LDR(LDO4)Transient load regulation, ΔVOUT OUT VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF IN(LDO4)OUT(LDO4)OUTOUT_MAX OUT_MAX OUT(LDO4)–2525mV 2.17 TLNR(LDO4) Transient line regulation, ΔVOUT / VOUT On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µs -25 25 mV 2.17TLNR(LDO4) LNR(LDO4)Transient line regulation, ΔVOUT / VOUT OUTOUTOn mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10 µsINPPrf-2525mV 2.18 VNOISE(LDO4) RMS Noise 100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA 15 µVRMS 2.18VNOISE(LDO4) NOISE(LDO4)RMS Noise100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mAINOUTOUT15µVRMS RMS 2.19 VTH_SC_RV(LDO4) Threshold voltage for Short Circuit LDO4_EN = 0 140 150 160 mV 2.19VTH_SC_RV(LDO4) TH_SC_RV(LDO4)Threshold voltage for Short Circuit LDO4_EN = 0 140150160mV Timing Requirements Timing Requirements 19.11a tSTART(LDO4) Start Time Time from completion of enable command to output voltage at 0.5 V 150 µs 19.11atSTART(LDO4) START(LDO4)Start TimeTime from completion of enable command to output voltage at 0.5 V150µs 19.12a1 tRAMP(LDO4) Ramp Time Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0 350 µs 19.12a1tRAMP(LDO4) RAMP(LDO4)Ramp TimeMeasured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 0350µs 19.12a2 Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 1 2.3 ms 19.12a2Measured from 0.5 V to 90% of LDO4_VSET.  LDO4_SLOW_RAMP = 12.3ms 19.12b tRAMP_SLEW(LDO4) Ramp up slew rate VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 0 27 mV/µs 19.12btRAMP_SLEW(LDO4) RAMP_SLEW(LDO4)Ramp up slew rateVOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 027mV/µs 19.12c VOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 1 3 mV/µs 19.12cVOUT from 0.5 V to 90% of LDO4_VSET. LDO4_SLOW_RAMP = 13mV/µs 19.13a tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs 19.13atdelay_OC(LDO4) delay_OC(LDO4)Over-current detection delayDetection signal delay when IOUT > ILIMOUT 35µs 19.13b tdeglitch_OC(LDO4) Over-current detection signal deglitch time Digital deglitch time for the over-current detection signal 38 44 µs 19.13btdeglitch_OC(LDO4) deglitch_OC(LDO4)Over-current detection signal deglitch timeDigital deglitch time for the over-current detection signal3844µs 19.14 tlatency_OC(LDO4) Over-current signal total latency time Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs 19.14tlatency_OC(LDO4) latency_OC(LDO4)Over-current signal total latency timeTotal delay from Iout > ILIM to interrupt or PFSM triggerout79µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators. Ceramic capacitors recommended Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Input capacitors must be placed as close as possible to the device pins.When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.Ceramic capacitors recommendedAdditional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V Electrical Characteristics Electrical Characteristics 3.1 COUT(LDOinternal) Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP Connected from VOUT_LDOx to GND 1 2.2 4 µF 3.1COUT(LDOinternal) OUT(LDOinternal)Output filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161088/SLVSE82-INTDLO-OUTCAPConnected from VOUT_LDOx to GND12.24µF 3.3a VOUT(LDOVRTC) LDO output voltage LDOVRTC 1.8 V 3.3aVOUT(LDOVRTC) OUT(LDOVRTC)LDO output voltageLDOVRTC1.8V 3.3b VOUT(LDOVINT) LDOVINT 1.8 V 3.3bVOUT(LDOVINT) OUT(LDOVINT)LDOVINT1.8V 3.7a IQoff(LDOinternal) Leakage current, off mode LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2 µA 3.7aIQoff(LDOinternal) Qoff(LDOinternal)Leakage current, off modeLDOVRTC, VCCA = 3.3 V, TJ = 25℃J2µA 3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2 3.7bLDOVINT, VCCA = 3.3 V, TJ = 25℃J2 3.8a IQon(LDOinternal) Quiescent current, on mode LDOVRTC under valid operating condition, ILOAD = 0 mA  3 10 µA 3.8aIQon(LDOinternal) Qon(LDOinternal)Quiescent current, on modeLDOVRTC under valid operating condition, ILOAD = 0 mA LOAD310µA 3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10 3.8bLDOVINT under valid operating condition, ILOAD = 0 mALOAD310 3.9 RDIS(LDOinterna;) Pulldown discharge resistance at LDO output LDOx disabled 60 125 190 Ω 3.9RDIS(LDOinterna;) DIS(LDOinterna;)Pulldown discharge resistance at LDO outputLDOx disabled60125190Ω 3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold LDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µs 1.62 1.64 1.665 V 3.10aiVUVLO(LDOVINT) UVLO(LDOVINT)LDOVINT UVLO thresholdLDOVINT output step from 1.8 V → 1.6 V, tf = 100 mV/µsf1.621.641.665V 3.10bi VUVLO(LDOVRTC) LDOVRTC UVLO threshold LDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs  1.62 1.64 1.665 V 3.10biVUVLO(LDOVRTC) UVLO(LDOVRTC)LDOVRTC UVLO thresholdLDOVRTC output step from 1.8 V → 1.6 V, tf = 100 mV/µs f1.621.641.665V 3.11ai VOVP(LDOVINT) LDOVINT OVP threshold LDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs  1.93 1.96 1.98 V 3.11aiVOVP(LDOVINT) OVP(LDOVINT)LDOVINT OVP thresholdLDOVINT output step from 1.8 V → 2.0 V, tr = 100 mV/µs r1.931.961.98V When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature. Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current. SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN. The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output. BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 RegulatorsBUCK4 BUCK5 Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature. Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current. SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN. The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output. Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs Over operating free-air temperature range (unless otherwise noted).  Voltage level are referenced to the thermal/ground pad of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative FB_Bn pin of the differential pair.OUT_Bn POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1b Multi-phase output 0.3 1.9 V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7b 1-phase, BUCK4 4 A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7d 2-phase 7 A 4.7e 3-phase 10.5 A 4.7f 4-phase 14 A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15b From 2-phase to 3-phase 4.0 A 4.15c From 3-phase to 4-phase 6.0 A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16b From 3-phase to 2-phase 2.7 A 4.16c From 4-phase to 3-phase 3.5 A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34b DCR 10 mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39b PFM mode 15 25 mVPP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.42 IOUT_Bn_SINK Current sink –1 A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45b DCR 10 mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54b DCR 10 mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59b PFM mode 15 50 mVPP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65b DCR 10 mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70b PFM mode 15 25 mVPP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74b DCR 10 mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79b PFM mode 15 25 mVPP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84b DCR 10 mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89b PFM mode 15 25 mVPP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94b DCR 10 mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99b PFM mode 15 25 mVPP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs Electrical Characteristics - Output Voltage Electrical Characteristics - Output Voltage 4.1a VVOUT_Bn Output voltage configurable range 1-phase output 0.3 3.34 V 4.1aVVOUT_Bn VOUT_BnOutput voltage configurable range1-phase output0.33.34V 4.1b Multi-phase output 0.3 1.9 V 4.1bMulti-phase output0.31.9V 4.2a VVOUT_Bn_Step Output voltage configurable step size 0.3 V ≤ VVOUT_Bn < 0.6 V 20 mV 4.2aVVOUT_Bn_Step VOUT_Bn_StepOutput voltage configurable step size0.3 V ≤ VVOUT_Bn < 0.6 VVOUT_Bn20mV 4.2b 0.6 V ≤ VVOUT_Bn < 1.1 V 5 mV 4.2b0.6 V ≤ VVOUT_Bn < 1.1 VVOUT_Bn 5mV 4.2c 1.1 V ≤ VVOUT_Bn < 1.66 V 10 mV 4.2c1.1 V ≤ VVOUT_Bn < 1.66 VVOUT_Bn10mV 4.2d 1.66 V ≤ VVOUT_Bn < 3.34 V 20 mV 4.2d1.66 V ≤ VVOUT_Bn < 3.34 VVOUT_Bn20mV 4.4 VDROPOUT_Bn Input and output voltage difference Minimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics 0.7 V 4.4VDROPOUT_Bn DROPOUT_BnInput and output voltage differenceMinimum voltage between PVIN_Bn and VOUT_Bn to fulfill the electrical characteristics0.7V 4.5a VOUT_SR_Bn Output voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs 4.5aVOUT_SR_Bn OUT_SR_BnOutput voltage slew-rate configurable range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER4#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER7BUCKn_SLEW_RATE[2:0] = 000b26.633.336.6mV/µs 4.5b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22 mV/µs 4.5bBUCKn_SLEW_RATE[2:0] = 001b172022mV/µs 4.5c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11 mV/µs 4.5cBUCKn_SLEW_RATE[2:0] = 010b91011mV/µs 4.5d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5 mV/µs 4.5dBUCKn_SLEW_RATE[2:0] = 011b4.555.5mV/µs 4.5e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75 mV/µs 4.5eBUCKn_SLEW_RATE[2:0] = 100b2.252.52.75mV/µs 4.5f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38 mV/µs 4.5fBUCKn_SLEW_RATE[2:0] = 101b1.121.251.38mV/µs 4.5g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69 mV/µs 4.5gBUCKn_SLEW_RATE[2:0] = 110b0.560.6250.69mV/µs 4.5h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344 mV/µs 4.5hBUCKn_SLEW_RATE[2:0] = 111b0.2810.31250.344mV/µs Electrical Characteristics - Output Current, Limits and Thresholds Electrical Characteristics - Output Current, Limits and Thresholds 4.7a IOUT_Bn Output current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 1-phase, BUCK5 2 A 4.7aIOUT_Bn OUT_BnOutput current#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER2#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER31-phase, BUCK52A 4.7b 1-phase, BUCK4 4 A 4.7b1-phase, BUCK44A 4.7c 1-phase, BUCK1, BUCK2, BUCK3 3.5 A 4.7c1-phase, BUCK1, BUCK2, BUCK33.5A 4.7d 2-phase 7 A 4.7d2-phase7A 4.7e 3-phase 10.5 A 4.7e 4.7e3-phase10.5A 4.7f 4-phase 14 A 4.7f 4.7f4-phase14A 4.8a IOUT_MP_Bal Current balancing for multi-phase output Mismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phase 20% 4.8aIOUT_MP_Bal OUT_MP_BalCurrent balancing for multi-phase outputMismatch between phase current and average phase current, 1A/phase < IOUT_Bn ≤ 2A / phaseOUT_Bn20% 4.8b Mismatch between phase current and average phase current, IOUT_Bn > 2 A / phase 10% 4.8bMismatch between phase current and average phase current, IOUT_Bn > 2 A / phaseOUT_Bn10% 4.9a ILIM_FWD_PEAK_ Range Forward current limit (peak during each switching cycle) configurable range BUCK5 2.5 3.5 A 4.9aILIM_FWD_PEAK_ Range LIM_FWD_PEAK_ RangeForward current limit (peak during each switching cycle) configurable range BUCK5 BUCK52.53.5A 4.9b BUCK1, BUCK2, BUCK3, BUCK4 2.5 5.5 A 4.9bBUCK1, BUCK2, BUCK3, BUCK4 , BUCK3, BUCK42.55.5A 4.10 ILIM_FWD_PEAK_Step Forward current limit step Size 1 A 4.10ILIM_FWD_PEAK_Step LIM_FWD_PEAK_StepForward current limit step Size1A 4.11a ILIM_FWD_PEAK_Accuracy Forward current limit accuracy ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V -0.55 0.55 A 4.11aILIM_FWD_PEAK_Accuracy LIM_FWD_PEAK_AccuracyForward current limit accuracyILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 VLIM_FWDPVIN_Bn-0.550.55A 4.11b ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 -0.55 0.55 A 4.11bILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 LIM_FWDPVIN_Bn, BUCK3, BUCK4-0.550.55A 4.11c ILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –15% 10% 4.11cILIM_FWD =  5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V, BUCK1, BUCK2, BUCK3, BUCK4 LIM_FWDPVIN_Bn, BUCK3, BUCK4–15%10% 4.11d ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 –10% 10% 4.11dILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V, BUCK1, BUCK2, BUCK3, BUCK4 LIM_FWDPVIN_Bn, BUCK3, BUCK4–10%10% 4.12 ILIM_NEG Negative current limit (peak during each switching cycle) 1.5 2 2.8 A 4.12ILIM_NEG LIM_NEGNegative current limit (peak during each switching cycle)1.522.8A 4.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A 4.15aIADD ADDPhase adding level (multi-phase rails)From 1-phase to 2-phase2.0A 4.15b From 2-phase to 3-phase 4.0 A 4.15bFrom 2-phase to 3-phase4.0A 4.15c From 3-phase to 4-phase 6.0 A 4.15cFrom 3-phase to 4-phase6.0A 4.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.3 A 4.16aISHED SHEDPhase shedding level (multi-phase rails)From 2-phase to 1-phase1.3A 4.16b From 3-phase to 2-phase 2.7 A 4.16bFrom 3-phase to 2-phase2.7A 4.16c From 4-phase to 3-phase 3.5 A 4.16cFrom 4-phase to 3-phase3.5A 4.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.7 A 4.16dISHED_Hyst SHED_HystPhase shedding hysteresis (multi-phase rails)Hysteresis from 2-phase to 1-phase0.7A 4.16e Hysteresis from 3-phase to 2-phase 1.3 A 4.16eHysteresis from 3-phase to 2-phase1.3A 4.16f Hysteresis from 4-phase to 3-phase 2.5 A 4.16fHysteresis from 4-phase to 3-phase2.5A Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance 4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V.  TJ = 25°C 1 µA 4.17Ioff offShutdown current, BUCKn disabledVCCA = VPVIN_Bn = 3.3 V.  TJ = 25°CPVIN_BnJ1µA 4.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°C 80 µA 4.18aIQ_AUTO Q_AUTOAuto mode quiescent currentIOUT_Bn = 0 mA, not switching, first single phase or primary phase in multi-phase configuration, TJ = 25°COUT_BnJ80µA 4.18b IOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°C 60 µA 4.18bIOUT_Bn = 0 mA, not switching, additional single phase or primary phase in multi-phase configuration, TJ = 25°COUT_BnJ60µA 4.18c IOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°C 30 µA 4.18cIOUT_Bn = 0 mA, not switching, secondary/tertiary/quaternary phase in multi-phase configuration, TJ = 25°COUT_BnJ30µA 4.19a RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK5 55 110 mΩ 4.19aRDS(ON) HS FET DS(ON) HS FETOn-resistance, high-side FETIOUT_Bn = 1 A, BUCK5OUT_Bn55110mΩ 4.19b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 52 100 mΩ 4.19bIOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4OUT_Bn52100mΩ 4.20a RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK5 41 70 mΩ 4.20aRDS(ON) LS FET DS(ON) LS FETOn-resistance, low-side FETIOUT_Bn = 1 A, BUCK5OUT_Bn 4170mΩ 4.20b IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4 30 55 mΩ 4.20bIOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3, BUCK4OUT_Bn3055mΩ 4.21 RDIS_Bn Output pulldown discharge resistance Regulator disabled, per phase, BUCKn_PLDN = 1 50 100 150 Ω 4.21RDIS_Bn DIS_BnOutput pulldown discharge resistanceRegulator disabled, per phase, BUCKn_PLDN = 150100150Ω 4.22 RSW_SC Short circuit detection resistance threshold at the SW pin 2 4.5 20 Ω 4.22RSW_SC SW_SCShort circuit detection resistance threshold at the SW pin24.520Ω Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single PhaseOUTOUT 4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.31VPVIN_Bn PVIN_BnInput voltage range3.03.35.5V 4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.32VVOUT_Bn VOUT_BnOutput voltage configurable range0.31.9V 4.33a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.33aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.33b COUT-Local(Buckn) Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.33bCOUT-Local(Buckn) OUT-Local(Buckn)Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1Per phase1022µF 4.33c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 70 250 µF 4.33cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1Per phase70250µF 4.34a LBn Power inductor Inductance 154 220 286 nH 4.34aLBn BnPower inductorInductance154220286nH 4.34b DCR 10 mΩ 4.34bDCR10mΩ 4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA 4.35IQ_PWM Q_PWMPWM mode Quiescent currentPer phase, IOUT_Bn = 0 mAOUT_Bn19mA 4.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.160aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.160bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.160cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2025mV 4.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.160dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 15 mV 4.37a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 10 mV 4.37aTLDSR_MP LDSR_MPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf10mV 4.37ba 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 15 mV 4.37ba0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1.75A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 VOUT_BnOUT_Bnrf, BUCK3, BUCK415mV 4.37bb 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 15 mV 4.37bb0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 VOUT_BnOUT_BnrfBUCK515mV 4.37ca 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 1.2% 4.37ca1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1.75 A / phase, tr = tf = 1 µs, PWM mode, BUCK1, BUCK2, BUCK3, BUCK4 VOUT_BnOUT_Bnrf, BUCK3, BUCK41.2% 4.37cb 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 1.0% 4.37cb1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode, BUCK5 VOUT_BnOUT_BnrfBUCK51.0% 4.38 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) -20 ±5 20 mV 4.38TLNSR LNSRTransient line responseVPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT(max) PVIN_BnrfOUT_BnOUT(max)-20±520mV 4.39a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 mVPP 4.39aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode, 1-phase3mVPP PP 4.39b PFM mode 15 25 mVPP 4.39bPFM mode1525mVPP PP 4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV 4.40VTH_SC_RV(Bn) TH_SC_RV(Bn)Threshold voltage for Short Circuit Bn_EN = 0 140150160mV 4.102 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA 4.102IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn400mA 4.101 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.101IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn500mA 4.103 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA 4.103IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn100mA Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only 4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.41VPVIN_Bn PVIN_BnInput voltage range2.83.35.5V 4.42 IOUT_Bn_SINK Current sink –1 A 4.42IOUT_Bn_SINK OUT_Bn_SINKCurrent sink–1A 4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V 4.43VVOUT_Bn VOUT_BnOutput voltage programmable range0.50.7V 4.44a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.44aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.44b COUT-TOTAL_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.44bCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11022µF 4.44c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 35 65 µF 4.44cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER13565µF 4.45a LBn Power inductor Inductance 329 470 611 nH 4.45aLBn BnPower inductorInductance329470611nH 4.45b DCR 10 mΩ 4.45bDCR10mΩ 4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.46aIQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mAOUT_Bn19mA 4.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.161aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.161bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.48 TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV 4.48TLDSR_MP LDSR_MPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to -1000 mA, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf15mV 4.49 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.49TLNSR LNSRTransient line responseVPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.50 VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 6 mVPP 4.50VOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode36mVPP PP Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase OnlyOUTOUT 4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.51VPVIN_Bn PVIN_BnInput voltage range3.03.35.5V 4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.52VVOUT_Bn VOUT_BnOutput voltage configurable range0.31.9V 4.53a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.53aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.53b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.53bCOUT-Local_Bn OUT-Local_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11022µF 4.53c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 25 100 µF 4.53cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER125100µF 4.54a LBn Power inductor Inductance 154 220 286 nH 4.54aLBn BnPower inductorInductance154220286nH 4.54b DCR 10 mΩ 4.54bDCR10mΩ 4.55a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 19 mA 4.55aIQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4OUT_Bn19mA 4.55b IOUT_Bn = 0 mA, BUCK5 19 mA 4.55bIOUT_Bn = 0 mA, BUCK5OUT_Bn 19mA 4.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.162aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.162bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV 4.162cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2035mV 4.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV 4.162dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 25 mV 4.57a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57aTLDSR_MP LDSR_MPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 200 mA / phase, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf15mV 4.57b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.57b0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf15mV 4.57c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.57c1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf1.5% 4.58 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.58TLNSR LNSRTransient line responseVPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.59a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 5 8 mVPP 4.59aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode58mVPP PP 4.59b PFM mode 15 50 mVPP 4.59bPFM mode1550mVPP PP 4.111 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA 4.111IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn500mA 4.112 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 420 mA 4.112IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn420mA 4.113 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA 4.113IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 VPVIN_BnVOUT_Bn100mA Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only Electrical Characteristics - 4.4 MHz VOUT Greater than 1.7 V, Single Phase OnlyOUT 4.61 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.61VPVIN_Bn PVIN_BnInput voltage range4.555.5V 4.62 IOUT_Bn_4.4_HVOUT Output current 2.5 A 4.62IOUT_Bn_4.4_HVOUT OUT_Bn_4.4_HVOUTOutput current2.5A 4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V 4.63VVOUT_Bn VOUT_BnOutput voltage configurable range1.73.34V 4.64a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.64aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.64b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.64bCOUT-Local_Bn OUT-Local_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11022µF 4.64c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 50 150 µF 4.64cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER150150µF 4.65a LBn Power inductor Inductance 329 470 611 nH 4.65aLBn BnPower inductorInductance329470611nH 4.65b DCR 10 mΩ 4.65bDCR10mΩ 4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA 4.66aIQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mAOUT_Bn19mA 4.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.163aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.163bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.163cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2025mV 4.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.163dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 15 mV 4.68 TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM mode 1.5% 4.68TLDSR_SP LDSR_SPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER61.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1 A/phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bn rf1.5% 4.69 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.69TLNSR LNSRTransient line responseVPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.70a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7 mVPP 4.70aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode37mVPP PP 4.70b PFM mode 15 25 mVPP 4.70bPFM mode1525mVPP PP 4.121 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA 4.121IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 VPVIN_BnVOUT_Bn400mA 4.122 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA 4.122IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 VPVIN_BnVOUT_Bn370mA 4.123 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA 4.123IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 VPVIN_BnVOUT_Bn30mA Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase OnlyOUTIN 4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V 4.71VPVIN_Bn PVIN_BnInput voltage range4.555.5V 4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.72VVOUT_Bn VOUT_BnOutput voltage configurable range0.33.34V 4.73a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.73aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.73b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.73bCOUT-Local_Bn OUT-Local_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11022µF 4.73c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 1000 µF 4.73cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11001000µF 4.74a LBn Power inductor Inductance 700 1000 1300 nH 4.74aLBn BnPower inductorInductance70010001300nH 4.74b DCR 10 mΩ 4.74bDCR10mΩ 4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.75IQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mAOUT_Bn13mA 4.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.164aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.164bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.164cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2025mV 4.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.164dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 15 mV 4.77a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77aTLDSR_MP LDSR_MPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf15mV 4.77b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.77b0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf15mV 4.77c 1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.5% 4.77c1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf1.5% 4.78 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.78TLNSR LNSRTransient line responseVPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.79a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.79aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode37.5mVPP PP 4.79b PFM mode 15 25 mVPP 4.79bPFM mode1525mVPP PP 4.131 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA 4.131IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn310mA 4.132 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA 4.132IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn290mA 4.133 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA 4.133IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn20mA Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single PhaseOUT 4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V 4.81VPVIN_Bn PVIN_BnInput voltage range3.03.35.5V 4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V 4.82VVOUT_Bn VOUT_BnOutput voltage configurable range0.31.9V 4.83a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.83aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.83b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 10 22 µF 4.83bCOUT-Local_Bn OUT-Local_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1Per phase1022µF 4.83c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 Per phase 100 1000 µF 4.83cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1Per phase1001000µF 4.84a LBn Power inductor Inductance 329 470 611 nH 4.84aLBn BnPower inductorInductance329470611nH 4.84b DCR 10 mΩ 4.84bDCR10mΩ 4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA 4.85IQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mAOUT_Bn13mA 4.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.165aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.165bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.165cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2025mV 4.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.165dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 15 mV 4.87a TLDSR_MP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV 4.87aTLDSR_MP LDSR_MPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf5mV 4.87b 0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV 4.87b0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf15mV 4.87c 1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 1.0% 4.87c1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf1.0% 4.88 TLNSR Transient line response VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) -20 ±5 20 mV 4.88TLNSR LNSRTransient line responseVPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bn= IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.89a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode, 1-phase 3 5 mVPP 4.89aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode, 1-phase35mVPP PP 4.89b PFM mode 15 25 mVPP 4.89bPFM mode1525mVPP PP 4.141 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA 4.141IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn500mA 4.142 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA 4.142IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn400mA 4.143 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA 4.143IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn100mA Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase OnlyOUT IN 4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V 4.91VPVIN_Bn PVIN_BnInput voltage range2.83.35.5V 4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V 4.92VVOUT_Bn VOUT_BnOutput voltage configurable range0.33.34V 4.93a CIN_Bn Input filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 3 22 µF 4.93aCIN_Bn IN_BnInput filtering capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER0322µF 4.93b COUT-Local_Bn Output capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 10 22 µF 4.93bCOUT-Local_Bn OUT-Local_BnOutput capacitance, local#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER11022µF 4.93c COUT-TOTAL_Bn Output capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 100 500 µF 4.93cCOUT-TOTAL_Bn OUT-TOTAL_BnOutput capacitance, total (local and POL)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER1100500µF 4.94a LBn Power inductor Inductance 700 1000 1300 nH 4.94aLBn BnPower inductorInductance70010001300nH 4.94b DCR 10 mΩ 4.94bDCR10mΩ 4.95 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4 13 mA 4.95IQ_PWM Q_PWMPWM mode Quiescent currentIOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3, BUCK4OUT_Bn13mA 4.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV 4.166aVOUT_DC_Bx OUT_DC_BxDC output voltage accuracy, includes voltage reference, DC load and line regulations and temperatureVVOUT_Bx < 1 V, PWM modeVOUT_Bx–1010mV 4.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1% 4.166bVVOUT_Bx ≥ 1 V, PWM modeVOUT_Bx–1%1% 4.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV 4.166dVVOUT_Bx ≥ 1 V, PFM modeVOUT_Bx-1% - 10 mV1% + 15 mV 4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV 4.166cVVOUT_Bx < 1 V, PFM modeVOUT_Bx–2025mV 4.97a TLDSR_SP Transient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 35 mV 4.97aTLDSR_SP LDSR_SPTransient load step response#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER60.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM modeVOUT_Bn OUT_Bnrf35mV 4.97b 0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 17 mV 4.97b0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf17mV 4.97c 1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 3.5% 4.97c1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM modeVOUT_BnOUT_Bnrf3.5% 4.98 TLNSR Transient line response VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) -20 ±5 20 mV 4.98TLNSR LNSRTransient line responseVPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bn = IOUT_Bn(max) PVIN_BnrfOUT_BnOUT_Bn(max)-20±520mV 4.99a VOUT_Ripple Ripple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 PWM mode 3 7.5 mVPP 4.99aVOUT_Ripple OUT_RippleRipple voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER6PWM mode37.5mVPP PP 4.99b PFM mode 15 25 mVPP 4.99bPFM mode1525mVPP PP 4.151 IPFM-PWM PFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA 4.151IPFM-PWM PFM-PWMPFM to PWM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn290mA 4.152 IPWM-PFM PWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA 4.152IPWM-PFM PWM-PFMPWM to PFM switch current threshold#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161122/SLVSE82_BUCK_FOOTER5Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn230mA 4.153 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA 4.153IPWM-PFM_HYST PWM-PFM_HYSTPWM to PFM switch current hysteresisAuto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0VPVIN_BnVOUT_Bn50mA Switching Characteristics Switching Characteristics 20.1a fSW Steady state switching frequency in PWM mode (NVM configurable) 2.2 MHz setting, internal clock 2 2.2 2.4 MHz 20.1afSW SWSteady state switching frequency in PWM mode (NVM configurable)2.2 MHz setting, internal clock22.22.4MHz 20.1b 4.4 MHz setting, internal clock 4 4.4 4.8 MHz 20.1b4.4 MHz setting, internal clock44.44.8MHz 20.1d 2.2 MHz setting, internal clock, spread spectrum 1.76 2.2 2.64 MHz 20.1d2.2 MHz setting, internal clock, spread spectrum1.762.22.64MHz 20.1e 4.4 MHz setting, internal clock, spread spectrum 3.5 4.4 5.3 MHz 20.1e4.4 MHz setting, internal clock, spread spectrum3.54.45.3MHz 20.1f 2.2 MHz setting, synchronized to external clock 1.76 2.2 2.64 MHz 20.1f2.2 MHz setting, synchronized to external clock1.762.22.64MHz 20.1g 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3 MHz 20.1g4.4 MHz setting, synchronized to external clock3.54.45.3MHz 20.2a fSW_max Automatic maximum switching frequency scaling in PWM mode 0.6 V ≤ VVOUT_Bn 4.4 MHz 20.2afSW_max SW_maxAutomatic maximum switching frequency scaling in PWM mode0.6 V ≤ VVOUT_Bn VOUT_Bn4.4MHz 20.2b 0.3 V ≤ VVOUT_Bn < 0.6 V 2.2 MHz 20.2b0.3 V ≤ VVOUT_Bn < 0.6 VVOUT_Bn2.2MHz Timing Requirements Timing Requirements 20.3 tsettle_Bn Settling time after voltage scaling From end of voltage ramp to within 15mV from target VOUT_DC_Bx 105 µs 20.3tsettle_Bn settle_BnSettling time after voltage scalingFrom end of voltage ramp to within 15mV from target VOUT_DC_Bx OUT_DC_Bx105µs 20.4 tstartup_Bn Start-up delay From enable to start of output voltage rise 100 150 218 µs 20.4tstartup_Bn startup_BnStart-up delayFrom enable to start of output voltage rise100150218µs 20.5a tdelay_OC Over-current detection delay Peak current limit triggering during everyswitching cycle 7 µs 20.5atdelay_OC delay_OCOver-current detection delayPeak current limit triggering during everyswitching cycle7µs 20.5b tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses 19 23 µs 20.5btdeglitch_OC deglitch_OCOver-current detection signal deglitch timeDigital deglitch time for detected signal.Time duration to filter out short positiveand negative pulses1923µs 20.6 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection tointerrupt or PFSM trigger 30 µs 20.6tlatency_OC latency_OCOver-current signal latency time from detectionTotal delay from over-current detection tointerrupt or PFSM trigger30µs Input capacitors must be placed as close as possible to the device pins. When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators. The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature. Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current. SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN. The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output. Input capacitors must be placed as close as possible to the device pins.When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of regulators.The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature.Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output current.SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU.  Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5VPlease refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions.  All ripple specs are defined across POL capacitor in the described PDN.The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the buck output.Bx Reference Generator (BandGap) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs Reference Generator (BandGap) Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs Electrical Characteristics Electrical Characteristics 5.1 Max capacitance at AMUX pin Capacitance between AMUXOUT pin and thermal/ground pad 100 pF 5.1Max capacitance at AMUX pinCapacitance between AMUXOUT pin and thermal/ground pad100pF 5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V 5.2Output voltageMeasured at the AMUXOUT pin1.171.21.23V Timing Requirements Timing Requirements 21.1 tSU_REF Start-up time From AMUXOUT_EN=1 to the time bandgap voltage settles 30 µs 21.1tSU_REF SU_REFStart-up timeFrom AMUXOUT_EN=1 to the time bandgap voltage settles30µs Monitoring Functions
  Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software. Interrupt status signal is input signal for PGOOD deglitch logic. Monitoring Functions
  Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software. Interrupt status signal is input signal for PGOOD deglitch logic. Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6h LDOn_OV_THR = 0x7 90 100 110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs Electrical Characteristics: BUCK REGULATORS OUTPUT Electrical Characteristics: BUCK REGULATORS OUTPUT 7.1a VBUCK_OV_TH Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x0 2% 3% 4% 7.1aVBUCK_OV_TH BUCK_OV_THOvervoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn ≥ 1 V(1) OUT_Bn (1)BUCKn_OV_THR = 0x02%3%4% 7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.1bBUCKn_OV_THR = 0x12.5%3.5%4.5% 7.1c BUCKn_OV_THR = 0x2 3% 4% 5% 7.1cBUCKn_OV_THR = 0x23%4%5% 7.1d BUCKn_OV_THR = 0x3 4% 5% 6% 7.1dBUCKn_OV_THR = 0x34%5%6% 7.1e BUCKn_OV_THR = 0x4 5% 6% 7% 7.1eBUCKn_OV_THR = 0x45%6%7% 7.1f BUCKn_OV_THR = 0x5 6% 7% 8% 7.1fBUCKn_OV_THR = 0x56%7%8% 7.1g BUCKn_OV_THR = 0x6 7% 8% 9% 7.1gBUCKn_OV_THR = 0x67%8%9% 7.1h BUCKn_OV_THR = 0x7 9% 10% 11% 7.1hBUCKn_OV_THR = 0x79%10%11% 7.2a VBUCK_OV_TH_mv  Overvoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x0 20 30 40 mV 7.2aVBUCK_OV_TH_mv BUCK_OV_TH_mvOvervoltage monitoring for BUCK output, threshold accuracy, VOUT_Bn < 1 V(1) OUT_Bn(1)BUCKn_OV_THR = 0x0203040mV 7.2b BUCKn_OV_THR = 0x1 25 35 45 7.2bBUCKn_OV_THR = 0x1253545 7.2c BUCKn_OV_THR = 0x2 30 40 50 7.2cBUCKn_OV_THR = 0x2304050 7.2d BUCKn_OV_THR = 0x3 40 50 60 7.2dBUCKn_OV_THR = 0x3405060 7.2e BUCKn_OV_THR = 0x4 50 60 70 7.2eBUCKn_OV_THR = 0x4506070 7.2f BUCKn_OV_THR = 0x5 60 70 80 7.2fBUCKn_OV_THR = 0x5607080 7.2g BUCKn_OV_THR = 0x6 70 80 90 7.2gBUCKn_OV_THR = 0x6708090 7.2h BUCKn_OV_THR = 0x7 90 100 110 7.2hBUCKn_OV_THR = 0x790100110 7.3a VBUCK_UV_TH  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) BUCKn_UV_THR = 0x0 –4% –3% –2% 7.3aVBUCK_UV_TH BUCK_UV_THUndervoltage monitoring for buck output, threshold accuracy, VOUT_Bn  ≥ 1 V(1) OUT_Bn(1)BUCKn_UV_THR = 0x0–4%–3%–2% 7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.3bBUCKn_UV_THR = 0x1–4.5%–3.5%–2.5% 7.3c BUCKn_UV_THR = 0x2 –5% –4% –3% 7.3cBUCKn_UV_THR = 0x2–5%–4%–3% 7.3d BUCKn_UV_THR = 0x3 –6% –5% –4% 7.3dBUCKn_UV_THR = 0x3–6%–5%–4% 7.3e BUCKn_UV_THR = 0x4 –7% –6% –5% 7.3eBUCKn_UV_THR = 0x4–7%–6%–5% 7.3f BUCKn_UV_THR = 0x5 –8% –7% –6% 7.3fBUCKn_UV_THR = 0x5–8%–7%–6% 7.3g BUCKn_UV_THR = 0x6 –9% –8% –7% 7.3gBUCKn_UV_THR = 0x6–9%–8%–7% 7.3h BUCKn_UV_THR = 0x7 –11% –10% –9% 7.3hBUCKn_UV_THR = 0x7–11%–10%–9% 7.4a VBUCK_UV_TH_mv  Undervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x0 –40 –30 –20 mV 7.4aVBUCK_UV_TH_mv BUCK_UV_TH_mvUndervoltage monitoring for buck output, threshold accuracy, VOUT_Bn < 1 V(1) OUT_Bn (1)BUCKn_UV_THR = 0x0–40–30–20mV 7.4b BUCKn_UV_THR = 0x1 –45 –35 –25 7.4bBUCKn_UV_THR = 0x1–45–35–25 7.4c BUCKn_UV_THR = 0x2 –50 –40 –30 7.4cBUCKn_UV_THR = 0x2–50–40–30 7.4d BUCKn_UV_THR = 0x3 –60 –50 –40 7.4dBUCKn_UV_THR = 0x3–60–50–40 7.4e BUCKn_UV_THR = 0x4 –70 –60 –50 7.4eBUCKn_UV_THR = 0x4–70–60–50 7.4f BUCKn_UV_THR = 0x5 –80 –70 –60 7.4fBUCKn_UV_THR = 0x5–80–70–60 7.4g BUCKn_UV_THR = 0x6 –90 –80 –70 7.4gBUCKn_UV_THR = 0x6–90–80–70 7.4h BUCKn_UV_THR = 0x7 –110 –100 –90 7.4hBUCKn_UV_THR = 0x7–110–100–90 Electrical Characteristics: LDO REGULATOR OUTPUTS Electrical Characteristics: LDO REGULATOR OUTPUTS 7.5a VLDO_OV_TH Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 2% 3% 4% 7.5aVLDO_OV_TH LDO_OV_THOvervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 OUT_LDOn #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2LDOn_OV_THR = 0x02%3%4% 7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5% 7.5bLDOn_OV_THR = 0x12.5%3.5%4.5% 7.5c LDOn_OV_THR = 0x2 3% 4% 5% 7.5cLDOn_OV_THR = 0x23%4%5% 7.5d LDOn_OV_THR = 0x3 4% 5% 6% 7.5dLDOn_OV_THR = 0x34%5%6% 7.5e LDOn_OV_THR = 0x4 5% 6% 7% 7.5eLDOn_OV_THR = 0x45%6%7% 7.5f LDOn_OV_THR = 0x5 6% 7% 8% 7.5fLDOn_OV_THR = 0x56%7%8% 7.5g LDOn_OV_THR = 0x6 7% 8% 9% 7.5gLDOn_OV_THR = 0x67%8%9% 7.5h LDOn_OV_THR = 0x7 9% 10% 11% 7.5hLDOn_OV_THR = 0x79%10%11% 7.6a VLDO_OV_TH_mv Overvoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_OV_THR = 0x0 20 30 40 mV 7.6aVLDO_OV_TH_mv LDO_OV_TH_mvOvervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 OUT_LDOn #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2LDOn_OV_THR = 0x0203040mV 7.6b LDOn_OV_THR = 0x1 25 35 45 7.6bLDOn_OV_THR = 0x1253545 7.6c LDOn_OV_THR = 0x2 30 40 50 7.6cLDOn_OV_THR = 0x2304050 7.6d LDOn_OV_THR = 0x3 40 50 60 7.6dLDOn_OV_THR = 0x3405060 7.6e LDOn_OV_THR = 0x4 50 60 70 7.6eLDOn_OV_THR = 0x4506070 7.6f LDOn_OV_THR = 0x5 60 70 80 7.6fLDOn_OV_THR = 0x5607080 7.6g LDOn_OV_THR = 0x6 70 80 90 7.6gLDOn_OV_THR = 0x6708090 7.6h LDOn_OV_THR = 0x7 90 100 110 7.6hLDOn_OV_THR = 0x790100110 7.7a VLDO_UV_TH Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –4% –3% –2% 7.7aVLDO_UV_TH LDO_UV_THUndervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn ≥ 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 OUT_LDOn #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2LDOn_UV_THR = 0x0–4%–3%–2% 7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5% 7.7bLDOn_UV_THR = 0x1–4.5%–3.5%–2.5% 7.7c LDOn_UV_THR = 0x2 –5% –4% –3% 7.7cLDOn_UV_THR = 0x2–5%–4%–3% 7.7d LDOn_UV_THR = 0x3 –6% –5% –4% 7.7dLDOn_UV_THR = 0x3–6%–5%–4% 7.7e LDOn_UV_THR = 0x4 –7% –6% –5% 7.7eLDOn_UV_THR = 0x4–7%–6%–5% 7.7f LDOn_UV_THR = 0x5 –8% –7% –6% 7.7fLDOn_UV_THR = 0x5–8%–7%–6% 7.7g LDOn_UV_THR = 0x6 –9% –8% –7% 7.7gLDOn_UV_THR = 0x6–9%–8%–7% 7.7h LDOn_UV_THR = 0x7 –11% –10% –9% 7.7hLDOn_UV_THR = 0x7–11%–10%–9% 7.8a VLDO_UV_TH_mv Undervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 LDOn_UV_THR = 0x0 –40 –30 –20 mV 7.8aVLDO_UV_TH_mv LDO_UV_TH_mvUndervoltage monitoring for LDO output, threshold accuracy, VOUT_LDOn < 1 V#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2 OUT_LDOn #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE2LDOn_UV_THR = 0x0–40–30–20mV 7.8b LDOn_UV_THR = 0x1 –45 –35 –25 7.8bLDOn_UV_THR = 0x1–45–35–25 7.8c LDOn_UV_THR = 0x2 –50 –40 –30 7.8cLDOn_UV_THR = 0x2–50–40–30 7.8d LDOn_UV_THR = 0x3 –60 –50 –40 7.8dLDOn_UV_THR = 0x3–60–50–40 7.8e LDOn_UV_THR = 0x4 –70 –60 –50 7.8eLDOn_UV_THR = 0x4–70–60–50 7.8f LDOn_UV_THR = 0x5 –80 –70 –60 7.8fLDOn_UV_THR = 0x5–80–70–60 7.8g LDOn_UV_THR = 0x6 –90 –80 –70 7.8gLDOn_UV_THR = 0x6–90–80–70 7.8h LDOn_UV_THR = 0x7 –110 –100 –90 7.8hLDOn_UV_THR = 0x7–110–100–90 Electrical Characteristics: VCCA INPUT Electrical Characteristics: VCCA INPUT 7.9a VCCAOV_TH Overvoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_OV_THR = 0x0 2% 3% 4% 7.9aVCCAOV_TH OV_THOvervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3VCCA_OV_THR = 0x02%3%4% 7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5% 7.9bVCCA_OV_THR = 0x12.5%3.5%4.5% 7.9c VCCA_OV_THR = 0x2 3% 4% 5% 7.9cVCCA_OV_THR = 0x23%4%5% 7.9d VCCA_OV_THR = 0x3 4% 5% 6% 7.9dVCCA_OV_THR = 0x34%5%6% 7.9e VCCA_OV_THR = 0x4 5% 6% 7% 7.9eVCCA_OV_THR = 0x45%6%7% 7.9f VCCA_OV_THR = 0x5 6% 7% 8% 7.9fVCCA_OV_THR = 0x56%7%8% 7.9g VCCA_OV_THR = 0x6 7% 8% 9% 7.9gVCCA_OV_THR = 0x67%8%9% 7.9h VCCA_OV_THR = 0x7 9% 10% 11% 7.9hVCCA_OV_THR = 0x79%10%11% 7.10a VCCAUV_TH Undervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 VCCA_UV_THR = 0x0 -4% -3% -2% 7.10aVCCAUV_TH UV_THUndervoltage monitoring for VCCA input, threshold accuracy#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE3VCCA_UV_THR = 0x0-4%-3%-2% 7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5% 7.10bVCCA_UV_THR = 0x1-4.5%-3.5%-2.5% 7.10c VCCA_UV_THR = 0x2 -5% -4% -3% 7.10cVCCA_UV_THR = 0x2-5%-4%-3% 7.10d VCCA_UV_THR = 0x3 -6% -5% -4% 7.10dVCCA_UV_THR = 0x3-6%-5%-4% 7.10e VCCA_UV_THR = 0x4 -7% -6% -5% 7.10eVCCA_UV_THR = 0x4-7%-6%-5% 7.10f VCCA_UV_THR = 0x5 -8% -7% -6% 7.10fVCCA_UV_THR = 0x5-8%-7%-6% 7.10g VCCA_UV_THR = 0x6 -9% -8% -7% 7.10gVCCA_UV_THR = 0x6-9%-8%-7% 7.10h VCCA_UV_THR = 0x7 -11% -10% -9% 7.10hVCCA_UV_THR = 0x7-11%-10%-9% Timing Requirements Timing Requirements 26.30a tdelay_OV_UV BUCK and LDO OV/UV detection delay Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive 8 µs 26.30atdelay_OV_UV delay_OV_UVBUCK and LDO OV/UV detection delayDetection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdriveinin8µs 26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs 26.30btdelay_OV_UV delay_OV_UVVCCA OV/UV detection delayDetection delay with 30 mV over/underdrive12µs 26.31a tdeglitch1_OV_UV VCCA, BUCK and LDO OV/UV signal deglitch time VMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal 3.4 3.8 4.2 µs 26.31atdeglitch1_OV_UV deglitch1_OV_UVVCCA, BUCK and LDO OV/UV signal deglitch timeVMON_DEGLITCH_SEL = 0: Digital deglitch time for detected signal3.43.84.2µs 26.31b tdeglitch2_OV_UV VMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal 18 20 22 µs 26.31btdeglitch2_OV_UV deglitch2_OV_UVVMON_DEGLITCH_SEL = 1: Digital deglitch time for detected signal182022µs 26.32a tlatency1_OV_UV BUCK and LDO OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 13 µs 26.32atlatency1_OV_UV latency1_OV_UVBUCK and LDO OV/UV signal latency timeVMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM triggerinin13µs 26.32b tlatency2_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM trigger 30 µs 26.32btlatency2_OV_UV latency2_OV_UVVMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM triggerinin30µs 26.32b tlatency1_VCCA_OV_UV VCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13 µs 26.32btlatency1_VCCA_OV_UV latency1_VCCA_OV_UVVCCA OV/UV signal latency time VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 13µs 26.32b tlatency2_VCCA_OV_UV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger 30 µs 26.32btlatency2_VCCA_OV_UV latency2_VCCA_OV_UVVMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/underdrive to interrupt or PFSM trigger30µs 26.33a tdeglitch_PGOOD_rise PGOOD signal deglitch time Internal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 9.5 10.5 µs 26.33atdeglitch_PGOOD_rise deglitch_PGOOD_risePGOOD signal deglitch timeInternal logic signal transitions from invalid to valid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE49.510.5µs 26.33b tdeglitch_PGOOD_fall Internal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 0 µs 26.33btdeglitch_PGOOD_fall deglitch_PGOOD_fallInternal logic signal transitions from valid to invalid#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE4 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161113/SLVSE82-MONITOR-FOOTNOTE40µs The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software. The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software. Interrupt status signal is input signal for PGOOD deglitch logic. The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by software.The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software.The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by software. Interrupt status signal is input signal for PGOOD deglitch logic. Clocks, Oscillators, and PLL Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance. External capacitors must be used if crystal load capacitance > 6 pF. Clocks, Oscillators, and PLL Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance. External capacitors must be used if crystal load capacitance > 6 pF. Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7b Internal Capacitors 9.5 12 14.5 pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.4 External clock input debounce time for clock detection 20 µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11b SS_DEPTH = 0x2 8.4% Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz Electrical Characteristics: CRYSTAL Electrical Characteristics: CRYSTAL 6.1 Crystal frequency 32768 Hz 6.1Crystal frequency32768Hz 6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm 6.2Crystal frequency toleranceParameter of crystal, TJ = 25°CJ–2020ppm 6.4 Crystal series resistance At fundamental frequency 90 kΩ 6.4Crystal series resistanceAt fundamental frequency90kΩ 6.5 Oscillator drive power The power dissipated in the crystal during oscillator operation 0.1 0.5 μW 6.5Oscillator drive powerThe power dissipated in the crystal during oscillator operation0.10.5μW 6.6 Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 Corresponding to crystal frequency, including parasitic capacitances 6 12.5 pF 6.6Crystal Load capacitance#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE1Corresponding to crystal frequency, including parasitic capacitances612.5pF 6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF 6.7Crystal shunt capacitanceParameter of crystal1.42.6pF Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 6.7a Load capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 External Capacitors 0 13 pF 6.7aLoad capacitance on OSC32KIN and OSC32KOUT (parallel mode, including parasitic of PCB for external capacitor)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161091/SF_XTAL_FOOTNOTE2External Capacitors013pF 6.7b Internal Capacitors 9.5 12 14.5 pF 6.7bInternal Capacitors9.51214.5pF Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK 23.1 Crystal Oscillator output frequency Typical with specified load capacitors 32768 Hz 23.1Crystal Oscillator output frequencyTypical with specified load capacitors32768Hz 23.2 Crystal Oscillator Output duty cycle Parameter of crystal, TJ = 25°C 40% 50% 60% 23.2Crystal Oscillator Output duty cycleParameter of crystal, TJ = 25°CJ 40%50%60% 23.3 Crystal Oscillator rise and fall time 10% to 90%, with 10 pF load capacitance 10 20 ns 23.3Crystal Oscillator rise and fall time10% to 90%, with 10 pF load capacitance1020ns 23.4 Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200 ms 23.4Crystal Oscillator Settling time From Oscillator enable to reaching ±1% of final output frequency   200ms Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK 23.10 20 MHz RC Oscillator output frequency 19 20 21 MHz 23.1020 MHz RC Oscillator output frequency192021MHz 23.12 128 kHz RC Oscillator output frequency 121 128 135 kHz 23.12128 kHz RC Oscillator output frequency121128135kHz Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT 22.1a External input clock nominal frequency EXT_CLK_FREQ = 0x0 1.1 MHz 22.1aExternal input clock nominal frequencyEXT_CLK_FREQ = 0x01.1MHz 22.1b EXT_CLK_FREQ = 0x1 2.2 22.1bEXT_CLK_FREQ = 0x12.2 22.1c EXT_CLK_FREQ = 0x2 4.4 22.1cEXT_CLK_FREQ = 0x24.4 22.2a External input clock required accuracy from nominal frequency SS_DEPTH = 0x0 –18% 18% 22.2aExternal input clock required accuracy from nominal frequencySS_DEPTH = 0x0–18%18% 22.2b SS_DEPTH = 0x1 –12% 12% 22.2bSS_DEPTH = 0x1–12%12% 22.2c SS_DEPTH = 0x2 –10% 10% 22.2cSS_DEPTH = 0x2–10%10% 22.13a Logic low time for SYNCCLKIN clock 40 ns 22.13aLogic low time for SYNCCLKIN clock40ns 22.13b Logic high time for SYNCCLKIN clock 40 ns 22.13bLogic high time for SYNCCLKIN clock40ns 22.3 External clock detection delay for missing clock detection 1.8 µs 22.3External clock detection delay for missing clock detection1.8µs 22.4 External clock input debounce time for clock detection 20 µs 22.4External clock input debounce time for clock detection20µs 22.5 Clock change delay (internal to external) From valid clock detection to use of external clock 600 µs 22.5Clock change delay (internal to external)From valid clock detection to use of external clock600µs 22.7a SYNCCLKOUT clock nominal frequency SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz 22.7aSYNCCLKOUT clock nominal frequencySYNCCLKOUT_FREQ_SEL = 0x11.1MHz 22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz 22.7bSYNCCLKOUT_FREQ_SEL = 0x22.2MHz 22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz 22.7cSYNCCLKOUT_FREQ_SEL = 0x34.4MHz 22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60% 22.8SYNCCLKOUT duty-cycleCycle-to-cycle40%50%60% 22.9 SYNCCLKOUT output buffer external load 5 35 50 pF 22.9SYNCCLKOUT output buffer external load53550pF 22.11a Spread spectrum variation for  nominal switching frequency SS_DEPTH = 0x1 6.3% 22.11aSpread spectrum variation for  nominal switching frequencySS_DEPTH = 0x16.3% 22.11b SS_DEPTH = 0x2 8.4% 22.11bSS_DEPTH = 0x28.4% Timing Requirements: Clock Monitors Timing Requirements: Clock Monitors 26.7a tlatency_CLKfail Clock Monitor Failure signal latency from occurrence of error Failure on 20MHz system clock 10 µs 26.7atlatency_CLKfail latency_CLKfailClock Monitor Failure signal latency from occurrence of errorFailure on 20MHz system clock10µs 26.7b Failure on 128KHz monitoring clock 40 µs 26.7bFailure on 128KHz monitoring clock40µs 26.8 tlatency_CLKdrift Clock Monitor Drift signal latency from detection 115 µs 26.8tlatency_CLKdrift latency_CLKdriftClock Monitor Drift signal latency from detection115µs 26.9 fsysclk Internal system clock 19 20 21 MHz 26.9fsysclk sysclkInternal system clock192021MHz 26.10 CLKdrift_TH Threshold for internal system clock frequency drift detection -20% 20% 26.10CLKdrift_THThreshold for internal system clock frequency drift detection-20%20% 26.11 CLKfail_TH Threshold for internal system clock stuck at high or stuck at low detection 10 MHz 26.11CLKfail_THThreshold for internal system clock stuck at high or stuck at low detection10MHz Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance. External capacitors must be used if crystal load capacitance > 6 pF. Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance.External capacitors must be used if crystal load capacitance > 6 pF. Thermal Monitoring and Shutdown Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs Thermal Monitoring and Shutdown Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs Electrical Characteristics Electrical Characteristics 8.1a TWARN_0 TWARN_INT thermal warning threshold (no hysteresis) TWARN_LEVEL = 0 120 130 140 °C 8.1aTWARN_0 WARN_0TWARN_INT thermal warning threshold (no hysteresis)TWARN_LEVEL = 0120130140°C 8.1b TWARN_1 TWARN_LEVEL = 1 130 140 150 °C 8.1bTWARN_1 WARN_1TWARN_LEVEL = 1130140150°C 8.2a TSD_orderly_0 TSD_ORD_INT thermal shutdown  rising threshold TSD_ORD_LEVEL = 0 130 140 150 °C 8.2aTSD_orderly_0 SD_orderly_0TSD_ORD_INT thermal shutdown  rising thresholdTSD_ORD_LEVEL = 0130140150°C 8.2b TSD_orderly_1 TSD_ORD_LEVEL = 1 135 145 155 °C 8.2bTSD_orderly_1 SD_orderly_1TSD_ORD_LEVEL = 1135145155°C 8.2c TSD_orderly_hys_0 TSD_ORD_INT thermal shutdown hysteresis TSD_ORD_LEVEL = 0 10 °C 8.2cTSD_orderly_hys_0 SD_orderly_hys_0TSD_ORD_INT thermal shutdown hysteresisTSD_ORD_LEVEL = 010°C 8.2d TSD_orderly_hys_1 TSD_ORD_LEVEL = 1 5 °C 8.2dTSD_orderly_hys_1 SD_orderly_hys_1TSD_ORD_LEVEL = 15°C 8.3a TSD_imm TSD_IMM_INT thermal shutdown rising threshold 140 150 160 °C 8.3aTSD_imm SD_immTSD_IMM_INT thermal shutdown rising threshold140150160°C 8.3b TSD_imm_hys TSD_IMM_INT thermal  shutdown hysteresis 5 °C 8.3bTSD_imm_hys SD_imm_hysTSD_IMM_INT thermal  shutdown hysteresis5°C Timing Requirements Timing Requirements 26.6 tlatency_TSD TSD signal latency from detection   425 µs 26.6tlatency_TSD latency_TSDTSD signal latency from detection 425µs System Control Thresholds Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms System Control Thresholds Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms Electrical Characteristics Electrical Characteristics 9.1 VPOR_Falling VCCA UVLO/POR falling threshold Measured on VCCA pin 2.7 2.75 2.8 V 9.1VPOR_Falling POR_FallingVCCA UVLO/POR falling thresholdMeasured on VCCA pin2.72.752.8V 9.2 VPOR_Rising VCCA UVLO/POR rising threshold Measured on VCCA pin 2.7 3 V 9.2VPOR_Rising POR_RisingVCCA UVLO/POR rising thresholdMeasured on VCCA pin2.73V 9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV 9.3VPOR_Hyst POR_HystVCCA UVLO/POR hysteresis100mV 9.5aa VVCCA_OVP_Rising VCCA OVP rising threshold Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V 9.5aaVVCCA_OVP_Rising VCCA_OVP_RisingVCCA OVP rising thresholdMeasured on VCCA pin. VCCA_PG_SET = 0b3.94.04.1V 9.5ab Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V 9.5abMeasured on VCCA pin. VCCA_PG_SET = 1b5.65.75.8V 9.5b VVCCA_OVP_Hyst VCCA OVP hysteresis 50 mV 9.5bVVCCA_OVP_Hyst VCCA_OVP_HystVCCA OVP hysteresis50mV 9.15 VVCCA_PVIN_SR Input slew rate of VCCA and PVIN_x supplies Measured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.15VVCCA_PVIN_SR VCCA_PVIN_SRInput slew rate of VCCA and PVIN_x suppliesMeasured at VCCA and PVIN_x pins as voltage rises from 0V to VPOR_Rising POR_Rising60mV/µs 9.16 VVIO_SR Input slew rate of VIO supply Measured at VIO pin as voltage rises from 0V to VPOR_Rising 60 mV/µs 9.16VVIO_SR VIO_SRInput slew rate of VIO supplyMeasured at VIO pin as voltage rises from 0V to VPOR_Rising POR_Rising60mV/µs 9.17 VVBACKUP_SR Input slew rate of VBACKUP supply Measured at VBACKUP pin 60 mV/µs 9.17VVBACKUP_SR VBACKUP_SRInput slew rate of VBACKUP supplyMeasured at VBACKUP pin60mV/µs Timing Requirements Timing Requirements 26.3a tlatency_VCCAOVP VCCA_OVP signal latency from detection VCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT   15 µs 26.3atlatency_VCCAOVP latency_VCCAOVP VCCA_OVP signal latency from detectionVCCA_OVP signalVCCA_PG_SEL = 0b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT  Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 15µs 26.3b VCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 µs 26.3bVCCA_PG_SEL = 1b. Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT Total delay from detection of VCCA_OVP to the rise of VCCA_OVP_INT 15 15µs 26.4 tlatency_VCCAUVLO VCCA_UVLO signal latency from detection Measured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signal 10 µs 26.4tlatency_VCCAUVLO latency_VCCAUVLOVCCA_UVLO signal latency from detectionMeasured time between VVCCA falling from 3.3 V to 2.7 V with ≤ 100mv/µs slope, to the detection of VCCA_UVLO signalVCCA10µs 26.5 tlatency_VINT LDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12 µs 26.5tlatency_VINT latency_VINTLDOVINT OVP and UVLO signal latency from detection With 25-mV overdrive 12µs 26.15 tLBISTrun Run time for LBIST 1.8 ms 26.15tLBISTrun LBISTrunRun time for LBIST1.8ms 26.16 tINIT_NVM_ANALOG Device initialization time to load default values for NVM registers, and start-up analog circuits 2 ms 26.16tINIT_NVM_ANALOG INIT_NVM_ANALOGDevice initialization time to load default values for NVM registers, and start-up analog circuits2ms 26.17 tINIT_REF_CLK_LDO Device initialization time for reference bandgaps, system clock, and internal LDOs 1 ms 26.17tINIT_REF_CLK_LDO INIT_REF_CLK_LDODevice initialization time for reference bandgaps, system clock, and internal LDOs1ms Current Consumption Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA Current Consumption Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA Over operating free-air temperature range (unless otherwise noted). POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA Electrical Characteristics Electrical Characteristics 10.2 IBACKUP_RTC Backup current consumption, regulators disabled From VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. 7 10 µA 10.2IBACKUP_RTC BACKUP_RTCBackup current consumption, regulators disabledFrom VBACKUP pin. PWRON/ENABLE deactivated. Device powered by the backup battery source. VCCA = 0V. VIO = 0V.  VBACKUP = 3.3V.  Only 32-kHz crystal oscillator and RTC counters are functioning. TJ = 25℃. J710µA 10.3a ILP_STANDBY Low Power Standby current consumption, regulators disabled Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 11 24 µA 10.3aILP_STANDBY LP_STANDBYLow Power Standby current consumption, regulators disabledCombined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx =  PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal oscillator and RTC digital is functioning. GPIO pins in LDOVRTC domain are active. All monitors are off.  TJ = 25℃. 32-kHz crystal oscillator and RTC digital is functioning. J1124µA 10.5a ISTANDBY Standby current consumption Combined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0. 50 62 µA 10.5aISTANDBY STANDBYStandby current consumptionCombined current from VCCA, and PVIN_x. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. VCCA_VMON_EN=0.J5062µA 10.6a ISLEEP_3V3 Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 290 363 µA 10.6aISLEEP_3V3 SLEEP_3V3Sleep current consumptionCombined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled.J290363µA 10.6b ISLEEP_5V Sleep current consumption Combined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled. 300 375 µA 10.6bISLEEP_5V SLEEP_5VSleep current consumptionCombined current from VCCA and PVIN_x pins. VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃. One buck regulator enabled in PFS/PWM mode, no load.  Buck and VCCA OV/UV monitoring enabled.J300375µA Backup Battery Charger Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV.  When VCCA-VBACKUP is ≤ 200mV, the charger remains fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.  Backup Battery Charger Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV.  When VCCA-VBACKUP is ≤ 200mV, the charger remains fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.  Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6b With additional capacitor in parallel 1000 Electrical Characteristics Electrical Characteristics 27.1a Icharge Charging current VBACKUP = 1 V, BB_ICHR = 0x0 100 µA 27.1aIcharge chargeCharging currentVBACKUP = 1 V, BB_ICHR = 0x0100µA 27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500 27.1bVBACKUP = 1 V, BB_ICHR = 0x1500 27.2a VEOC End of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W BB_VEOC = 0x0 2.4 2.5 2.6 V 27.2aVEOC EOCEnd of charge voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0W #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161116/SFCHSBNAXV0WBB_VEOC = 0x02.42.52.6V 27.2b BB_VEOC = 0x1 2.7 2.8 2.9 27.2bBB_VEOC = 0x12.72.82.9 27.2c BB_VEOC = 0x2 2.9 3 3.1 27.2cBB_VEOC = 0x22.933.1 27.2d BB_VEOC = 0x3 3.2 3.3 3.4 27.2dBB_VEOC = 0x33.23.33.4 27.3 Iq_CHGR Quiescent current of backup battery charger End of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin 5 9 µA 27.3Iq_CHGR q_CHGRQuiescent current of backup battery chargerEnd of charge, charger enabled, VCCA - VBACKUP > 200 mV.  Measured from VCCA pin59µA 27.4a Iq_CHGR_OFF Off current of backup battery charger VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C 10 100 nA 27.4aIq_CHGR_OFF q_CHGR_OFFOff current of backup battery chargerVCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. Tj < 125°C10100nA 27.4b VCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C 250 27.4bVCCA - VBACKUP > 200 mV. Charger disabled. Device not in BACKUP state. 125°C < Tj < 150°C250 27.5 CBKUP Backup battery capacitance with additional capacitor Additional capacitor added when backup battery ESR > 20 Ω 1 2.2 4 µF 27.5CBKUP BKUPBackup battery capacitance with additional capacitorAdditional capacitor added when backup battery ESR > 20 Ω12.24µF 27.6a RBKUP_ESR Backup battery series resistance Without additional capacitor in parallel 20 Ω 27.6aRBKUP_ESR BKUP_ESRBackup battery series resistanceWithout additional capacitor in parallel20Ω 27.6b With additional capacitor in parallel 1000 27.6bWith additional capacitor in parallel1000 End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV.  When VCCA-VBACKUP is ≤ 200mV, the charger remains fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.  End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV.  When VCCA-VBACKUP is ≤ 200mV, the charger remains fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.  Digital Input Signal Parameters Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not available. Digital Input Signal Parameters Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not available. Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.3 Hysteresis 150 mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.6 Hysteresis 150 mV Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs Electrical Characteristics: nPWRON/ENABLE Electrical Characteristics: nPWRON/ENABLE 11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V 11.1VIL(VCCA) IL(VCCA)Low-level input voltage-0.300.54V 11.2 VIH(VCCA) High-level input voltage 1.26 V 11.2VIH(VCCA) IH(VCCA)High-level input voltage1.26V 11.3 Hysteresis 150 mV 11.3Hysteresis150mV Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins 11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V 11.4VIL(DIG) IL(DIG)Low-level input voltage-0.300.54V 11.5 VIH(DIG) High-level input voltage 1.26 V 11.5VIH(DIG) IH(DIG)High-level input voltage1.26V 11.6 Hysteresis 150 mV 11.6Hysteresis150mV Timing Requirements: nPWRON/ENABLE Timing Requirements: nPWRON/ENABLE 24.1a tLPK_TIME nPWRON Long Press Key time 8 s 24.1atLPK_TIME LPK_TIMEnPWRON Long Press Key time8s 24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms 24.1btdegl_PWRON degl_PWRONnPWRON button deglitch timeENABLE_DEGLITCH_EN = 1485052ms 24.2 tdegl_ENABLE ENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR ENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available 6 8 10 µs 24.2tdegl_ENABLE degl_ENABLEENABLE signal deglitch time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WOR #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000161096/SF87UUTB1WORENABLE_EGLITCH_EN = 1, exclude when activated under LP_STANDBY state while the system clock is not available6810µs Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals 24.3 tWKUP_LP Time from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states 5 ms 24.3tWKUP_LP WKUP_LPTime from valid GPIx assertion until device wakes up from LP_STANDBY state to ACTIVE or MCU ONLY states5ms 25.1a tdegl_GPIx GPIx and nSLEEPx signal deglitch time GPIOn_DEGLITCH_EN = 1 6 8 10 µs 25.1atdegl_GPIx degl_GPIxGPIx and nSLEEPx signal deglitch timeGPIOn_DEGLITCH_EN = 16810µs 25.2a tSTARTUP Time from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion 5 ms 25.2atSTARTUP STARTUPTime from receiving nPWRON/ENABLE trigger in STANDBY state to nRSTOUT assertion5ms 25.2b Time from a valid GPIx assertion until device starts power-up sequence from a low power state LDOVINT = 1.8V 1.5 ms 25.2bTime from a valid GPIx assertion until device starts power-up sequence from a low power stateLDOVINT = 1.8V1.5ms 25.3 tSLEEP Time from nSLEEPx assertion until device starts power-down sequence to enter a low power state LDOVINT = 1.8V 1.5 ms 25.3tSLEEP SLEEPTime from nSLEEPx assertion until device starts power-down sequence to enter a low power stateLDOVINT = 1.8V1.5ms 25.4a tWK_PW_MIN Minimum valid input pulse width for the WKUP input signals input through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state 40 ns 25.4atWK_PW_MIN WK_PW_MINMinimum valid input pulse width for the WKUP input signalsinput through LP_WKUP1 and LP_WKUP2 (GPIO3 or GPIO4) pins while the device is in LP_STANDBY state40ns 25.4b input through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states 200 ns 25.4binput through WKUP1, WKUP2, LP_WKUP1 and LP_WKUP2 pins while the device is in mission states200ns 25.5a tWD_DIS DISABLE_WDOG input signal deglitch time 24 30 36 µs 25.5atWD_DIS WD_DISDISABLE_WDOG input signal deglitch time243036µs 25.5b tWD_pulse TRIG_WDOG input signal deglitch time 24 30 36 µs 25.5btWD_pulse WD_pulseTRIG_WDOG input signal deglitch time243036µs ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not available. ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not available. Digital Output Signal Parameters
  Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs Digital Output Signal Parameters
  Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.3 Supply for external pullup resistor, open drain VIO V Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins 12.11 VOL(VIO)_20mA Low-level output voltage, push-pull and open-drain IOL = 20 mA 0.4 V 12.11VOL(VIO)_20mA OL(VIO)_20mALow-level output voltage, push-pull and open-drainIOL = 20 mAOL0.4V 12.12 VOH(VIO) High-level output voltage, push-pull  IOH = 3 mA VIO – 0.4 V 12.12VOH(VIO) OH(VIO)High-level output voltage, push-pull IOH = 3 mAOHVIO – 0.4V Electrical Characteristics: Output Signals through GPO3 and GPO4 pins Electrical Characteristics: Output Signals through GPO3 and GPO4 pins 12.13 VOL(DIG) Low-level output voltage, push-pull IOL = 3 mA 0.4 V 12.13VOL(DIG) OL(DIG)Low-level output voltage, push-pullIOL = 3 mAOL0.4V 12.14 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V 12.14VOH(DIG) OH(DIG)High-level output voltage, push-pullIOH = 3 mAOH1.4V Electrical Characteristics: Output Signals through GPO5 and GPO6 pins Electrical Characteristics: Output Signals through GPO5 and GPO6 pins 12.4 VOL(DIG)_20mA Low-level output voltage, push-pull IOL = 20 mA 0.4 V 12.4VOL(DIG)_20mA OL(DIG)_20mALow-level output voltage, push-pullIOL = 20 mAOL0.4V 12.5 VOH(DIG) High-level output voltage, push-pull IOH = 3 mA 1.4 V 12.5VOH(DIG) OH(DIG)High-level output voltage, push-pullIOH = 3 mAOH1.4V Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins 12.1 VOL(VIO) Low-level output voltage, push-pull and open-drain IOL = 3 mA 0.4 V 12.1VOL(VIO) OL(VIO)Low-level output voltage, push-pull and open-drainIOL = 3 mAOL0.4V 12.2 VOH(VIO) High-level output voltage, push-pull IOH = 3 mA VIO – 0.4 V 12.2VOH(VIO) OH(VIO)High-level output voltage, push-pullIOH = 3 mAOHVIO – 0.4V 12.3 Supply for external pullup resistor, open drain VIO V 12.3Supply for external pullup resistor, open drainVIOV Electrical Characteristics:nINT, nRSTOUT Electrical Characteristics:nINT, nRSTOUT 12.7 VOL(nINT) Low-level output voltage for nINT pin IOL = 20 mA 0.4 V 12.7VOL(nINT) OL(nINT)Low-level output voltage for nINT pinIOL = 20 mAOL0.4V 12.8 VOL(nRSTOUT) Low-level output voltage for nRSTOUT and nRSTOUT_SoC pin IOL = 20 mA 0.4 V 12.8VOL(nRSTOUT) OL(nRSTOUT)Low-level output voltage for nRSTOUT and nRSTOUT_SoC pinIOL = 20 mAOL0.4V Timing Requirements Timing Requirements 12.10 tgate_readback Gating time for readback monitor Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs 12.10tgate_readback gate_readbackGating time for readback monitorSignal level change or GPIO selection (GPIOn_SEL)8.89.6µs I/O Pullup and Pulldown Resistance Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ I/O Pullup and Pulldown Resistance Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ Electrical Characteristics Electrical Characteristics 13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ 13.1anPWRON pullup resistancenPWRON IO buffer internal pull up to VCCA supply280400520kΩ 13.1b ENABLE pullup and pulldown resistance ENABLE IO buffer internal pull up to VCCA supply and pull down to ground 280 400 520 kΩ 13.1bENABLE pullup and pulldown resistanceENABLE IO buffer internal pull up to VCCA supply and pull down to ground280400520kΩ 13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ 13.2GPIO pullup resistanceGPIO1 -11 pins configured as input with internal pullup280400520kΩ 13.3 GPIO pulldown resistance GPIO1 - 11 pins configured as inputs with internal pulldown  280 400 520 kΩ 13.3GPIO pulldown resistanceGPIO1 - 11 pins configured as inputs with internal pulldown 280400520kΩ 13.4 nRSTOUT and nRSTOUT_SoC pullup resistance Internal pullup to VIO supply when output driven high 8 10 12 kΩ 13.4nRSTOUT and nRSTOUT_SoC pullup resistanceInternal pullup to VIO supply when output driven high81012kΩ I²C Interface Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 I²C Interface2 Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POSPARAMETERTEST CONDITIONSMINTYPMAXUNIT Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1b Fast mode 400 16.1c Fast mode+ 1 MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2b Fast mode 1.3 16.2c Fast mode+ 0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2e High-speed mode, Cb = 400 pF 320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3b Fast mode 0.6 16.3c Fast mode+ 0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3e High-speed mode, Cb = 400 pF 120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4b Fast mode 100 16.4c Fast mode+ 50 16.4d High-speed mode 10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5b Fast mode 10 900 16.5c Fast mode+ 10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6b Fast mode 0.6 16.6c Fast mode+ 0.26 16.6d High-speed mode 160 ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7b Fast mode 0.6 16.7c Fast mode+ 0.26 16.7d High-speed mode 160 ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8b Fast mode 1.3 16.8c Fast mode+ 0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9b Fast mode 0.6 16.9c Fast mode+ 0.26 16.9d High-speed mode 160 ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10b Fast mode 20 300 16.10c Fast mode+ 120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10e High-speed mode, Cb = 400 pF 20 160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11b Fast mode 6.5 300 16.11c Fast mode+ 6.5 120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11e High-speed mode, Cb = 400 pF 13 160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12b Fast mode 20 300 16.12c Fast mode+ 120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12e High-speed mode, Cb = 400 pF 20 80 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14b Fast mode 6.5 300 16.14c Fast mode+ 6.5 120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14e High-speed mode, Cb = 400 pF 20 80 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15b High-speed mode 10 Electrical Characteristics Electrical Characteristics 14.1 CB Capacitive load for SDA and SCL 400 pF 14.1CB BCapacitive load for SDA and SCL400pF Timing Requirements Timing Requirements 16.1a ƒSCL Serial clock frequency Standard mode 100 kHz 16.1aƒSCL SCLSerial clock frequencyStandard mode100kHz 16.1b Fast mode 400 16.1bFast mode400 16.1c Fast mode+ 1 MHz 16.1cFast mode+1MHz 16.1d High-speed mode, Cb = 100 pF 3.4 16.1dHigh-speed mode, Cb = 100 pFb3.4 16.1e High-speed mode, Cb = 400 pF 1.7 16.1eHigh-speed mode, Cb = 400 pFb1.7 16.2a tLOW SCL low time Standard mode 4.7 µs 16.2atLOW LOWSCL low timeStandard mode4.7µs 16.2b Fast mode 1.3 16.2bFast mode1.3 16.2c Fast mode+ 0.5 16.2cFast mode+0.5 16.2d High-speed mode, Cb = 100 pF 160 ns 16.2dHigh-speed mode, Cb = 100 pFb160ns 16.2e High-speed mode, Cb = 400 pF 320 16.2eHigh-speed mode, Cb = 400 pFb320 16.3a tHIGH SCL high time Standard mode 4 µs 16.3atHIGH HIGHSCL high timeStandard mode4µs 16.3b Fast mode 0.6 16.3bFast mode0.6 16.3c Fast mode+ 0.26 16.3cFast mode+0.26 16.3d High-speed mode, Cb = 100 pF 60 ns 16.3dHigh-speed mode, Cb = 100 pFb60ns 16.3e High-speed mode, Cb = 400 pF 120 16.3eHigh-speed mode, Cb = 400 pFb120 16.4a tSU;DAT Data setup time Standard mode 250 ns 16.4atSU;DAT SU;DATData setup timeStandard mode250ns 16.4b Fast mode 100 16.4bFast mode100 16.4c Fast mode+ 50 16.4cFast mode+50 16.4d High-speed mode 10 16.4dHigh-speed mode10 16.5a tHD;DAT Data hold time Standard mode 10 3450 ns 16.5atHD;DAT HD;DATData hold timeStandard mode103450ns 16.5b Fast mode 10 900 16.5bFast mode10900 16.5c Fast mode+ 10 16.5cFast mode+10 16.5d High-speed mode, Cb = 100 pF 10 70 ns 16.5dHigh-speed mode, Cb = 100 pFb1070ns 16.5e High-speed mode, Cb = 400 pF 10 150 16.5eHigh-speed mode, Cb = 400 pFb10150 16.6a tSU;STA Setup time for a start or a REPEATED START condition Standard mode 4.7 µs 16.6atSU;STA SU;STASetup time for a start or a REPEATED START conditionStandard mode4.7µs 16.6b Fast mode 0.6 16.6bFast mode0.6 16.6c Fast mode+ 0.26 16.6cFast mode+0.26 16.6d High-speed mode 160 ns 16.6dHigh-speed mode160ns 16.7a tHD;STA Hold time for a start or a REPEATED START condition Standard mode 4 µs 16.7atHD;STA HD;STAHold time for a start or a REPEATED START conditionStandard mode4µs 16.7b Fast mode 0.6 16.7bFast mode0.6 16.7c Fast mode+ 0.26 16.7cFast mode+0.26 16.7d High-speed mode 160 ns 16.7dHigh-speed mode160ns 16.8a tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs 16.8atBUF BUFBus free time between a STOP and START conditionStandard mode4.7µs 16.8b Fast mode 1.3 16.8bFast mode1.3 16.8c Fast mode+ 0.5 16.8cFast mode+0.5 16.9a tSU;STO Setup time for a STOP condition Standard mode 4 µs 16.9atSU;STO SU;STOSetup time for a STOP conditionStandard mode4µs 16.9b Fast mode 0.6 16.9bFast mode0.6 16.9c Fast mode+ 0.26 16.9cFast mode+0.26 16.9d High-speed mode 160 ns 16.9dHigh-speed mode160ns 16.10a trDA Rise time of SDA signal Standard mode 1000 ns 16.10atrDA rDARise time of SDA signalStandard mode1000ns 16.10b Fast mode 20 300 16.10bFast mode20300 16.10c Fast mode+ 120 16.10cFast mode+120 16.10d High-speed mode, Cb = 100 pF 10 80 16.10dHigh-speed mode, Cb = 100 pFb1080 16.10e High-speed mode, Cb = 400 pF 20 160 16.10eHigh-speed mode, Cb = 400 pFb20160 16.11a tfDA Fall time of SDA signal Standard mode 300 ns 16.11atfDA fDAFall time of SDA signalStandard mode300ns 16.11b Fast mode 6.5 300 16.11bFast mode6.5300 16.11c Fast mode+ 6.5 120 16.11cFast mode+6.5120 16.11d High-speed mode, Cb = 100 pF 10 80 16.11dHigh-speed mode, Cb = 100 pFb1080 16.11e High-speed mode, Cb = 400 pF 13 160 16.11eHigh-speed mode, Cb = 400 pFb13160 16.12a trCL Rise time of SCL signal Standard mode 1000 ns 16.12atrCL rCLRise time of SCL signalStandard mode1000ns 16.12b Fast mode 20 300 16.12bFast mode20300 16.12c Fast mode+ 120 16.12cFast mode+120 16.12d High-speed mode, Cb = 100 pF 10 40 16.12dHigh-speed mode, Cb = 100 pFb1040 16.12e High-speed mode, Cb = 400 pF 20 80 16.12eHigh-speed mode, Cb = 400 pFb2080 16.13a trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit High-speed mode, Cb = 100 pF 10 80 ns 16.13atrCL1 rCL1Rise time of SCL signal after a repeated start condition and after an acknowledge bitHigh-speed mode, Cb = 100 pFb1080ns 16.13b High-speed mode, Cb = 400 pF 20 160 16.13bHigh-speed mode, Cb = 400 pFb20160 16.14a tfCL Fall time of SCL signal Standard mode 300 ns 16.14atfCL fCLFall time of SCL signalStandard mode300ns 16.14b Fast mode 6.5 300 16.14bFast mode6.5300 16.14c Fast mode+ 6.5 120 16.14cFast mode+6.5120 16.14d High-speed mode, Cb = 100 pF 10 40 16.14dHigh-speed mode, Cb = 100 pFb1040 16.14e High-speed mode, Cb = 400 pF 20 80 16.14eHigh-speed mode, Cb = 400 pFb2080 16.15a tSP Pulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed) Standard mode, fast mode, and fast mode+ 50 ns 16.15atSP SPPulse width of spike suppressed (SCL and SDA spikes that are less than the indicated width are suppressed)Standard mode, fast mode, and fast mode+50ns 16.15b High-speed mode 10 16.15bHigh-speed mode10 Serial Peripheral Interface (SPI) These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted). POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns Serial Peripheral Interface (SPI) These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted). POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted). POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted). POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT POSPARAMETERSTEST CONDITIONSMINNOMMAXUNIT Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF Timing Requirements 17.1 1 Cycle time 200 ns 17.2 2 Enable lead time 150 ns 17.3 3 Enable lag time 150 ns 17.4 4 Clock low time 60 ns 17.5 5 Clock high time 60 ns 17.6 6 Data setup time 15 ns 17.7 7 Data hold time 15 ns 17.8 8 Output data valid after SCLK falling 4 ns 17.9 9 New output data valid after SCLK falling 60 ns 17.10 10 Disable time 30 ns 17.11 11 CS inactive time 100 ns Electrical Characteristics Electrical Characteristics 15.1 Capacitive load on pin SDO 30 pF 15.1Capacitive load on pin SDO30pF Timing Requirements Timing Requirements 17.1 1 Cycle time 200 ns 17.11Cycle time200ns 17.2 2 Enable lead time 150 ns 17.22Enable lead time150ns 17.3 3 Enable lag time 150 ns 17.33Enable lag time150ns 17.4 4 Clock low time 60 ns 17.44Clock low time60ns 17.5 5 Clock high time 60 ns 17.55Clock high time60ns 17.6 6 Data setup time 15 ns 17.66Data setup time15ns 17.7 7 Data hold time 15 ns 17.77Data hold time15ns 17.8 8 Output data valid after SCLK falling 4 ns 17.88Output data valid after SCLK falling4ns 17.9 9 New output data valid after SCLK falling 60 ns 17.99New output data valid after SCLK falling60ns 17.10 10 Disable time 30 ns 17.1010Disable time30ns 17.11 11 CS inactive time 100 ns 17.1111CS inactive time100ns Typical Characteristics Quiescent Current vs Input Voltage TA = 25°C Standby Current with VCCA Monitor TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C Typical Characteristics Quiescent Current vs Input Voltage TA = 25°C Standby Current with VCCA Monitor TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C Quiescent Current vs Input Voltage TA = 25°C Standby Current with VCCA Monitor TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C Quiescent Current vs Input Voltage TA = 25°C Standby Current with VCCA Monitor TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C Quiescent Current vs Input Voltage TA = 25°C Quiescent Current vs Input Voltage TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C Standby Current with VCCA Monitor TA = 25°C Standby Current with VCCA Monitor TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C Buck Phase Adding and Shedding VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1.0 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C Buck Ramp-up Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V TA = 25°C VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 0.6 V to 1.4 VTA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C Buck Ramp-down Slew Rate VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V TA = 25°C VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1.4 V to 0.6 VTA = 25°C Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1 VSlew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Start-up with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1 VSlew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with no Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1 VSlew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms Buck Shutdown with 1A Load, Auto Mode VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1 VSlew Rate = 5 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms Buck Ramp-up with and without Load VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 0.6 V to 1.4 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 0.6 V to 1.4 VSlew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms Buck Ramp-down with and without Load VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1.4 V to 0.6 V Slew Rate = 33.3 V/ms VPVIN_Bn = 3.3 V PVIN_BnBuck VSET = 1.4 V to 0.6 VSlew Rate = 33.3 V/ms GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C GPLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C GPLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)LDOn_PLDN = 500 ΩTA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 0 VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C LNLDO Start-up with LDOn_SLOW_RAMP = 1 VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C LNLDO Shutdown VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C VIN(LDOn) = 3.3 V or 5 VIN(LDOn)LDOn_PLDN = 500 ΩTA = 25°C Detailed Description Overview The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails. The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device. I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers. The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits. The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary TPS6593-Q1 PMIC. Functional Block Diagram Feature Description System Supply Voltage Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function. LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor Power Resources (Bucks and LDOs) The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA. The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device. Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise Buck Regulators BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. (1) Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. Sync Clock and DPLL Module Low Dropout Regulators (LDOs) All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Output Voltage Monitor and PGOOD Generation A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. Thermal Monitoring The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. Thermal Warning Function The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). Thermal Shutdown The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. Backup Supply Power-Path The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA. When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state. Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. General-Purpose I/Os (GPIO Pins) The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters. When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function. All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and . Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port. The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. nINT, EN_DRV, and nRSTOUT Pins The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions. The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under . The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails. The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'. Interrupts The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host. Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. RTC General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC Interrupts The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling Watchdog (WDOG) A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. Watchdog Fail Counter and Status The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. Watchdog Start-Up and Configuration When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] MCU to Watchdog Synchronization In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. Watchdog Disable Function The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. Watchdog Sequence Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Watchdog Trigger Mode When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. WatchDog Flow Chart and Timing Diagrams in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog Question-Answer Mode A 20220110 Added Section:Watchdog Question-Answer Modeyes When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Error Signal Monitor (ESM) A 20220110 Added Section: Error Signal Monitor (ESM)yes The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. ESM Error-Handling Procedure Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Device Functional Modes Device State Machine The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. Fixed Device Power FSM The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Pre-Configurable Mission States When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram Error Handling Operations The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Device Start-up Timing shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. Power Sequences A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. First Supply Detection The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . Register Power Domains and Reset Levels The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT Multi-PMIC Synchronization A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation SPMI Interface System Setup An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. Transmission Protocol and CRC The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. SPMI Target Device Communication to SPMI Controller Device An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. SPMI-BIST Overview The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) Control Interfaces A 20220110 For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . CRC Calculation for I²C and SPI Interface Protocols A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1. For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1. and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) I²C-Compatible Interface The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram Start and Stop Conditions The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK Serial Peripheral Interface (SPI) The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. Configurable Registers Register Page Partitioning A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses. When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 CRC Protection for Configuration, Control, and Test Registers The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. . The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1. The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. CRC Protection for User Registers A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM. After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion. The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance. If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h. Register Write Protection For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections. Watchdog and ESM Configuration Registers The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) User Registers User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. Register Maps A 20220314 Corrected description of register DEV_REVyes A 20220314 Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes TPS6593-Q1 Registers lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in . Return to the Summary Table. DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in . Return to the Summary Table. NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in . Return to the Summary Table. NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in . Return to the Summary Table. BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in . Return to the Summary Table. BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in . Return to the Summary Table. BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in . Return to the Summary Table. BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in . Return to the Summary Table. BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in . Return to the Summary Table. BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in . Return to the Summary Table. BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in . Return to the Summary Table. BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in . Return to the Summary Table. BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in . Return to the Summary Table. BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in . Return to the Summary Table. LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in . Return to the Summary Table. LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in . Return to the Summary Table. LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in . Return to the Summary Table. LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in . Return to the Summary Table. LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in . Return to the Summary Table. LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in . Return to the Summary Table. LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in . Return to the Summary Table. LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in . Return to the Summary Table. LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in . Return to the Summary Table. VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in . Return to the Summary Table. VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in . Return to the Summary Table. GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in . Return to the Summary Table. GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in . Return to the Summary Table. GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in . Return to the Summary Table. GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in . Return to the Summary Table. GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in . Return to the Summary Table. GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in . Return to the Summary Table. GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in . Return to the Summary Table. GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in . Return to the Summary Table. GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in . Return to the Summary Table. GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in . Return to the Summary Table. GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in . Return to the Summary Table. NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in . Return to the Summary Table. GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in . Return to the Summary Table. GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in . Return to the Summary Table. GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in . Return to the Summary Table. GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in . Return to the Summary Table. RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in . Return to the Summary Table. RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in . Return to the Summary Table. RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in . Return to the Summary Table. MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in . Return to the Summary Table. MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in . Return to the Summary Table. MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in . Return to the Summary Table. MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in . Return to the Summary Table. MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in . Return to the Summary Table. MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in . Return to the Summary Table. MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in . Return to the Summary Table. MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in . Return to the Summary Table. MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in . Return to the Summary Table. MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in . Return to the Summary Table. MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in . Return to the Summary Table. MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in . Return to the Summary Table. MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in . Return to the Summary Table. MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in . Return to the Summary Table. INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in . Return to the Summary Table. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in . Return to the Summary Table. INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in . Return to the Summary Table. INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in . Return to the Summary Table. INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in . Return to the Summary Table. INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in . Return to the Summary Table. INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in . Return to the Summary Table. INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in . Return to the Summary Table. INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in . Return to the Summary Table. INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in . Return to the Summary Table. INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in . Return to the Summary Table. INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in . Return to the Summary Table. INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in . Return to the Summary Table. INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in . Return to the Summary Table. INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in . Return to the Summary Table. INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in . Return to the Summary Table. INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in . Return to the Summary Table. INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in . Return to the Summary Table. INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in . Return to the Summary Table. STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in . Return to the Summary Table. STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in . Return to the Summary Table. STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in . Return to the Summary Table. STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in . Return to the Summary Table. STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in . Return to the Summary Table. STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in . Return to the Summary Table. STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in . Return to the Summary Table. STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in . Return to the Summary Table. STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in . Return to the Summary Table. STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in . Return to the Summary Table. STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in . Return to the Summary Table. PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in . Return to the Summary Table. PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in . Return to the Summary Table. PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in . Return to the Summary Table. PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in . Return to the Summary Table. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in . Return to the Summary Table. CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in . Return to the Summary Table. CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in . Return to the Summary Table. ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in . Return to the Summary Table. MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in . Return to the Summary Table. ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in . Return to the Summary Table. BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in . Return to the Summary Table. SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in . Return to the Summary Table. FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in . Return to the Summary Table. FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in . Return to the Summary Table. USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in . Return to the Summary Table. ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in . Return to the Summary Table. ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in . Return to the Summary Table. REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in . Return to the Summary Table. MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in . Return to the Summary Table. CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in . Return to the Summary Table. SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in . Return to the Summary Table. RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in . Return to the Summary Table. RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in . Return to the Summary Table. RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in . Return to the Summary Table. RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in . Return to the Summary Table. RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in . Return to the Summary Table. RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in . Return to the Summary Table. RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in . Return to the Summary Table. ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in . Return to the Summary Table. ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in . Return to the Summary Table. ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in . Return to the Summary Table. ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in . Return to the Summary Table. ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in . Return to the Summary Table. ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in . Return to the Summary Table. RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in . Return to the Summary Table. RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in . Return to the Summary Table. RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in . Return to the Summary Table. RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in . Return to the Summary Table. RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in . Return to the Summary Table. RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in . Return to the Summary Table. RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in . Return to the Summary Table. WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in . Return to the Summary Table. WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in . Return to the Summary Table. WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in . Return to the Summary Table. WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in . Return to the Summary Table. WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in . Return to the Summary Table. WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in . Return to the Summary Table. WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in . Return to the Summary Table. WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in . Return to the Summary Table. WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in . Return to the Summary Table. WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. Detailed Description Overview The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails. The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device. I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers. The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits. The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary TPS6593-Q1 PMIC. Overview The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails. The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device. I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers. The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits. The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary TPS6593-Q1 PMIC. The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails. The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device. I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers. The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits. The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary TPS6593-Q1 PMIC. The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails.TPS6593-Q1TPS6593-Q1TPS6593-Q1 fivefourhas4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode., BUCK2, BUCK3,BUCK4 3.514four BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. five2The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device.TPS6593-Q1500 mA2TPS6593-Q1I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers. 2, the RTC registers2The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss. TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits.TPS6593-Q1 The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1TPS6593-Q1The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU.TPS6593-Q1An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary TPS6593-Q1 PMIC.TPS6593-Q1TPS6593-Q1 Functional Block Diagram Functional Block Diagram Feature Description System Supply Voltage Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function. LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor Power Resources (Bucks and LDOs) The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA. The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device. Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise Buck Regulators BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. Sync Clock and DPLL Module Low Dropout Regulators (LDOs) All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Output Voltage Monitor and PGOOD Generation A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. Thermal Monitoring The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. Thermal Warning Function The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). Thermal Shutdown The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. Backup Supply Power-Path The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA. When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state. Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. General-Purpose I/Os (GPIO Pins) The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters. When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function. All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and . Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port. The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. nINT, EN_DRV, and nRSTOUT Pins The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions. The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under . The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails. The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'. Interrupts The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host. Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. RTC General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC Interrupts The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling Watchdog (WDOG) A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. Watchdog Fail Counter and Status The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. Watchdog Start-Up and Configuration When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] MCU to Watchdog Synchronization In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. Watchdog Disable Function The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. Watchdog Sequence Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Watchdog Trigger Mode When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. WatchDog Flow Chart and Timing Diagrams in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog Question-Answer Mode A 20220110 Added Section:Watchdog Question-Answer Modeyes When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Error Signal Monitor (ESM) A 20220110 Added Section: Error Signal Monitor (ESM)yes The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. ESM Error-Handling Procedure Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Feature Description System Supply Voltage Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function. LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor System Supply Voltage Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function. LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function. LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state machine of the device. VCCA voltage detection outputs determine the power states of the device as follows: VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. TPS6593-Q1 VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UVLOThe TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY state. TPS6593-Q1returns to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management (BSM) module during the BACKUP state. The device The device cannot return to the BACKUP state from the NO SUPPLY state. VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up. VCCA_UVThe TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the VCCA pin rises above VCCA_UV during initial power-up.TPS6593-Q1 VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence. VCCA_OVPIf the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown sequence.TPS6593-Q1 clears the ENABLE_DRV bit andA separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to for additional detail on the operation of the PGOOD monitor function.LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly. shows a block diagram of the VCCA input voltage monitoring. VCCA Monitor VCCA Monitor Power Resources (Bucks and LDOs) The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA. The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device. Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise Buck Regulators BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. Sync Clock and DPLL Module Low Dropout Regulators (LDOs) All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Power Resources (Bucks and LDOs) The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA. The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device. Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA. The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device. Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks and linear LDOs. These supply resources provide power to the external processors, components, and modules inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which is at a lower voltage level than the VCCA.TPS6593-Q1TPS6593-Q1The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. #GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742 lists the power resources provided by the TPS6593-Q1 device.#GUID-4B7B2915-7E2F-4669-92C2-3E88664B9019/SLVSE825742TPS6593-Q1 Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise Power Resources RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS RESOURCETYPEVOLTAGECURRENT CAPABILITYCOMMENTS BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise BUCK1, BUCK2, BUCK3 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps 3.5 A Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK1, BUCK2, BUCK3 , BUCK2, BUCK3BUCK0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V, 20-mV steps3.5 ACan be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK 0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode Can be configured in multi-phase mode or stand-alone in single-phase mode BUCK4 BUCK4BUCK0.3 V to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10 mV steps 1.66 V to 3.34 V, 20-mV steps 4 A in single-phase mode 3.5 A in multi-phase mode4 A in single-phase mode 3.5 ACan be configured in multi-phase mode or stand-alone in single-phase mode BUCK5 BUCK 0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps 2 A Only in single-phase mode BUCK5 BUCK5BUCK0.3 to 0.6 V, 20-mV steps 0.6 V to 1.1 V, 5-mV steps 1.1 V to 1.66 V, 10-mV steps 1.66 V to 3.34 V , 20-mV steps2 AOnly in single-phase mode LDO1, LDO2, LDO3 LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable LDO1, LDO2, LDO3LDO0.6 V to 3.3 V, 50-mV steps 500 mA 500 mABypass mode configurable LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise LDO4LDO1.2 V to 3.3 V, 25-mV steps300 mALow-noise Buck Regulators BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. Sync Clock and DPLL Module Buck Regulators BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ BUCK Regulator Overview A 20220110 BUCK Regulator Overview: added Current Limityes A 20220110 BUCK Regulator Overview: added Current Limityes A 20220110 BUCK Regulator Overview: added Current Limityes A20220110BUCK Regulator Overview: added Current Limityes yes The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features: Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator When the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding There are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels. When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase configuration. All of the buck converters support the following features:TPS6593-Q1five, of which four can be combined in multi-phase configurationfour Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation External clock synchronization option to minimize crosstalk Optional spread spectrum technique to reduce EMI Soft start AVS support with configurable slew-rate Windowed undervoltage and overvoltage monitors with configurable threshold Windowed voltage monitor for external supply when the buck converter is inactive Output Current Limit Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operationExternal clock synchronization option to minimize crosstalkOptional spread spectrum technique to reduce EMISoft startAVS support with configurable slew-rateWindowed undervoltage and overvoltage monitors with configurable thresholdWindowed voltage monitor for external supply when the buck converter is inactiveOutput Current LimitShort-to-Ground Detection on SW_Bx pins at start-up of the buck regulatorWhen the outputs of these buck converters are combined in multi-phase configuration, it also supports the following features: Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding Current balancing between the phases of the converter Differential voltage sensing from point of the load Phase shifted outputs for EMI reduction Optional dynamic phase shedding or adding Current balancing between the phases of the converterDifferential voltage sensing from point of the loadPhase shifted outputs for EMI reductionOptional dynamic phase shedding or addingThere are two modes of operation for the buck converter, depending on the required output current: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM = 1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output current levels.When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on the load current level. The forced multi-phase mode can be enabled for lower ripple at the output. shows a block diagram of a single core. shows the interleaving switching action of the multi-phase converters. BUCK Core Block Diagram BUCK Core Block Diagram Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase Configuration. ⁽¹⁾ Graph is not in scale and is for illustrative purposes only. Graph is not in scale and is for illustrative purposes only. Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Multi-Phase Operation and Phase-Adding or Shedding The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in . The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions. The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of increasing load current automatically increases the number of active phases is called phase adding. The process in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number of active phases is called phase shedding. The concept is shown in .4, BUCK2, BUCK3,BUCK490°4four. In the same way, 3-phase converter has an effective ripple frequency three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching frequency of any one phase; the parallel operationTPS6593-Q1The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register. If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to follow the required output current. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) ⁽¹⁾ Graph is not in scale and is for illustrative purposes only. Graph is not in scale and is for illustrative purposes only. Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. Transition Between PWM and PFM Modes The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes. The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current range by combining the PFM and the PWM modes.TPS6593-Q1 Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Multi-Phase BUCK Regulator Configurations The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration. Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. The control of the multi-phase regulator settings is done using the control registers of the primary BUCK regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the secondary and, if used, the tertiary and quaternary BUCK regulators : BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT TPS6593-Q1 BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF register BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT BUCKn_CTRL register, except BUCKn_VMON_EN BUCKn_CONF registerBUCKn_VOUT_1 and BUCKn_VOUT_2 registersBUCKn_PG_WINDOW registerInterrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT #GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK regulator in each configuration.#GUID-E61220E0-AB07-48B8-BBB5-1EEC54C6C2D1/SLVSE828295 Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 Primary BUCK Assignment for Supported Multi-phase Configuration Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment Supported Multi-Phase BUCK Regulator ConfigurationPrimary BUCK Assignment 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1 4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1 3-Phase: BUCK1 + BUCK2 + BUCK3BUCK1 2-Phase: BUCK1 + BUCK2 BUCK1 2-Phase: BUCK1 + BUCK2BUCK1 2-Phase: BUCK3 + BUCK4 BUCK3 2-Phase: BUCK3 + BUCK4BUCK3When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4 regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set the target voltage for the external voltage monitoring function under such configuration: BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register TPS6593-Q1 BUCKn_VMON_EN bit BUCKn_VSEL bit BUCKn_SLEW_RATE BUCKn_VOUT_1 and BUCKn_VOUT_2 registers BUCKn_PG_WINDOW register BUCKn_VMON_EN bitBUCKn_VSEL bitBUCKn_SLEW_RATEBUCKn_VOUT_1 and BUCKn_VOUT_2 registersBUCKn_PG_WINDOW registerCustomers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits must be set to '0'. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Spread-Spectrum Mode The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL. The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported. The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance. The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth When internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL.TPS6593-Q1The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during operation is not supported.The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock to the DPLL is ±18% to secure parametric compliance of the BUCK output performance.The internal modulation is inactive by default and can be enabled and configured after power up. Internal modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0) when changing the following parameter: SS_DEPTH[1:0] – Spread Spectrum modulation depth SS_DEPTH[1:0] – Spread Spectrum modulation depthWhen internal modulation is enabled and configured, it can be made inactive by the system MCU during operation. The device transition to different mission states does not impact internal modulation when it is enabled and configured. Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC. All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by . When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by . tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp. tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs Because output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC.All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur: Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state TPS6593-Q1 Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state Error that causes the device to execute warm reset MCU configures the device to enter the LP STANDBY state Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY stateError that causes the device to execute warm resetMCU configures the device to enter the LP STANDBY state shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers. AVS/DVS Configuration Register Arbitration Diagram AVS/DVS Configuration Register Arbitration DiagramThe digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by .When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by .tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx PG_OV_UV_DELAYsettle_BxIn order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by . The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp.PG_OV_GATEand tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µsPG_UV_GATEBecause output capacitance, forward and negative current limits and load current of the BUCK regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE may not be sufficient long for the slower slew rate setting when the target BUCK regulator output voltage is higher. Please refer to the PMIC user's guide for detail information about the supported voltage level and slew rate setting combinations of a particular orderable part number. PG_UV_GATE and are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes. AVS Voltage and OV UV Threshold Level Change Timing Diagram AVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram DVS Voltage and OV UV Threshold Level Change Timing Diagram BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCK Output Voltage Setting #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage. Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 #GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 shows the coding used to select the BUCK regulator output voltage.#GUID-965FCD6F-7229-471D-B68C-B904FBDCB342/X927 Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 Output Voltage Selection for BUCK Regulators BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 5 mV steps BUCKn_VSETn Output Voltage [V] 10 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETn Output Voltage [V] 20 mV steps BUCKn_VSETnOutput Voltage [V] 20 mV stepsBUCKn_VSETnOutput Voltage [V] 5 mV stepsBUCKn_VSETnOutput Voltage [V] 5 mV stepsBUCKn_VSETnOutput Voltage [V] 10 mV stepsBUCKn_VSETnOutput Voltage [V] 20 mV stepsBUCKn_VSETnOutput Voltage [V] 20 mV steps 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x40 0.845 0x72 1.095 0xA4 1.59 0xA5 1.6 0xA6 1.61 0xA7 1.62 0xA8 1.63 0xA9 1.64 0xAA 1.65 0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52 0x000.30x0F0.60x410.850x731.10xAB1.660xD62.52 0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54 0x010.320x100.6050x420.8550x741.110xAC1.680xD72.54 0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56 0x020.340x110.610x430.860x751.120xAD1.70xD82.56 0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58 0x030.360x120.6150x440.8650x761.130xAE1.720xD92.58 0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6 0x040.380x130.620x450.870x771.140xAF1.740xDA2.6 0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62 0x050.40x140.6250x460.8750x781.150xB01.760xDB2.62 0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64 0x060.420x150.630x470.880x791.160xB11.780xDC2.64 0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66 0x070.440x160.6350x480.8850x7A1.170xB21.80xDD2.66 0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68 0x080.460x170.640x490.890x7B1.180xB31.820xDE2.68 0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7 0x090.480x180.6450x4A0.8950x7C1.190xB41.840xDF2.7 0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72 0x0A0.50x190.650x4B0.90x7D1.20xB51.860xE02.72 0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74 0x0B0.520x1A0.6550x4C0.9050x7E1.210xB61.880xE12.74 0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76 0x0C0.540x1B0.660x4D0.910x7F1.220xB71.90xE22.76 0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78 0x0D0.560x1C0.6650x4E0.9150x801.230xB81.920xE32.78 0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8 0x0E0.580x1D0.670x4F0.920x811.240xB91.940xE42.8 0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82 0x1E0.6750x500.9250x821.250xBA1.960xE52.82 0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84 0x1F0.680x510.930x831.260xBB1.980xE62.84 0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86 0x200.6850x520.9350x841.270xBC20xE72.86 0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88 0x210.690x530.940x851.280xBD2.020xE82.88 0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9 0x220.6950x540.9450x861.290xBE2.040xE92.9 0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92 0x230.70x550.950x871.30xBF2.060xEA2.92 0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94 0x240.7050x560.9550x881.310xC02.080xEB2.94 0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96 0x250.710x570.960x891.320xC12.10xEC2.96 0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98 0x260.7150x580.9650x8A1.330xC22.120xED2.98 0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0 0x270.720x590.970x8B1.340xC32.140xEE3.0 0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02 0x280.7250x5A0.9750x8C1.350xC42.160xEF3.02 0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04 0x290.730x5B0.980x8D1.360xC52.180xF03.04 0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06 0x2A0.7350x5C0.9850x8E1.370xC62.20xF13.06 0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08 0x2B0.740x5D0.990x8F1.380xC72.220xF23.08 0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1 0x2C0.7450x5E0.9950x901.390xC82.240xF33.1 0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12 0x2D0.750x5F1.00x911.40xC92.260xF43.12 0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14 0x2E0.7550x601.0050x921.410xCA2.280xF53.14 0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16 0x2F0.760x611.010x931.420xCB2.30xF63.16 0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18 0x300.7650x621.0150x941.430xCC2.320xF73.18 0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2 0x310.770x631.020x951.440xCD2.340xF83.2 0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22 0x320.7750x641.0250x961.450xCE2.360xF93.22 0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24 0x330.780x651.030x971.460xCF2.380xFA3.24 0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26 0x340.7850x661.0350x981.470xD02.40xFB3.26 0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28 0x350.790x671.040x991.480xD12.420xFC3.28 0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3 0x360.7950x681.0450x9A1.490xD22.440xFD3.3 0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32 0x370.80x691.050x9B1.50xD32.460xFE3.32 0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34 0x380.8050x6A1.0550x9C1.510xD42.480xFF3.34 0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5 0x390.810x6B1.060x9D1.520xD52.5 0x3A 0.815 0x6C 1.065 0x9E 1.53 0x3A0.8150x6C1.0650x9E1.53 0x3B 0.82 0x6D 1.07 0x9F 1.54 0x3B0.820x6D1.070x9F1.54 0x3C 0.825 0x6E 1.075 0xA0 1.55 0x3C0.8250x6E1.0750xA01.55 0x3D 0.83 0x6F 1.08 0xA1 1.56 0x3D0.830x6F1.080xA11.56 0x3E 0.835 0x70 1.085 0xA2 1.57 0x3E0.8350x701.0850xA21.57 0x3F 0.84 0x71 1.09 0xA3 1.58 0x3F0.840x711.090xA31.58 0x40 0.845 0x72 1.095 0xA4 1.59 0x400.8450x721.0950xA41.59 0xA5 1.6 0xA51.6 0xA6 1.61 0xA61.61 0xA7 1.62 0xA71.62 0xA8 1.63 0xA81.63 0xA9 1.64 0xA91.64 0xAA 1.65 0xAA1.65 BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. BUCK Regulator Current Limit A 20220110 Added section: BUCK Regulator Current Limit yes A 20220110 Added section: BUCK Regulator Current Limit yes A 20220110 Added section: BUCK Regulator Current Limit yes A20220110Added section: BUCK Regulator Current Limit yes yes Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0]. The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4 adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0].BUCK1..4BUCK5BUCK5_ILIM[3:0]The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A. SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . SW_Bx Short-to-Ground Detection Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the SAFE RECOVERY state, after which it performs an attempt to restart as described in . 55TPS6593-Q15TPS6593-Q1 Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. Sync Clock Functionality The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection. The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10. The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in . The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection.TPS6593-Q1The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range.The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10.TPS6593-Q1 Sync Clock and DPLL Module Sync Clock and DPLL Module Sync Clock and DPLL Module Sync Clock and DPLL Module Sync Clock and DPLL Module Low Dropout Regulators (LDOs) All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Low Dropout Regulators (LDOs) All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt. The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms. If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such conditions, the output voltage droops to near the PVIN_LDOn level. TPS6593-Q1Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or LDOn_UV_INT interrupt.RESERVEDThe LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1', however, the ramp up speed of the regulator output voltage is < 3 V/ms.If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in ), and adjust the resistor values to compensate for the voltage shift. Impedance at the VOUT_LDOn Pins Impedance at the VOUT_LDOn Pins LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVINT The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state. The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1 device, which are not required to be always-on and can be turned-off when the device is in low power states. The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY state.TPS6593-Q1The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other components or external loads to this VOUT_LDOVINT pin. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. LDOVRTC The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states. The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use only, and cannot be used to support external loads. An output filtering capacitor must be connected at the VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin. This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level. or backup , the digital components, the crystal, and the RTC calendar moduleTPS6593-Q1The LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is above the LDOVRTC_UVLO level.Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up functions only. The RTC calendar and interrupt functions are fully activated in the mission states.The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source when the 32 KHz crystal and RTC counter functions are no longer needed. shelf mode shelf mode shelf mode shelf mode LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved LDO1, LDO2, and LDO3 A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes A 20220110 Added LDO1, LDO2, LDO3 Current Limit descriptionyes A20220110Added LDO1, LDO2, LDO3 Current Limit descriptionyes yes The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin. The bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply. The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA. It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3. Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as load switches with power sequencing control. Similar to the buck regulators mentioned in , the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by connecting the external rail to the VOUT_LDOn pin.500 mAThe bypass capability to connect the input voltage to the output in bypass mode is supported when the input voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O supply.The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA.It is important to wait until the LDO has settled on the target voltage from the previous change when changing the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 + the number of 50-mV steps to the new target voltage). #GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3.#GUID-EC409DDC-2E1D-4E58-8C0F-5BA31078220E/X2414 Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved Output Voltage Selection for LDO1, LDO2, and LDO3 LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSET Output Voltage [V] LDOx_VSETOutput Voltage [V]LDOx_VSETOutput Voltage [V]LDOx_VSETOutput Voltage [V]LDOx_VSETOutput Voltage [V] 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved 0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80 0x00Reserved0x101.200x202.000x302.80 0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85 0x01Reserved0x111.250x212.050x312.85 0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90 0x02Reserved0x121.300x222.100x322.90 0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95 0x03Reserved0x131.350x232.150x332.95 0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00 0x040.600x141.400x242.200x343.00 0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05 0x050.650x151.450x252.250x353.05 0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10 0x060.700x161.500x262.300x363.10 0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15 0x070.750x171.550x272.350x373.15 0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20 0x080.800x181.600x282.400x383.20 0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25 0x090.850x191.650x292.450x393.25 0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30 0x0A0.900x1A1.700x2A2.500x3A3.30 0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved 0x0B0.950x1B1.750x2B2.550x3BReserved 0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved 0x0C1.000x1C1.800x2C2.600x3CReserved 0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved 0x0D1.050x1D1.850x2D2.650x3DReserved 0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved 0x0E1.100x1E1.900x2E2.700x3EReserved 0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved 0x0F1.150x1F1.950x2F2.750x3FReserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Low-Noise LDO (LDO4) A 20220110 Added LDO4 Current Limit descriptionyes A 20220110 Added LDO4 Current Limit descriptionyes A 20220110 Added LDO4 Current Limit descriptionyes A20220110Added LDO4 Current Limit descriptionyes yes The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin. The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4. Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail to the VOUT_LDO4 pin.The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This Current-Limit has a fixed value between 400 mA and 900 mA. #GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 shows the coding used to select the output voltage for LDO4.#GUID-7532B08A-787D-48A5-866A-CF9357CABD43/X1331 Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved Output Voltage Selection for LDO4 LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSET Output Voltage [V] LDO4_VSETOutput Voltage [V]LDO4_VSETOutput Voltage [V]LDO4_VSETOutput Voltage [V]LDO4_VSETOutput Voltage [V] 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved 0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800 0x00Reserved0x201.2000x402.0000x602.800 0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825 0x01Reserved0x211.2250x412.0250x612.825 0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850 0x02Reserved0x221.2500x422.0500x622.850 0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875 0x03Reserved0x231.2750x432.0750x632.875 0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900 0x04Reserved0x241.3000x442.1000x642.900 0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925 0x05Reserved0x251.3250x452.1250x652.925 0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950 0x06Reserved0x261.3500x462.1500x662.950 0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975 0x07Reserved0x271.3750x472.1750x672.975 0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000 0x08Reserved0x281.4000x482.2000x683.000 0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025 0x09Reserved0x291.4250x492.2250x693.025 0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050 0x0AReserved0x2A1.4500x4A2.2500x6A3.050 0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075 0x0BReserved0x2B1.4750x4B2.2750x6B3.075 0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100 0x0CReserved0x2C1.5000x4C2.3000x6C3.100 0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125 0x0DReserved0x2D1.5250x4D2.3250x6D3.125 0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150 0x0EReserved0x2E1.5500x4E2.3500x6E3.150 0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175 0x0FReserved0x2F1.5750x4F2.3750x6F3.175 0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200 0x10Reserved0x301.6000x502.4000x703.200 0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225 0x11Reserved0x311.6250x512.4250x713.225 0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250 0x12Reserved0x321.6500x522.4500x723.250 0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275 0x13Reserved0x331.6750x532.4750x733.275 0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300 0x14Reserved0x341.7000x542.5000x743.300 0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved 0x15Reserved0x351.7250x552.5250x75Reserved 0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved 0x16Reserved0x361.7500x562.5500x76Reserved 0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved 0x17Reserved0x371.7750x572.5750x77Reserved 0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved 0x18Reserved0x381.8000x582.6000x78Reserved 0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved 0x19Reserved0x391.8250x592.6250x79Reserved 0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved 0x1AReserved0x3A1.8500x5A2.6500x7AReserved 0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved 0x1BReserved0x3B1.8750x5B2.6750x7BReserved 0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved 0x1CReserved0x3C1.9000x5C2.7000x7CReserved 0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved 0x1DReserved0x3D1.9250x5D2.7250x7DReserved 0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved 0x1EReserved0x3E1.9500x5E2.7500x7EReserved 0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved 0x1FReserved0x3F1.9750x5F2.7750x7FReserved Output Voltage Monitor and PGOOD Generation A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. Output Voltage Monitor and PGOOD Generation A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes A 20220110 Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes A20220110Added explanation on how to use Voltage Monitors of unused BUCK and LDO regulatorsyes yes The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present. The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system. The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal. An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals. The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status. The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored. The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Waveforms The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. TPS6593-Q1and LDO,, and is set by the PGOOD_SEL_LDOn register bits for each LDO regulatorThe PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present.The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin. For LDO regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit (ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled. In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the corresponding LDO regulator must be set.or an LDOFor LDO regulators, if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the VOUT_LDOn pin.When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system.or LDOThe VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the PGOOD monitor output signal., that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST statedevice passes An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for external peripherals.The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the sources shows active status.The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored.The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits. shows the Power-Good generation block diagram, and shows the Power-Good waveforms. PGOOD Block Diagram PGOOD Block Diagram PGOOD Waveforms PGOOD WaveformsThe OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated automatically by the digital control block when the output voltage setting changes. When the output voltage of the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed. The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK and LDO output monitors to update with the correct timing, the following operating procedures must be followed when updating the _VSET values of the regulators to avoid detection of OV/UV fault: and the LDO regulators outputoutputand LDO, or LDOn_VSET, LDOn_UV_THR, and the LDOn_OV_THRand LDO BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON New voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completed BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMONand LDONew voltage level must not be set before the start-up has finished New voltage level must not be set before the previous voltage change (ramp plus settling time) has completedThe voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are used for monitoring external supply rails: For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. or LDO In three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3 (on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external supply voltages., or LDOn_VSET, LDOn_UV_THR, and the LDOn_OV_THRor LDO For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3V For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pinFor voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the monitored supply rail is 3.3Vand LDO regulatorsFor voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after the corresponding BUCKn_VMON_EN bit is set. See equation (2) in . If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors. and for voltage monitors of BUCK3 and/or BUCK4 regulators if used in a three-phase or four-phase configurationIf BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors.For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs. Thermal Monitoring The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. Thermal Warning Function The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). Thermal Shutdown The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. Thermal Monitoring The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC. The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die. Three thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately. Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register. The current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started. If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold. The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the PMIC.TPS6593-Q1The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-temperature condition at either module first generates a warning to the system, and if the temperature continues to rise, then a switch-off of the PMIC device can occur before damage to the die.TPS6593-Q1LDO andThree thermal protection levels are available. One of these protections is a thermal warning function described in , that sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in , that begins device shutdown orderly or immediately.Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is written to the TWARN_INT register.or LDO LP_STANDBY regulators areThe current consumption of the thermal monitoring can be decreased in the mission states when the low power dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal detection modules, only one thermal detection module is monitored. If the temperature rises in this module, monitoring in all thermal detection modules is started.If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger (respectively) in the state machine. While the sequencing and error handling is NVM memory dependent, TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the temperature falls below the thermal warning threshold.TPS6593-Q1 Thermal Warning Function The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). Thermal Warning Function The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold. The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level. When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). The thermal monitor provides a warning to the host processor through the interrupt system when the temperature reaches within a cautionary range. The threshold value must be set to less than the thermal shutdown threshold.The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal warning level.TPS6593-Q1When the power-management software triggers an interrupt, immediate action must be taken to reduce the amount of power drawn from the PMIC device (for example, noncritical applications must be closed). Thermal Shutdown The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. Thermal Shutdown The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold. The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1 device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot restart until the die temperature is below the thermal warning threshold.SD_orderlyTPS6593-Q1SD_immTPS6593-Q1 Backup Supply Power-Path The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA. When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state. Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. Backup Supply Power-Path The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA. When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state. Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA. When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state. Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply. When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC, and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path switches the input of LDOVRTC back to VCCA.When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below 1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the device into the NO SUPPLY state.Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the VBACKUP pin is grounded. General-Purpose I/Os (GPIO Pins) The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters. When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function. All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and . Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port. The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. General-Purpose I/Os (GPIO Pins) The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters. When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function. All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and . Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port. The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters. When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function. All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and . Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port. The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with alternative features as listed in TPS6593-Q1elevenFor GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters.When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register. GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input) GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull GPIOn_DIR: Configures the input or output direction of each GPIO pin GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input)GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pinGPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selectedGPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pullGPIOn_DIR: Configures the input or output direction of each GPIO pinEach GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions: nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 nRSTOUT_SOC PGOOD nERR_MCU nERR_SoC TRIG_WDOG DISABLE_WDOG NSLEEP1, NSLEEP2 WKUP1, WKUP2 LP_WKUP1, LP_WKUP2 nRSTOUT_SOCPGOODnERR_MCUnERR_SoCTRIG_WDOGDISABLE_WDOGNSLEEP1, NSLEEP2WKUP1, WKUP2LP_WKUP1, LP_WKUP2The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to for more detail on the predetermined IO characteristics for each pre-defined digital interface function.SCL_I2C2, CLK32KOUT, All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to and .Only GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up the device from LP_STANDBY state.Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port.The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. , thepin thepinand the GPIO pin assigned as pin, thepinand the GPIO pin assigned asgate_readbackAll GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the configuration for the pin is loaded from the NVM. For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of its output power domain. nINT, EN_DRV, and nRSTOUT Pins The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions. The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under . The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails. The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'. nINT, EN_DRV, and nRSTOUT Pins, EN_DRV, The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions. The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under . The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails. The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'. The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions. The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under . The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails. The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'. The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with dedicated functions.EN_DRV The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be found under .The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map. These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the voltage rails.TPS6593-Q1The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'.TPS6593-Q1TPS6593-Q1 Interrupts The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host. Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. Interrupts The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host. Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host. Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the following categories: BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . BUCK ERRORThese interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC) and over-current (ILIM) error conditions found on the BUCK regulators . LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. LDO ERRORThese interrupts indicate OV, UV, and SC error conditions found on the LDO regulators, as well as OV and UV error conditions found on the VCCA supply. VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply. VMON ERRORThese interrupts indicate OV and UV error conditions found on the VCCA supply. SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State. SEVERE ERRORThese errors indicate severe device error conditions, such as thermal shutdown, PFSM sequencing and execution error and VCCA over-voltage, that causes the device to trigger the PFSM to execute immediate shutdown of all digital outputs, external voltage rails and monitors, and proceed to the Safe Recovery State.VCCA over-voltage MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MODERATE ERRORThese interrupts provide warnings to the system to indicate multiple restart attempts from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-reset executions exceeding the allowed recovery count, detection of long press nPWRON button, SPMI communication error, register CRC error, BIST failure, read-back error on nRSTOUT or nINT pins, or junction temperature reaching orderly shutdown level. These warning causes the device to trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage rails and monitors, and proceed to the SAFE RECOVERY state.The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. detection of long press nPWRON button,BIST failure, The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite state machine (PFSM) settings always follow this described error handling to meet device specifications. MISCELLANEOUS WARNING These interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability. MISCELLANEOUS WARNINGThese interrupts provide information to the system to indicate detection of WDOG or ESM errors, die temperature crossing thermal warning threshold, device passing BIST test, or external sync clock availability.or ESM device passing BIST test, START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. START-UP SOURCEThese interrupts provide information to the system on the mechanism that caused the device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of the ENABLE pin or the nPRWON pin button detection. RTC alarm or timer interrupts,or the nPRWON pin button detection. GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins. GPIO DETECTIONThese interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-Level or Falling-Edge detection at the GPIO1 through GPIO11 pins.GPIO11 FSM ERROR INTERRUPT These interrupts indicate the detection of an error that causes the device mission state changes. FSM ERROR INTERRUPTThese interrupts indicate the detection of an error that causes the device mission state changes.All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source information until it is cleared by the host.Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according to the categories described above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new event occurs. Hierarchical Structure of Interrupt Registers Hierarchical Structure of Interrupt Registers Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit Summary of Interrupt Signals EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR EVENT TRIGGER FOR FSM RESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D RECOVERY INTERRUPT BIT MASK FOR INTERRUPT LIVE STATUS BIT INTERRUPT CLEAR EVENTTRIGGER FOR FSMRESULT #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DRECOVERYINTERRUPT BITMASK FOR INTERRUPTLIVE STATUS BITINTERRUPT CLEAR BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram BUCKn_ILIM_INT = 1 BUCKn_ILIM_MASK BUCKn_ILIM_STAT Write 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK regulator forward current limit triggered EN_ILIM_FSM_CTRL=1: According to BUCKn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/AEN_ILIM_FSM_CTRL=1:EN_ILIM_FSM_CTRL=0: EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt onlyEN_ILIM_FSM_CTRL=1:EN_ILIM_FSM_CTRL=0:Depends on PFSM configuration, see PFSM transition diagramBUCKn_ILIM_INT = 1BUCKn_ILIM_MASKBUCKn_ILIM_STATWrite 1 to BUCKn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/A EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt only Depends on PFSM configuration, see PFSM transition diagram LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT Write 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active LDO regulator current limit triggered EN_ILIM_FSM_CTRL=1: According to LDOn_GRP_SEL and x_RAIL_TRIG bits EN_ILIM_FSM_CTRL=0: N/AEN_ILIM_FSM_CTRL=1:EN_ILIM_FSM_CTRL=0: EN_ILIM_FSM_CTRL=1: Transition according to FSM trigger and interrupt EN_ILIM_FSM_CTRL=0: Interrupt onlyEN_ILIM_FSM_CTRL=1:EN_ILIM_FSM_CTRL=0:Depends on PFSM configuration, see PFSM transition diagramLDOn_ILIM_INT = 1LDOn_ILIM_MASKLDOn_ILIM_STATWrite 1 to LDOn_ILIM_INT bit Interrupt is not cleared if current limit violation is active BUCK output or switch short circuit detected According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_SC_INT = 1 N/A N/A Write 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK output or switch short circuit detectedAccording to BUCKn_GRP_SEL and x_RAIL_TRIG bitsRegulator disable and transition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramBUCKn_SC_INT = 1N/AN/AWrite 1 to BUCKn_SC_INT bit Interrupt is not cleared if the BUCKn is enabled and the BUCKn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detected According to LDOn_GRP_SEL and x_RAIL_TRIG bits Regulator disable and transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_SC_INT = 1 N/A N/A Write 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval LDO output short circuit detectedAccording to LDOn_GRP_SEL and x_RAIL_TRIG bitsRegulator disable and transition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramLDOn_SC_INT = 1N/AN/AWrite 1 to LDOn_SC_INT bit Interrupt is not cleared if the LDOn is enabled and the LDOn output voltage is below the short-circuit threshold after elapse of expected ramp-up time interval BUCK regulator overvoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT Write 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator overvoltageAccording to BUCKn_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramBUCKn_OV_INT = 1BUCKn_OV_MASKBUCKn_OV_STATWrite 1 to BUCKn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltage According to BUCKn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT Write 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present BUCK regulator undervoltageAccording to BUCKn_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramBUCKn_UV_INT = 1BUCKn_UV_MASKBUCKn_UV_STATWrite 1 to BUCKn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT Write 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator overvoltageAccording to LDOn_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramLDOn_OV_INT = 1LDOn_OV_MASKLDOn_OV_STATWrite 1 to LDOn_OV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltage According to LDOn_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT Write 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present LDO regulator undervoltageAccording to LDOn_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramLDOn_UV_INT = 1LDOn_UV_MASKLDOn_UV_STATWrite 1 to LDOn_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT Write 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input overvoltage monitoringAccording to VCCA_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramVCCA_OV_INT = 1VCCA_OV_MASKVCCA_OV_STATWrite 1 to VCCA_OV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoring According to VCCA_GRP_SEL and x_RAIL_TRIG bits Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT Write 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present VCCA input undervoltage monitoringAccording to VCCA_GRP_SEL and x_RAIL_TRIG bitsTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramVCCA_UV_INT = 1VCCA_UV_MASKVCCA_UV_STATWrite 1 to VCCA_UV_INT bit Interrupt is not cleared if the associated fault condition is still present Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT Write 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal warningN/AInterrupt onlyNot validTWARN_INT = 1TWARN_MASKTWARN_STATWrite 1 to TWARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown, orderly sequenced ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_ORD_INT = 1 N/A TSD_ORD_STAT Write 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, orderly sequencedORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN levelTSD_ORD_INT = 1N/ATSD_ORD_STATWrite 1 to TSD_ORD_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediate IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN level TSD_IMM_INT = 1 N/A TSD_IMM_STAT Write 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. Thermal shutdown, immediateIMMEDIATE_SHUTDOWN (SEVERE_ERR_INT)All regulators deavtivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] state after temperature is below TWARN levelTSD_IMM_INT = 1N/ATSD_IMM_STATWrite 1 to TSD_IMM_INT bit This interrupt bit can only be read by the MCU after the device has recovered from a previously occurred over-temperature event. BIST error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A Write 1 to BIST_FAIL_INT bit BIST errorORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateBIST_FAIL_INT = 1BIST_FAIL_MASKN/AWrite 1 to BIST_FAIL_INT bit Register CRC error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state REG_CRC_ERR_INT = 1 REG_CRC_ERR_MASK N/A Write 1 to REG_CRC_ERR_INT bit Register CRC errorORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateREG_CRC_ERR_INT = 1REG_CRC_ERR_MASKN/AWrite 1 to REG_CRC_ERR_INT bit SPMI communication error ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A Write 1 to SPMI_ERR_INT bit SPMI communication errorORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateSPMI_ERR_INT = 1SPMI_ERR_MASKN/AWrite 1 to SPMI_ERR_INT bit SPI frame error N/A Interrupt only Not valid COMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 COMM_FRM_ERR_MASK N/A Write 1 to COMM_FRM_ERR_INT bit SPI frame errorN/AInterrupt onlyNot validCOMM_FRM_ERR_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4 #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9DF08CFD-9BBC-447C-84ED-FCDE84D590E4COMM_FRM_ERR_MASKN/AWrite 1 to COMM_FRM_ERR_INT bit I2C1 or SPI CRC error N/A Interrupt only Not valid COMM_CRC_ERR_INT = 1 COMM_CRC_ERR_MASK N/A Write 1 to COMM_CRC_ERR_INT bit I2C1 or SPI CRC errorN/AInterrupt onlyNot validCOMM_CRC_ERR_INT = 1COMM_CRC_ERR_MASKN/AWrite 1 to COMM_CRC_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid COMM_ADR_ERR_INT = 1 COMM_ADR_ERR_MASK N/A Write 1 to COMM_ADR_ERR_INT bit I2C1 or SPI address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9CN/AInterrupt onlyNot validCOMM_ADR_ERR_INT = 1COMM_ADR_ERR_MASKN/AWrite 1 to COMM_ADR_ERR_INT bit I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_INT = 1 I2C2_CRC_ERR_MASK N/A Write 1 to I2C2_CRC_ERR_INT bit I2C2 CRC errorN/AInterrupt onlyNot validI2C2_CRC_ERR_INT = 1I2C2_CRC_ERR_MASKN/AWrite 1 to I2C2_CRC_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C N/A Interrupt only Not valid I2C2_ADR_ERR_INT = 1 I2C2_ADR_ERR_MASK N/A Write 1 to I2C2_ADR_ERR_INT bit I2C2 address error#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9C #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-7AB53B62-E467-4C08-BA51-CAD05393EC9CN/AInterrupt onlyNot validI2C2_ADR_ERR_INT = 1I2C2_ADR_ERR_MASKN/AWrite 1 to I2C2_ADR_ERR_INT bit PFSM error IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery. PFSM_ERR_INT = 1 N/A Write 1 to PFSM_ERR_INT bit PFSM errorIMMEDIATE_SHUTDOWN (SEVERE_ERR_INT)All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] state. If previous PFSM_ERR_INT is pending, VCCA power cycle needed for recovery.PFSM_ERR_INT = 1N/AWrite 1 to PFSM_ERR_INT bit EN_DRV pin read-back error (monitoring high and low states) N/A Interrupt only Not valid EN_DRV_READBACK_INT = 1 EN_DRV_READBACK_MASK EN_DRV_READBACK_STAT Write 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present EN_DRV pin read-back error (monitoring high and low states)N/AInterrupt onlyNot validEN_DRV_READBACK_INT = 1EN_DRV_READBACK_MASKEN_DRV_READBACK_STATWrite 1 to EN_DRV_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NINT_READBACK_INT = 1 NINT_READBACK_MASK NINT_READBACK_STAT Write 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NINT pin read-back error (monitoring low state)ORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateNINT_READBACK_INT = 1NINT_READBACK_MASKNINT_READBACK_STATWrite 1 to NINT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state) ORDERLY_SHUTDOWN (MODERATE_ERR_INT) All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state NRSTOUT_READBACK_INT = 1 NRSTOUT_READBACK_MASK NRSTOUT_READBACK_STAT Write 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT pin read-back error (monitoring low state)ORDERLY_SHUTDOWN (MODERATE_ERR_INT)All regulators deactivated and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateNRSTOUT_READBACK_INT = 1NRSTOUT_READBACK_MASKNRSTOUT_READBACK_STATWrite 1 to NRSTOUT_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state) N/A Interrupt only Not valid NRSTOUT_SOC_READBACK_INT = 1 NRSTOUT_SOC_READBACK_MASK NRSTOUT_SOC_READBACK_STAT Write 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present NRSTOUT_SOC pin read-back error (monitoring low state)N/AInterrupt onlyNot validNRSTOUT_SOC_READBACK_INT = 1NRSTOUT_SOC_READBACK_MASKNRSTOUT_SOC_READBACK_STATWrite 1 to NRSTOUT_SOC_READBACK_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation) N/A Interrupt only Not valid ESM_SOC_PIN_INT = 1 ESM_SOC_PIN_MASK N/A Write 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level detected, PWM mode: PWM signal timing violation)N/AInterrupt onlyNot validESM_SOC_PIN_INT = 1ESM_SOC_PIN_MASKN/AWrite 1 to ESM_SOC_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_SOC_FAIL_INT = 1 ESM_SOC_FAIL_MASK N/A Write 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1time)N/AInterrupt and EN_DRV = 0 (configurable)Not validESM_SOC_FAIL_INT = 1ESM_SOC_FAIL_MASKN/AWrite 1 to ESM_SOC_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_SOC_RST Interrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of SoC warm reset ESM_SOC_RST_INT = 1 ESM_SOC_RST_MASK N/A Write 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by SOC ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time)ESM_SOC_RSTInterrupt, and NRSTOUT_SOC toggle#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatically returns to the current operating state after the completion of SoC warm resetESM_SOC_RST_INT = 1ESM_SOC_RST_MASKN/AWrite 1 to ESM_SOC_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery thresholdTPS6593-Q1 Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violation N/A Interrupt only Not valid ESM_MCU_PIN_INT = 1 ESM_MCU_PIN_MASK N/A Write 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level detected, PWM mode: PWM signal timing violationN/AInterrupt onlyNot validESM_MCU_PIN_INT = 1ESM_MCU_PIN_MASKN/AWrite 1 to ESM_MCU_PIN_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time) N/A Interrupt and EN_DRV = 0 (configurable) Not valid ESM_MCU_FAIL_INT = 1 ESM_MCU_FAIL_MASK N/A Write 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1 time)N/AInterrupt and EN_DRV = 0 (configurable)Not validESM_MCU_FAIL_INT = 1ESM_MCU_FAIL_MASKN/AWrite 1 to ESM_MCU_FAIL_INT bit Interrupt is not cleared if the associated fault condition is still present Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time) ESM_MCU_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset ESM_MCU_RST_INT = 1 ESM_MCU_RST_MASK N/A Write 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Fault detected by MCU ESM (level mode: low level longer than DELAY1+DELAY2 time, PWM mode: ESM error counter > FAIL_THR longer than DELAY1+DELAY2 time)ESM_MCU_RSTInterrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatically returns to the current operating state after the completion of warm resetESM_MCU_RST_INT = 1ESM_MCU_RST_MASKN/AWrite 1 to ESM_MCU_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery thresholdTPS6593-Q1 External clock is expected, but it is not available or the frequency is not in the valid range N/A Interrupt only Not valid EXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 EXT_CLK_MASK EXT_CLK_STAT Write 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present External clock is expected, but it is not available or the frequency is not in the valid rangeN/AInterrupt onlyNot validEXT_CLK_INT = 1#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721 #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/SNVSA486721EXT_CLK_MASKEXT_CLK_STATWrite 1 to EXT_CLK_INT bit Interrupt is not cleared if the associated fault condition is still present BIST completed successfully N/A Interrupt only Not valid BIST_PASS_INT = 1 BIST_PASS_MASK N/A Write 1 to BIST_PASS_INT bit BIST completed successfullyN/AInterrupt onlyNot validBIST_PASS_INT = 1BIST_PASS_MASKN/AWrite 1 to BIST_PASS_INT bit Watchdog fail counter above fail threshold N/A Interrupt and EN_DRV = 0 Clear interrupt and WD_FAIL_CNT < WD_FAIL_TH WD_FAIL_INT = 1 N/A N/A Write 1 to WD_FAIL_INT bit Watchdog fail counter above fail thresholdN/AInterrupt and EN_DRV = 0 and EN_DRVClear interrupt and WD_FAIL_CNT < WD_FAIL_THWD_FAIL_INT = 1N/AN/AWrite 1 to WD_FAIL_INT bit Watchdog fail counter above reset threshold WD_RST (if WD_RST_EN = 1) Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_RST_INT = 1 N/A N/A Write 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog fail counter above reset thresholdWD_RST (if WD_RST_EN = 1)Interrupt and Warm Reset if WD_RST_EN = 1 (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D EN_DRV = 0 and#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatically returns to the current operating state after the completion of warm resetWD_RST_INT = 1N/AN/AWrite 1 to WD_RST_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery thresholdTPS6593-Q1 Watchdog long window timeout WD_RST Interrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatically returns to the current operating state after the completion of warm reset WD_LONGWIN_TIMEOUT_INT = 1 N/A N/A Write 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery threshold Watchdog long window timeoutWD_RSTInterrupt and Warm Reset (EN_DRV = 0 and NRSTOUT and NRSTOUT_SOC toggle)#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D EN_DRV = 0 and#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatically returns to the current operating state after the completion of warm resetWD_LONGWIN_TIMEOUT_INT = 1N/AN/AWrite 1 to WD_LONGWIN_TIMEOUT_INT bit This bit can only be read by the MCU after the TPS6593-Q1 has executed a warm-reset and the recovery counter does not exceed the recovery thresholdTPS6593-Q1 RTC alarm wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ALARM = 1 IT_ALARM = 0 N/A Write 1 to ALARM bit RTC alarm wake-upTRIGGER_SU_xStart-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validALARM = 1IT_ALARM = 0N/AWrite 1 to ALARM bit RTC timer wake-up TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit RTC timer wake-upTRIGGER_SU_xStart-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validTIMER = 1IT_TIMER = 0N/AWrite 1 to TIMER bit Low state in NPWRON pin TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid NPWRON_START_INT = 1 NPWRON_START_MASK NPWRON_IN Write 1 to NPWRON_START_INT bit Low state in NPWRON pinTRIGGER_SU_xStart-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validNPWRON_START_INT = 1NPWRON_START_MASKNPWRON_INWrite 1 to NPWRON_START_INT bit Long low state in NPWRON pin ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid power-on request NPWRON_LONG_INT = 1 NPWRON_LONG_MASK NPWRON_IN Write 1 to NPWRON_LONG_INT bit Long low state in NPWRON pinORDERLY_SHUTDOWNAll regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DValid power-on requestNPWRON_LONG_INT = 1NPWRON_LONG_MASKNPWRON_INWrite 1 to NPWRON_LONG_INT bit Low state in ENABLE pin TRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBY Transition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D ENABLE pin rise N/A N/A N/A N/A Low state in ENABLE pinTRIGGER_FORCE_STANDBY/TRIGGER_FORCE_LP_STANDBYTransition to STANDBY or LP_STANDBY depending on the LP_STANDBY_SEL bit setting#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DENABLE pin riseN/AN/AN/AN/A ENABLE pin rise TRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT Write 1 to ENABLE_INT bit ENABLE pin riseTRIGGER_SU_x #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validENABLE_INT = 1ENABLE_MASKENABLE_STATWrite 1 to ENABLE_INT bit Fault causing orderly shutdown ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state ORD_SHUTDOWN_INT ORD_SHUTDOWN_MASK N/A Write 1 to ORD_SHUTDOWN_INT Fault causing orderly shutdownORDERLY_SHUTDOWNAll regulators deactivated and Output GPIOx set to low in a sequence and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateORD_SHUTDOWN_INTORD_SHUTDOWN_MASKN/AWrite 1 to ORD_SHUTDOWN_INT Fault causing immediate shutdown IMMEDIATE_SHUTDOWN All regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state IMM_SHUTDOWN_INT IMM_SHUTDOWN_MASK N/A Write 1 to IMM_SHUTDOWN_INT Fault causing immediate shutdownIMMEDIATE_SHUTDOWNAll regulators deactivated (depending on NVM configuration with or without pull-down resistors) and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] stateIMM_SHUTDOWN_INTIMM_SHUTDOWN_MASKN/AWrite 1 to IMM_SHUTDOWN_INT Power supply error for MCU MCU_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram MCU_PWR_ERR_INT MCU_PWR_ERR_MASK N/A Write 1 to MCU_PWR_ERR_INT Power supply error for MCUMCU_POWER_ERRORTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramMCU_PWR_ERR_INTMCU_PWR_ERR_MASKN/AWrite 1 to MCU_PWR_ERR_INT Power supply error for SOC SOC_POWER_ERROR Transition according to FSM trigger and interrupt Depends on PFSM configuration, see PFSM transition diagram SOC_PWR_ERR_INT SOC_PWR_ERR_MASK N/A Write 1 to SOC_PWR_ERR_INT Power supply error for SOCSOC_POWER_ERRORTransition according to FSM trigger and interruptDepends on PFSM configuration, see PFSM transition diagramSOC_PWR_ERR_INTSOC_PWR_ERR_MASKN/AWrite 1 to SOC_PWR_ERR_INT VCCA over-voltage (VCCAOVP) IMMEDIATE_SHUTDOWN (SEVERE_ERR_INT) All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Automatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP VCCA_OVP_INT = 1 N/A VCCA_OVP_STAT Write 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared. VCCA over-voltage (VCCAOVP)OVPIMMEDIATE_SHUTDOWN (SEVERE_ERR_INT)All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DAutomatic start-up to STARTUP_DEST[1:0] state after VCCA voltage is below VCCAOVP OVPVCCA_OVP_INT = 1N/AVCCA_OVP_STATWrite 1 to VCCA_OVP _INT bitThis bit can only be read by the MCU if VCCA < VCCAOVP level. As long as VCCA ⩾ VCCAOVP level, device stays in SAFE RECOVEY state, and hence this interrupt cannot be not cleared.OVPOVP GPIO interrupt According to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bits Transition according to FSM trigger and interrupt Not valid GPIOx_INT = 1 GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit GPIO interruptAccording to GPIOx_FSM_MASK and GPIOx_FSM_MASK_POL bitsTransition according to FSM trigger and interruptNot validGPIOx_INT = 1GPIOx_RISE_MASK GPIOx_FALL_MASKGPIOx_INWrite 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals WKUP1 Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP1 and LP_WKUP1 signals and LP_WKUP1WKUP1Transition to ACTIVE state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validN/AGPIOx_RISE_MASK GPIOx_FALL_MASKGPIOx_INWrite 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals WKUP2 Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid N/A GPIOx_RISE_MASK GPIOx_FALL_MASK GPIOx_IN Write 1 to GPIOx_INT bit WKUP2 and LP_WKUP2 signals and LP_WKUP2WKUP2Transition to MCU ONLY state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validN/AGPIOx_RISE_MASK GPIOx_FALL_MASKGPIOx_INWrite 1 to GPIOx_INT bit NSLEEP1 signal, NSLEEP1B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A NSLEEP1 signal, NSLEEP1B bitAccording to NSLEEP1 and NSLEEP2State transition based on NSLEEP1 and NSLEEP2Not validN/ANSLEEP1_MASKGPIOx_INN/A NSLEEP2 signal, NSLEEP2B bit According to NSLEEP1 and NSLEEP2 State transition based on NSLEEP1 and NSLEEP2 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A NSLEEP2 signal, NSLEEP2B bitAccording to NSLEEP1 and NSLEEP2State transition based on NSLEEP1 and NSLEEP2Not validN/ANSLEEP2_MASKGPIOx_INN/A LDOVINT over- or undervoltage Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Valid LDOVINT voltage N/A N/A N/A N/A LDOVINT over- or undervoltageReset condition for all logic circuitsAll regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DValid LDOVINT voltageN/AN/AN/AN/A Main clock outside valid frequency Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Main clock outside valid frequencyReset condition for all logic circuitsAll regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DVCCA power cycleN/AN/AN/AN/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 ORDERLY_SHUTDOWN All regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA power cycle N/A N/A N/A N/A Recovery counter limit exceeded#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1 #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-62DA79CD-FF8E-46FB-B352-C566571197E1ORDERLY_SHUTDOWNAll regulators deactivated and Output GPIOx set to low in a sequence#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DVCCA power cycleN/AN/AN/AN/A VCCA supply falling below VCCAUVLO Reset condition for all logic circuits All regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D VCCA voltage rising N/A N/A N/A N/A VCCA supply falling below VCCAUVLO UVLOReset condition for all logic circuitsAll regulators deactivated with pull-down resistors and Output GPIOx set to low immediately#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DVCCA voltage risingN/AN/AN/AN/A First supply detection, VCCA supply rising above VCCAUVLO TRIGGER_SU_x Start-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D Not valid FSD_INT = 1 FSD_MASK N/A Write 1 to FSD_INT bit First supply detection, VCCA supply rising above VCCAUVLO UVLOTRIGGER_SU_xStart-up to STARTUP_DEST[1:0] state and interrupt#GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4D #GUID-3D6886D7-5E33-49FE-9D3A-1031C2320523/GUID-9C16B3DF-4913-471A-9BEE-93C8FBAA2C4DNot validFSD_INT = 1FSD_MASKN/AWrite 1 to FSD_INT bit The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations. Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled. This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt. I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and documentation before deviating from these recommendations.Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually saturates when it reaches the maximum count of 15. Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not cause the COMM_FRM_ERR_INT interrupt.I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'. RTC General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC Interrupts The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling RTC General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions.The main functions of the RTC block are: Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code Calendar information (day, month, year, and day of the week) in BCD code up to year 2099 Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) codeCalendar information (day, month, year, and day of the week) in BCD code up to year 2099Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and masked individually: Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods) Alarm interrupt at a precise time of the day (alarm function) Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods)Alarm interrupt at a precise time of the day (alarm function)Oscillator frequency calibration and time correction with 1/32768 resolution shows the RTC block diagram. RTC Block Diagram RTC Block Diagram Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413: RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Month data ranges from 01 to 12. Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year Weekday value ranges from 0 to 6. Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. Minutes value ranges from 0 to 59. Seconds value ranges from 0 to 59. Year data ranges from 00 to 99. Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) Common Year = Other years Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on)Common Year = Other yearsMonth data ranges from 01 to 12.Day value ranges: 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 1 to 30 when months are 4, 6, 9, 11 1 to 29 when month is 2 and year is a leap year 1 to 28 when month is 2 and year is a common year 1 to 31 when months are 1, 3, 5, 7, 8, 10, 121 to 30 when months are 4, 6, 9, 111 to 29 when month is 2 and year is a leap year1 to 28 when month is 2 and year is a common yearWeekday value ranges from 0 to 6.Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode.Minutes value ranges from 0 to 59.Seconds value ranges from 0 to 59.Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in #GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413:#GUID-D55684DC-1A31-4EAF-B994-D540AFAEA45A/SWCS0959413 RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 RTC Time Calendar Registers Example REGISTER CONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 REGISTER CONTENT REGISTER CONTENT REGISTERCONTENT RTC_SECONDS 0x36 RTC_MINTURES 0x54 RTC_HOURS 0x10 RTC_DAYS 0x05 RTC_MONTHS 0x09 RTC_YEARS 0x08 RTC_WEEKS 0x06 RTC_SECONDS 0x36 RTC_SECONDS0x36 RTC_MINTURES 0x54 RTC_MINTURES0x54 RTC_HOURS 0x10 RTC_HOURS0x10 RTC_DAYS 0x05 RTC_DAYS0x05 RTC_MONTHS 0x09 RTC_MONTHS0x09 RTC_YEARS 0x08 RTC_YEARS0x08 RTC_WEEKS 0x06 RTC_WEEKS0x06The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed.Example: If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S If current time is 10H59M45S, round operation changes time to 11H00M00S If current time is 10H59M29S, round operation changes time to 10H59M00S If current time is 10H59M45S, round operation changes time to 11H00M00SIf current time is 10H59M29S, round operation changes time to 10H59M00S TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Read Access TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC register read access can be done in two ways: A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading.Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. TC Registers Write Access TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated ALARM interrupts. See for how these register values are written in BCD code, with the same data range as described for the TC registers. RTC Interrupts The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. RTC Interrupts The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. The RTC supports two types of interrupts: ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing. TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing. ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent the interrupt from mis-firing.TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing.Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the LP_STANDBY state when they are not masked. RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value. The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must perform an external calibration of the oscillator frequency by calculating the needed drift compensation compared to one hour time-period, and load the compensation registers with the drift compensation value.The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The compensation process happens after the first second of each hour. The time between second 1 and second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-second time-unit accuracy per hour and up to 1 second per hour.(32768 - COMP_REG) / 32768Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2.If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading of the internal 32-kHz counter can only be done when the RTC is stopped. shows the RTC compensation scheduling. RTC Compensation Scheduling RTC Compensation Scheduling Watchdog (WDOG) A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. Watchdog Fail Counter and Status The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. Watchdog Start-Up and Configuration When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] MCU to Watchdog Synchronization In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. Watchdog Disable Function The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. Watchdog Sequence Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Watchdog Trigger Mode When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. WatchDog Flow Chart and Timing Diagrams in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog Question-Answer Mode A 20220110 Added Section:Watchdog Question-Answer Modeyes When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Watchdog (WDOG) A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes A 20220110 Watchdog (WDOG): added Q&A (question an answer) modeyes A20220110Watchdog (WDOG): added Q&A (question an answer) modeyes yes The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. The MCU can control the logic-level of the EN_DRV pin when the watchdog detects correct operation of the MCU.EN_DRVWhen the watchdog detects an incorrect operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin lowTPS6593-Q1EN_DRV.This EN_DRV pin can be used in the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU.EN_DRVThe watchdog has two different modes that are defined as follows: Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details. Trigger modeIn trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details.WD_pulsepre-assigned Q&A (question and answer) mode In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. Q&A (question and answer) modeIn Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details). To select this mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides more details. 1, I2C2 bus or SPI bus. (Which of these communication busses is to be used depends on the NVM configuration. Please refer to the user's guide of the orderable part number for further details) Watchdog Question-Answer Mode provides more details. Watchdog Fail Counter and Status The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. Watchdog Fail Counter and Status The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low. When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or decrements because of good events. Furthermore, the watchdog includes two configurable thresholds: Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) bad eventsgood events Fail-threshold (configurable through bits WD_FAIL_TH[2:0]) Reset-threshold (configurable through bits WD_RST_TH[2:0]) Fail-threshold (configurable through bits WD_FAIL_TH[2:0])Reset-threshold (configurable through bits WD_RST_TH[2:0])When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold (WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-flags are set. WD_FIRST_OKMCU can set the ENABLE_DRV bit when no other error-flags are setWhen the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold (WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag WD_FAIL_INT, and pulls the nINT pin low.clears the ENABLE_DRV bit,WD_FAIL_INTWhen the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time. generates a WD_ERROR trigger in the state machine (see PFSM Trigger Selections) andWD_RST_INTUnless described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and released after a pre-configured delay time.TPS6593-Q1nRSTOUT pinThe device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits.WD_FAIL_INTWD_RST_INTOverview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0] Device Status Watchdog Fail Counter value WD_FAIL_CNT[3:0]Device Status WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set. WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0] MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no other error-flags are set.MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and WD_FIRST_OK WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])The device sets error-flag WD_FAIL_INT and pulls the nINT pin low. Furthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_INTFurthermore, , the device clears the ENABLE_DRV bit. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])If configuration bit WD_RST_EN=1, device generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM, sets the error-flag WD_RST_INT, and pulls the nINT pin low. See Summary of Interrupt Signals for the interrupt handling of WD_RST. generates WD_ERROR trigger in the state machine and reacts as defined in the PFSM,WD_RST_INTSee Summary of Interrupt Signals for the interrupt handling of WD_RST.The WD_FAIL_CNT[3:0] counter responds as follows: When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000 A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1 A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1ARefer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good events and bad events. and Watchdog Q&A Related Definitions respectively Watchdog Start-Up and Configuration When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] Watchdog Start-Up and Configuration When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0]. As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation The device keeps the above register bit values configured by the MCU as long as the device is powered. The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps Use #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00: tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 If the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate. When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window. The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0].LONG_WINDOWAs long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits: WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation WD_EN to enable or disable the watchdog WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode) WD_PWRHOLD to activate the Watchdog Disable function (more detail in ) WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in ) WD_WIN1[6:0] to configure the duration of the Window-1 time-interval WD_WIN2[6:0] to configure the duration of the Window-2 time-interval WD_RST_EN to enable or disable the watchdog-reset function WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold WD_RST_TH[2:0] to configure the Watchdog-Reset threshold WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation WD_QA_LFSR[1:0] to configure the settings for the question-generation WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation WD_EN to enable or disable the watchdogWD_LONGWIN[7:0] to increase the duration of the Long-Window time-intervalincreaseWD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode)WD_PWRHOLD to activate the Watchdog Disable function (more detail in )WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in )WD_WIN1[6:0] to configure the duration of the Window-1 time-intervalWD_WIN2[6:0] to configure the duration of the Window-2 time-intervalWD_RST_EN to enable or disable the watchdog-reset functionWD_FAIL_TH[2:0] to configure the Watchdog-Fail thresholdWD_RST_TH[2:0] to configure the Watchdog-Reset thresholdWD_QA_FDBK[1:0] to configure the settings for the reference answer-generationWD_QA_LFSR[1:0] to configure the settings for the question-generationWD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generationThe device keeps the above register bit values configured by the MCU as long as the device is powered.The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps LONG_WINDOWThe WD_LONGWIN[7:0] bits are defined as: 0x00: 80 ms 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps 0x00: 80 ms0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps0x41 - 0xFF: 12 sec to 772 sec, in 4-sec stepsUse #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888 and #GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625 to calculate the minimum and maximum values for the Long Window (tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00:#GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE828888#GUID-349299FD-F71B-4E28-A307-921903D70A3E/SLVSE822625LONG_WINDOWtLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 LONG_WINDOW_MINtLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05LONG_WINDOW_MAXIf the MCU software changes the duration of the Long-Window to an interval shorter than the time in which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no longer operate.When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window.When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set., and the MCU can control the ENABLE_DRV bit when no other error-flags are setThe watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence: WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] WD_WIN1[6:0] WD_WIN2[6:0] WD_LONGWIN[7:0] WD_MODE_SELECT WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0] WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] WD_WIN1[6:0]WD_WIN2[6:0]WD_LONGWIN[7:0]WD_MODE_SELECTWD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0]WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0] MCU to Watchdog Synchronization In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. MCU to Watchdog Synchronization In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode When the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it. In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following before elapse of the Long Window time interval: Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode Clear bits WD_PWRHOLD (more detail in ) Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode Clear bits WD_PWRHOLD (more detail in )Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the watchdog is configured for Trigger mode, or WD_pulsepre-assigned in the case the watchdog is configured for Trigger mode, orWrite four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A modeWhen the MCU fails to get the watchdog out of the Long Window before the configured Long Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it.LONG_WINDOWthrough a warm reset,WD_LONGWIN_TIMEOUT_INT‘1’ to clear it Watchdog Disable Function The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. Watchdog Disable Function The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit. In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation. The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit.TPS6593-Q1WD_DISIn case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU, the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog sequence (as described in ), the MCU must clear bit WD_RETURN_LONGWIN before the end of the first watchdog sequence in order to continue the watchdog sequence operation.LONG_WINDOW Watchdog Sequence Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Watchdog Sequence Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence. Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval. tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval. tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next sequence when one of the events below occurs: The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The configured Window-2 time period elapses The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A mode The configured Window-2 time period elapsesThe watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if the watchdog is used in Trigger mode WD_pulsepre-assigned GPIO pinif the watchdog is used in Trigger modeThe watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A modeThe MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence.WINDOW1WINDOW2Use #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785 to calculate the minimum and maximum values for the tWINDOW1 time interval.#GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822895#GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE828785WINDOW1tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 msWINDOW1_MINtWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 msWINDOW1_MAXUse #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341 and #GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158 to calculate the minimum and maximum values for the tWINDOW-2 time interval.#GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE824341#GUID-601CEE28-A758-488E-9836-FEEC1D7197D3/SLVSE822158WINDOW-2tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 msWINDOW2_MINtWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 msWINDOW2_MAX Watchdog Trigger Mode When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. Watchdog Trigger Mode When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin . The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event. The watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max). The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin .TPS6593-Q1pre-assigned GPIO pinWD_pulse(max)WD_pulsepre-assigned GPIO pinThe watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event.good eventpre-assignedWD_pulseThe watchdog detects a bad event when one of the following events occurs: The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. bad event The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT. No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT. The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT.pre-assigned GPIO pinWD_pulseNo watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the device sets bits WD_TIMEOUT and WD_BAD_EVENT.Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max).WD_pulse (max)The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence.WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode. WatchDog Flow Chart and Timing Diagrams in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. WatchDog Flow Chart and Timing Diagrams in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Flow Chart for WatchDog Monitor in Trigger Mode Flow Chart for WatchDog Monitor in Trigger Mode , , , , and give examples of watchdog is trigger mode with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one 20-MHz system clock cycle. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event. Watchdog Question-Answer Mode A 20220110 Added Section:Watchdog Question-Answer Modeyes When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Watchdog Question-Answer Mode A 20220110 Added Section:Watchdog Question-Answer Modeyes A 20220110 Added Section:Watchdog Question-Answer Modeyes A 20220110 Added Section:Watchdog Question-Answer Modeyes A20220110Added Section:Watchdog Question-Answer Modeyes yes When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU. The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence. A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU.TPS6593-Q1The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins. SPI or the dedicated I2C2 interface, mapped to GPIO1 and GPIO2 pins.212A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the correct watchdog window and in the correct sequence.A bad event occurs when one of the events that follows occur: The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. The MCU sends the correct answer-bytes, but not in the correct watchdog window. The MCU sends incorrect answer-bytes. The MCU returns correct answer-bytes, but in the incorrect sequence. The MCU sends the correct answer-bytes, but not in the correct watchdog window.The MCU sends incorrect answer-bytes.The MCU returns correct answer-bytes, but in the incorrect sequence.If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0] counter, and starts a new watchdog sequence. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Watchdog Q&A Related Definitions A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. A question and answer are defined as follows: Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. Question A question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event QuestionA question is a 4-bit word (see ). The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits. The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits.The MCU can request each new question at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also have a software implementation that generates the question according the circuit shown in . Nevertheless, the answer and therefore the answer-bytes are always based on the question generated inside the watchdog of the device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect question, the watchdog detects a bad event Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. AnswerAn answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event. The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0 in Window 2) to detect a good event.The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a time-out event when the Window-2 time-interval elapses. Watchdog Sequence in Q&A Mode The register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question (1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0. (2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses. Watchdog Sequence in Q&A ModeThe register WD_QUESTION_ANSW_CNT has following bits: Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question Bit 6: Reserved Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte Bit 3-0: WD_QUESTION. These bits give the value of the current generated question Bit 6: ReservedBit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byteBit 3-0: WD_QUESTION. These bits give the value of the current generated question(1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0.(2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses.2or SPI Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Question Generation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in ), and a 4-bit Markov chain to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog generates a new question when the question counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event.question counterThe question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000. The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out of the Long Window. The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In following situations, the MCU software needs to read the current question in order to synchronize with the Question-Generator: After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 After MCU re-boot from a warm-reset After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long Window After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 After MCU re-boot from a warm-reseta warm-After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long WindowAfter MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1 shows the logic combination for the WD_QUESTION[3:0] generation. shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits generates the reference answer-bytes. Watchdog Question Generation (1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Question Generation(1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question generation begins from this value. Watchdog Reference Answer Calculation Watchdog Reference Answer Calculation Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Answer Comparison The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0]. The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and controls the generation of the reference answer-byte as shown in . At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects the MCU to write the correct Answer-3 in WD_ANSWER[7:0].The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears this status bit only if the MCU writes a ‘1’ to this bit. Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value: WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. WD_ANSW_CNT[1:0] = 2‘b11: The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. The watchdog calculates the reference Answer-3. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0]. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect. The watchdog calculates the reference Answer-3.A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0].The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0].The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status bit to 1 if the Answer-3 byte was incorrect.WD_ANSW_CNT[1:0] = 2b‘10: The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. The watchdog calculates the reference Answer-2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect. The watchdog calculates the reference Answer-2.A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0].The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0]..The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status bit to 1 if the Answer-2 byte was incorrect.WD_ANSW_CNT[1:0] = 2b‘01: The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. The watchdog calculates the reference Answer-1. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0].. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect. The watchdog calculates the reference Answer-1.A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0].The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0]..The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status bit to 1 if the Answer-1 byte was incorrect.WD_ANSW_CNT[1:0] = 2b‘00: The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. The watchdog calculates the reference Answer-0. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0]. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0]. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. The watchdog calculates the reference Answer-0.A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0].The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0].The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect.The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG Register WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 WD QUESTION ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) WD QUESTIONANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0]) ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0 ANSWER-3ANSWER-2ANSWER-1ANSWER-0 WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x1 B0 40 BF 4F 0x2 E9 19 E6 16 0x3 A6 56 A9 59 0x4 75 85 7A 8A 0x5 3A CA 35 C5 0x6 63 93 6C 9C 0x7 2C DC 23 D3 0x8 D2 22 DD 2D 0x9 9D 6D 92 62 0xA C4 34 CB 3B 0xB 8B 7B 84 74 0xC 58 A8 57 A7 0xD 17 E7 18 E8 0xE 4E BE 41 B1 0xF 01 F1 0E FE WD_QUESTION[3:0] WD_ANSW_CNT [1:0] = 2’b11 WD_ANSW_CNT [1:0] = 2’b10 WD_ANSW_CNT [1:0] = 2’b01 WD_ANSW_CNT [1:0] = 2’b00 WD_QUESTION[3:0]WD_ANSW_CNT [1:0] = 2’b11WD_ANSW_CNT [1:0] = 2’b10WD_ANSW_CNT [1:0] = 2’b01WD_ANSW_CNT [1:0] = 2’b00 0x0 FF 0F F0 00 0x0FF0FF000 0x1 B0 40 BF 4F 0x1B040BF4F 0x2 E9 19 E6 16 0x2E919E616 0x3 A6 56 A9 59 0x3A656A959 0x4 75 85 7A 8A 0x475857A8A 0x5 3A CA 35 C5 0x53ACA35C5 0x6 63 93 6C 9C 0x663936C9C 0x7 2C DC 23 D3 0x72CDC23D3 0x8 D2 22 DD 2D 0x8D222DD2D 0x9 9D 6D 92 62 0x99D6D9262 0xA C4 34 CB 3B 0xAC434CB3B 0xB 8B 7B 84 74 0xB8B7B8474 0xC 58 A8 57 A7 0xC58A857A7 0xD 17 E7 18 E8 0xD17E718E8 0xE 4E BE 41 B1 0xE4EBE41B1 0xF 01 F1 0E FE 0xF01F10EFE Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Watchdog Sequence Events and Status Updates The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode The watchdog sequence events are as follows for the different scenarios listed: A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. A good event occurs when all answer bytes are correct in value and timing. After such a good event, following events occur: The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence. The question-counter increments by one and the watchdog generates a new question. The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence.The question-counter increments by one and the watchdog generates a new question.A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad event, following events occur: The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1.The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers in Window-1.The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.The question-counter does not change, and hence the watchdog does not generate a new question.A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte.The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.The question-counter does not change, and hence the watchdog does not generate a new question.A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing. After such a bad event, following events occur: The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an incorrect answer-byte.The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1.The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-bytes in Window-1.The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.The question-counter does not change, and hence the watchdog does not generate a new question.A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval elapses. After a time-out event occurs, following events occur: WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence. The question-counter does not change, and hence the watchdog does not generate a new question. WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before watchdog has received Answer-3, Answer-2 and Answer-1.The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence.The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.The question-counter does not change, and hence the watchdog does not generate a new question.The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence.The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’ to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence. shows the flow-chart of the watchdog in Q&A mode. Flow Chart for WatchDog in Q&A Mode Flow Chart for WatchDog in Q&A Mode Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Watchdog Q&A Sequence Scenarios Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable Correct and Incorrect WD Q&A Sequence Run Scenarios NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT NUMBER OF WD ANSWERS ACTION WD STATUS BITS IN WDT_STATUS REGISTER COMMENTS NUMBER OF WD ANSWERSACTIONWD STATUS BITS IN WDT_STATUS REGISTERCOMMENTS RESPONSE WINDOW 1 RESPONSE WINDOW 2 ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT RESPONSE WINDOW 1RESPONSE WINDOW 2ANSW_ERRANSW_EARLYSEQ_ERRTIME_OUT 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 2 INCORRECT answers 1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 2 INCORRECT answers 2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 1 CORRECT answers 0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable 0 answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b No answers 0 answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b1bNo answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b0bWD_ANSW_CNT[1:0] = 3 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3 0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b0bWD_ANSW_CNT[1:0] = 3 0 answers 1 CORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 0 answers1 CORRECT answer-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b1bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 CORRECT answer 1 CORRECT answer1 CORRECT answer 2 CORRECT answer 1 CORRECT answer 2 CORRECT answer1 CORRECT answer 0 answers 1 INCORRECT answer -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 0 answers1 INCORRECT answer-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b1bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 CORRECT answer 1 INCORRECT answer 1 CORRECT answer1 INCORRECT answer 2 CORRECT answers 1 INCORRECT answer 2 CORRECT answers1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b0bLess than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 CORRECT answers 1 CORRECT answer3 CORRECT answers 2 CORRECT answers 2 CORRECT answers 2 CORRECT answers2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b0bLess than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 CORRECT answer 3 INCORRECT answers 1 CORRECT answer3 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers 2 CORRECT answers2 INCORRECT answers 0 answers 3 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 0 answers3 CORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b1bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 CORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b 1 INCORRECT answer2 CORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b1b 2 INCORRECT answers 1 CORRECT answer 2 INCORRECT answers1 CORRECT answer 0 answers 3 INCORRECT answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 1b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 0 answers3 INCORRECT answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b1bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 1 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer2 INCORRECT answer 2 INCORRECT answer 1 INCORRECT answer 2 INCORRECT answer1 INCORRECT answer 0 answers 4 CORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 0 answers4 CORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question0b0b1b0bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 CORRECT answers 1b 0b 1b 0b 1 INCORRECT answer3 CORRECT answers1b0b1b0b 2 INCORRECT answers 2 CORRECT answers 2 INCORRECT answers2 CORRECT answers 0 answers 4 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 1b 0b Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 0 answers4 INCORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b1b0bLess than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] = 3) 1 INCORRECT answer 3 INCORRECT answers 1 INCORRECT answer3 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers 2 INCORRECT answers2 INCORRECT answers 3 CORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question 0b 0b 0b 1b Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 3 CORRECT answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question0b0b0b1bLess than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (WD_ANSW_CNT[1:0] < 3) 2 CORRECT answers 0 answers 0b 0b 1b 1b 2 CORRECT answers0 answers0b0b1b1b 1 CORRECT answers 0 answers 1 CORRECT answers0 answers 3 CORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question 0b 0b 0b 0b CORRECT SEQUENCE 3 CORRECT answers1 CORRECT answer-New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question0b0b0b0bCORRECT SEQUENCE 3 CORRECT answers 1 INCORRECT answers -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 CORRECT answers1 INCORRECT answers-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b0b0bWD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 0 answers -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3 3 INCORRECT answers0 answers-New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question1b0b0b1bWD_ANSW_CNT[1:0] < 3 3 INCORRECT answers 1 CORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers1 CORRECT answer-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b0b0bWD_ANSW_CNT[1:0] = 3 3 INCORRECT answers 1 INCORRECT answer -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3 3 INCORRECT answers1 INCORRECT answer-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b0b0b0bWD_ANSW_CNT[1:0] = 3 4 CORRECT answers Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 0b 1b 0b 0b 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 4 CORRECT answersNot applicable-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question0b1b0b0b4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 3 CORRECT answers + 1 INCORRECT answer Not applicable -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question 1b 1b 0b 0b 3 CORRECT answers + 1 INCORRECT answerNot applicable-New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question1b1b0b0b 2 CORRECT answers + 2 INCORRECT answers Not applicable 2 CORRECT answers + 2 INCORRECT answersNot applicable 1 CORRECT answer + 3 INCORRECT answers Not applicable 1 CORRECT answer + 3 INCORRECT answersNot applicable Error Signal Monitor (ESM) A 20220110 Added Section: Error Signal Monitor (ESM)yes The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. ESM Error-Handling Procedure Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Error Signal Monitor (ESM) A 20220110 Added Section: Error Signal Monitor (ESM)yes A 20220110 Added Section: Error Signal Monitor (ESM)yes A 20220110 Added Section: Error Signal Monitor (ESM)yes A20220110Added Section: Error Signal Monitor (ESM)yes yes The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin. At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: Configuration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG Configuration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin. The MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START. The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pin.TPS6593-Q1twos):one ESM_MCU to monitor the MCU error output signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC input pinAt device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the corresponding ESM through software after the system is powered up and the initial software configuration is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM is started, the following configuration registers are write protected and can only be read: and ESM_SoCs and ESM_SOC_ENThe values for these configuration bits are sor ESM_SOC_START for the corresponding ESMacorrespondingConfiguration registers write-protected by the ESM_MCU_START register bit: ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG ESM_MCU_DELAY1_REG ESM_MCU_DELAY2_REG ESM_MCU_MODE_CFG ESM_MCU_HMAX_REG ESM_MCU_HMIN_REG ESM_MCU_LMAX_REG ESM_MCU_LMIN_REG ESM_MCU_DELAY1_REGESM_MCU_DELAY2_REGESM_MCU_MODE_CFGESM_MCU_HMAX_REGESM_MCU_HMIN_REGESM_MCU_LMAX_REGESM_MCU_LMIN_REGConfiguration registers write-protected by the ESM_SOC_START register bit: ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG ESM_SOC_DELAY1_REG ESM_SOC_DELAY2_REG ESM_SOC_MODE_CFG ESM_SOC_HMAX_REG ESM_SOC_HMIN_REG ESM_SOC_LMAX_REG ESM_SOC_LMIN_REG ESM_SOC_DELAY1_REGESM_SOC_DELAY2_REGESM_SOC_MODE_CFGESM_SOC_HMAX_REGESM_SOC_HMIN_REGESM_SOC_LMAX_REGESM_SOC_LMIN_REGThe ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin.degl_ESMxThe MCU can configure the ESM in two different modes that are defined as follows: Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. Level Mode the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx. To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail. Level Modethe ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the deglitch-time tdegl_ESMx.degl_ESMx To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detail.To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See for further detailTo select this mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. PWM Mode the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. PWM Modethe ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event when the frequency and duty cycle of the PWM signal match with the expected signal for one signal period. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value. To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details. The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM detects an ESM-error when the error-counter value is more than its related threshold value.or ESM_SOC_ERR_CNT[4:0]To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See for further details.To select this mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE.The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START.eachor ESM_SOC_STARTarelated relateds and ESM_SOC_START ESM Error-Handling Procedure Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) ESM Error-Handling Procedure Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1: Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2: Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 , in which x stands for either MCU or SoC. Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an ESM-error: If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC Each respective_x If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits). If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7. If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and pulls the nINT pin low._xor ESM_SOC_PIN_INTThe ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or ESM_SOC_DELAY1[7:0] bits).or ESM_SOC_DELAY1[7:0]If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin. relatedor ESM_SOC_PIN_INTIf the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1. relatedor ESM_SOC_PIN_INT or if bit ESM_SOC_ENDRV=1If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits) is set to 0, then the ESM skips steps 6 of this list, and performs step 7.or ESM_SOC_DELAY2[7:0]If the delay-2 timer is not set to 0, then: ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. ESM starts the delay-2 timer, If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer. ESM starts the delay-2 timer,If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin low and starts the delay-2 timer.If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low and starts the delay-2 timer.If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers and continues to monitor its input pin: ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6) ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or , orESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6)If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses, then : For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC related, or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU For ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC For ESM_MCU, the device: clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU clears the ESM_MCU_START BIT sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_MCU clears the ESM_MCU_START BITsets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for FSM, described in Summary of Interrupt SignalsAfter this trigger handling completes, the device re-initializes the ESM_MCUFor ESM_SoC, the device: clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC clears the ESM_SOC_START bit sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals After this trigger handling completes, the device re-initializes the ESM_SoC clears the ESM_SOC_START bitsets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for FSM, described in Summary of Interrupt SignalsAfter this trigger handling completes, the device re-initializes the ESM_SoCESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308 to calculate the worst-case values for the tDELAY-1:and ESM_SOC_DELAY1[7:0]DELAY-1relatedor ESM_SoC#GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE82707#GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827308DELAY-1Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95DELAY-1_xMax. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05DELAY-1_x, in which x stands for either MCU or SoC.eitheror SoCESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related ESM_MCU or ESM_SoC. Use #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186 and #GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893 to calculate the worst-case values for the tDELAY-2:or ESM_SOC_DELAY2[7:0]DELAY-2relatedor ESM_SoC#GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE827186#GUID-DF6532B4-B17E-4C92-B12D-2D4021966C59/SLVSE825893DELAY-2Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95DELAY-2_xMax. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05DELAY-2_x, in which x stands for either MCU or SoC.eitheror SoC Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM. For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects an ESM-error, it starts the ESM Error-Handling procedure as described in . The Error-Handling Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM.or bit ESM_SOC_STARTor nERR_SoCEachdegl_ESMxan_xdegl_ESMx_x_x_xFor a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC. , , , and show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the ESM_MCU is shown. In this flow-chart, the _x stands for either _MCUeither or _SoCIn these examples, only the ESM_MCU is shown. Flow Chart for Error Detection in Level Mode Flow Chart for Error Detection in Level Mode Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Before Elapse of Delay-2 Time-Interval Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2 PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) PWM Mode Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. Good-Events and Bad-Events In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows: After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 , in which x stands for either MCUor SoC. ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 , in which x stands for either MCU or SoC. Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances: ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) , in which x stands for either MCU or SoC. In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as follows:eachs After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring. After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoringLOW_MAX_THAfter a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse time-duration monitoring.HIGH_MAX_THIn addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. eachrelated or nERR_SoC A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0]. A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0]. A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0].HIGH_MAX_THcorresponding or ESM_SOC_HMAX[7:0]A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0].HIGH_MIN_THcorresponding or ESM_SOC_HMIN[7:0]A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0].LOW_MAX_THcorresponding or ESM_SOC_LMAX[7:0]A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0].LOW_MIN_THcorresponding or ESM_SOC_LMIN[7:0] Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the related input pin nERR_MCU or nERR_SoC: A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds Eachrelated or nERR_SoC A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, orA high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholdsRegister bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580 to calculate the worst-case values for the tHIGH_MAX_TH: and ESM_SOC_HMAX[7:0]HIGH_MAX_TH related#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE821225#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829580HIGH_MAX_THMin. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95HIGH_MAX_TH_xMax. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05HIGH_MAX_TH_x, in which x stands for either MCU or SoC. either or SoCESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911 to calculate the worst-case values for the tHIGH_MIN_TH: and ESM_SOC_HMIN[7:0]HIGH_MIN_TH related#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822177#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE828911HIGH_MIN_THMin. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95HIGH_MIN_TH_xMax. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05HIGH_MIN_TH_x, in which x stands for either MCU or SoC. either or SoCESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752 to calculate the worst-case values for the tLOW_MAX_TH: and ESM_SOC_LMAX[7:0]LOW_MAX_TH related#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829755#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823752LOW_MAX_THMin. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95LOW_MAX_TH_xMax. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05LOW_MAX_TH_x, in which x stands for either MCUor SoC. eitheror SoCESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the related ESM. Use #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247 and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117 to calculate the worst-case values for the tLOW_MIN_TH: and ESM_SOC_LMIN[7:0]LOW_MIN_TH related#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE822247#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE829117LOW_MIN_THMin. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95LOW_MIN_TH_xMax. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05LOW_MIN_TH_x, in which x stands for either MCU or SoC. either or SoCPlease note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated. #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780, #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462, and #GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152 are a guideline on how to incorporate these clock-tolerances:TPS6593-Q1#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE826982#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE823780#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE827462#GUID-8AB05BFB-234E-4174-9368-666CD9A02C95/SLVSE825152ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance)_x_x_x/SoC ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance)_x_x_x/SoC ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance)_x_x_x/SoC ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance)_x_x_x/SoC , in which x stands for either MCU or SoC. either or SoC ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. ESM Error-Counter If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1. The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM. If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1.anrelatedor bits ESM_SOC_ERR_CNT[4:0]anrelatedor bits ESM_SOC_ERR_CNT[4:0]The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. each_xFurthermore, the device clears the error-counter ESM_SOC_ERR[4:0] when it resets the SoC. Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . If the ESM error-counter reached a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes the related ESM.Eachrelatedor bits ESM_SOC_ERR_CNT_TH[3:0]related_xrelated_x_x_xrelated ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Start-Up in PWM Mode After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two possible scenarios: The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . anor bit ESM_SOC_START The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . related Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]. Wait for a first rising edge on its deglitched input signal. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3. If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0].correspondingor ESM_SOC_LMAX[7:0]Wait for a first rising edge on its deglitched input signal.If the rising edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 1.If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 3.correspondingor ESM_SOC_LMAX[7:0]relatedIf the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in .relatedDuring this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC. shows a scenario in which the device resets the MCU or SoC as Case Number 4.related_xor SoCor SoCIf the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in .The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this scenario, the related ESM starts the following procedure: Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . related Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]. Wait for a first falling edge on its deglitched input signal. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in . If the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in . During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0].correspondingor ESM_SOC_HMAX[7:0]Wait for a first falling edge on its deglitched input signal.If the falling edge comes before the configured time-length elapses, the ESM skips the next step and starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as described in . shows an example this scenario as Case Number 2.If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter with +2. Hereafter, the ESM detects good-events or bad-events as described in .correspondingor ESM_SOC_HMAX[7:0]relatedIf the ESM error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and starts the Error-Handling Procedure as described in .relatedDuring this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which, depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4.related_xor SoCIf the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in . ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode ESM Flow Chart and Timing Diagrams in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in . In this flow-chart, the _x stands for either _MCU or _SoC , , , and show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for either _MCU or _SoC In this flow-chart, the _x stands for either _MCUeither or _SoCIn this flow-chart, the _x stands for either _MCUeither or _SoC Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode Flow-Chart for ESM_MCU and ESM_SoC in PWM Modeand ESM_SoC Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC)or _SoC Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC)or _SoC Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC)or _SoC Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC) Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger to the PFSM (The _x stand for _MCU or _SoC)_xor _SoC Device Functional Modes Device State Machine The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. Fixed Device Power FSM The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Pre-Configurable Mission States When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram Error Handling Operations The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Device Start-up Timing shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. Power Sequences A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. First Supply Detection The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . Register Power Domains and Reset Levels The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT Multi-PMIC Synchronization A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation SPMI Interface System Setup An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. Transmission Protocol and CRC The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. SPMI Target Device Communication to SPMI Controller Device An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. SPMI-BIST Overview The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) Device Functional Modes Device State Machine The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. Fixed Device Power FSM The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Pre-Configurable Mission States When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram Error Handling Operations The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Device Start-up Timing shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. Power Sequences A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. First Supply Detection The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . Register Power Domains and Reset Levels The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT Device State Machine The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM. Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences. The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms. The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device during operating state transitions. The device supports NVM-configurable mission states with configurable input triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing. When a resource is not controlled or configured through a power sequence, the resource is left in the default state as pre-configured by the NVM.TPS6593-Q154 LDO regulators,11Each resource can be pre-configured through the NVM configuration, or re-configured through register bits. Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can automatically control the resource during state sequences.2The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper operation of all the power resources as well as the control interface and device IOs. control interface and device IOs.There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device: Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations TPS6593-Q1 Fixed Device Power Finite State Machine (FFSM) Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) Error Handling Operations Fixed Device Power Finite State Machine (FFSM)Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP) (ACTIVE, MCU_ONLY, S2R, DEEP_SLEEP)Error Handling OperationsThe PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to all platforms.and voltage monitoring Fixed Device Power FSM The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Fixed Device Power FSM The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured. Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails are fully enabled and ready to power external loadings, and the power down of the device when in the event of insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low. While the device is in one of the Hardware Device Powers states, the ENABLE_DRV bit remains low.The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured.Following are the definitions of the Device Power states: NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is completely powered off. NO SUPPLYThe device is not powered by a valid energy source on the system power rail. The device is completely powered off. BACKUP (RTC backup battery) The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. BACKUP (RTC backup battery)The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO); a backup power source, however, is present and is within the operating range of the LDOVRTC. The RTC clock counter remains active in this state if it has been previously activated by appropriate register enable bit. The calendar function of the RTC block is activated, but not accessible in this state. Customer has the option to enable the shelf mode by disconnecting the VCCA supply completely, even while the backup battery is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup battery. shelf mode shelf mode shelf mode shelf mode LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . LP_STANDBYThe device can enter this state from a mission state after receiving a valid OFF request or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in . or an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. Low Power Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When a logic level transition from high-to-low or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the device proceeds to power up the device and reach the default mission state. More details regarding the LP_WAKE function can be found in .RTC clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been previously activated by appropriate register enable bit. alsoLP_WKUPor if the device detects a valid on-request or a wake-up signal from the RTC block, or a wake-up signal from the RTC block INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly. INITThe device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC reads its internal NVM memory in this state and configures default values to registers, IO configuration and FSM accordingly.If the device was previously in LP_STANDBY state, it has received an external wake-up signal at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from the nPWRON/ENABLE pinLP_, the RTC alarm or timer wake-up signalnPWRON/ BOOT BIST The device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) BOOT BISTThe device is running the built-in self-test routine that includesThe ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. The ABIST on the voltage monitor circuits for the BUCK regulators, the LDO regulators is performed after the start-up of these regulators. The ABIST on the VMON1 and VMON2 is performed after these voltage monitors are enabled. See Voltage Monitors. An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. The following NVM bits are pre-configured options to enable or disable parts of the CRC tests if further sequence time reduction is required (please refer to the user's guide of the orderable part number): REG_CRC_EN = '0': disables the register map and SRAM CRC check Note: the BIST tests are executed as parallel processes, and the longest process determines the total BIST duration the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors) An option is available to shorten the device power up time from the NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before exceeding the recovery counter limit, the device powers up normally. REG_CRC_EN = '0': disables the register map and SRAM CRC check REG_CRC_EN = '0': disables the register map and SRAM CRC checkNote: the BIST tests are executed as parallel processes, and the longest process determines the total BIST durationthe ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators, VMON1 and VMON2 is performed individually after these voltage monitors are enabled. See Voltage Monitors)xn RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test (RUNTIME_BIST) on the device. No rails are modified and all external signals, including all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all enabled voltage monitor circuits. A request was received from the MCU A request was received from the MCU2If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided after the request for the BIST operation until the device pulls the nINT pin low to indicate the completion of BIST. The results of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt bits.After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages are not affected by this masking of the LDOx_UV detections. SAFE RECOVERY The device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold SAFE RECOVERYThe device meets the qualified error condition for immediate or ordered shutdown request. If the error is recovered within the recovery time interval or meets the restart condition, the device increments the recovery counter, and returns to INIT state if the recovery counter value does not exceed the threshold value. Until a supply power cycle occurs, the device stays in the SAFE RECOVERY state if one of the following conditions occur: the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN level VCCA stays above OVP threshold the recovery counter exceeds the threshold value the die temperature cannot be reduced to less than TWARN levelWARNVCCA stays above OVP thresholdWhen multiple system conditions occur simultaneously that demand power state arbitration, the device goes to the higher priority state according to the following priority order: NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES NO SUPPLY BACKUP SAFE_RECOVERY LP_STANDBY MISSION STATES NO SUPPLYBACKUPSAFE_RECOVERYLP_STANDBYMISSION STATES shows the power transition states of the FSM engine. State Diagram for Device Power States State Diagram for Device Power States Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Register Resets and NVM Read at INIT State Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Below are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits Below are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the TPS6593-Q1. These registers are referred to as NVM pre-configured registers. TPS6593-Q1TPS6593-Q1When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to '1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being over written. Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset Register resets and NVM read at INIT state FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration FIRST _STARTUP_DONE NVM pre-configured registers in RTC Domain Registers without NVM pre-configuration in RTC Domain Other NVM pre-configured registers Registers without NVM pre-configuration FIRST _STARTUP_DONENVM pre-configured registers in RTC DomainRegisters without NVM pre-configuration in RTC DomainOther NVM pre-configured registersRegisters without NVM pre-configuration 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 1 No changes No changes Reset and defaults read from NVM Reset 0 Defaults read from NVM No changes Reset and defaults read from NVM Reset 0Defaults read from NVMNo changesReset and defaults read from NVMReset 1 No changes No changes Reset and defaults read from NVM Reset 1No changesNo changesReset and defaults read from NVMResetBelow are the NVM pre-configured register bits in the RTC domain: GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits PFSM_DELAYn, and RTC_SPARE_n bits GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bitsGPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bitsNPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bitsFSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bitsSTARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bitsFAST_BIST, , XTAL_SEL, and XTAL_ENPFSM_DELAYn, and RTC_SPARE_n bitsBelow are the register bits without NVM pre-configuration in the RTC domain: FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers FIRST_STARTUP_DONE bit SCRATCH_PAD_n bits All of RTC control and configuration registers FIRST_STARTUP_DONE bitSCRATCH_PAD_n bitsAll of RTC control and configuration registers Pre-Configurable Mission States When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram Pre-Configurable Mission States When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers, further referred to as PFSM storage registers (R0-3). shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state. Error Source Hierarchical Mask System Error Source Hierarchical Mask System shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. provides the instruction set and usage description of each instruction in the following sections. describes how the instructions are stored in the NVM memory. PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). PFSM Instruction set Command Opcode Command Command Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). Command Opcode Command Command Description Command Opcode Command Command Description Command OpcodeCommandCommand Description "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). "0000" REG_WRITE_MASK_PAGE0_IMM Write the specified data, except the masked bits, to the specified page 0 register address. "0000"REG_WRITE_MASK_PAGE0_IMMWrite the specified data, except the masked bits, to the specified page 0 register address. "0001" REG_WRITE_IMM Write the specified data to the specified register address. "0001"REG_WRITE_IMMWrite the specified data to the specified register address. "0010" REG_WRITE_MASK_IMM Write the specified data, except the masked bits, to the specified register address. "0010"REG_WRITE_MASK_IMMWrite the specified data, except the masked bits, to the specified register address. "0011" REG_WRITE_VOUT_IMM Write the target voltage of a specified regulator after a specified delay. "0011"REG_WRITE_VOUT_IMMWrite the target voltage of a specified regulator after a specified delay. "0100" REG_WRITE_VCTRL_IMM Write the operation mode of a specified regulator after a specified delay. "0100"REG_WRITE_VCTRL_IMMWrite the operation mode of a specified regulator after a specified delay. "0101" REG_WRITE_MASK_SREG Write the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0101"REG_WRITE_MASK_SREGWrite the data from PFSM storage register (R0-3), except the masked bits, to the specified register address. "0110" SREG_READ_REG Write PFSM storage register (R0-3) with data from a specified address. "0110"SREG_READ_REGWrite PFSM storage register (R0-3) with data from a specified address. "0111" WAIT Execution is paused until the specified type of the condition is met or timed out. "0111"WAITExecution is paused until the specified type of the condition is met or timed out. "1000" DELAY_IMM Delay the execution by a specified time. "1000"DELAY_IMMDelay the execution by a specified time. "1001" DELAY_SREG Delay the execution by a time value stored in the specified PFSM storage register (R0-3). "1001"DELAY_SREGDelay the execution by a time value stored in the specified PFSM storage register (R0-3). "1010" TRIG_SET Set a trigger destination address for a given input signal or condition. "1010"TRIG_SETSet a trigger destination address for a given input signal or condition. "1011" TRIG_MASK Sets a trigger mask that determines which triggers are active. "1011"TRIG_MASKSets a trigger mask that determines which triggers are active. "1100" END Mark the final instruction in a sequential task. "1100"ENDMark the final instruction in a sequential task. "1101" REG_WRITE_BIT_PAGE0_IMM Write the specified data to the BIT_SEL location of the specified page 0 register address. "1101"REG_WRITE_BIT_PAGE0_IMMWrite the specified data to the BIT_SEL location of the specified page 0 register address. "1110" REG_WRITE_WIN_PAGE0_IMM Write the specified data to the SHIFT location of the specified page 0 register address. "1110"REG_WRITE_WIN_PAGE0_IMMWrite the specified data to the SHIFT location of the specified page 0 register address. "1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3). "1111"SREG_WRITE_IMMWrite the specified data to the PFSM storage register (R0-3). PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END PFSM Commands Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. Following section describes each PFSM command in detail and provides example usage codes. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power. More information on example NVM configuration, available device options and documentations can be found at Fully Customizable Integrated Power.Fully Customizable Integrated Power REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_IMM Command Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 Description: Write the specified data to the specified register address Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> Address and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 Description: Write the specified data to the specified register addressAssembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data> REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data>Address and Data can be in any literal integer format (decimal, hex, and so forth).'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order.Examples: REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10 REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10 REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1DREG_WRITE_IMM 0x1D 0x55 REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10REG_WRITE_IMM ADDR=0x10 DATA=0xFF REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10REG_WRITE_IMM DATA=0xFF ADDR=0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM Command Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 Description: Write the specified data, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 Description: Write the specified data, except the masked bits, to the specified register addressAssembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.Examples: REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1DREG_WRITE_MASK_IMM 0x1D 0x80 0xF0 REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM Command Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 Description: Write the specified data, except the masked bits, to the specified page 0 register address Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 Description: Write the specified data, except the masked bits, to the specified page 0 register addressAssembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.Examples: REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1D REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10 REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address 0x1DREG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the register at address 0x10REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the register at address 0x10REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM Command Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 Description: Write the specified data to the BIT_SEL location of the specified page 0 register address Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 Description: Write the specified data to the BIT_SEL location of the specified page 0 register addressAssembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data> REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data>Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth).'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order.Examples: REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10 REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1DREG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address 0x10REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_WIN_PAGE0_IMM Command Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. Description: Write the specified data to the SHIFT location of the specified page 0 register address Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth). 'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order. Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. Description: Write the specified data to the SHIFT location of the specified page 0 register addressAssembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift> REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask> [SHIFT=]<Shift>Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth).'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order.Examples: REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10. REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10 to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted 2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10.REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VOUT_IMM Command Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> 'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. VOUT = output voltage in mV or V. Unit must be listed. DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1) Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits.Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL> [VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS> [SEL=]<VSEL>[BYPASS=]<BYPASS>'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters can be in any order., ''SEL='and 'BYPASS='Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4 , BUCK5, LDO1, LDO2, LDO3, or LDO4. , BUCK5, LDO1, LDO2, LDO3, or LDO4, BUCK5VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3': Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored. nn-5nnnnIf Regulator ID is LDO1-4, VSEL value is ignored.VOUT = output voltage in mV or V. Unit must be listed.DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay.BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode (BYPASS=1)Examples: REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms. REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 ms REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active BUCK3_VSET register after 100 µsREG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets LDO1 to 700 mV in linear mode after 6 ms.REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets LDO2 to 3.3VV in bypass mode after 0 msREG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_VCTRL_IMM Command Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits. Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> 'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order. Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4. VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always) Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off of the REG_WRITE_IMM command with the intention to save instruction bits.Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode> REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL> [MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode>'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any order.Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4., BUCK5, LDO1, LDO2, LDO3, or LDO4VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_EN LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and BUCKn_ENnn_FPWM_MPLDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_ENDELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63, which becomes the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay.Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches) MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always)Examples: REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 ms REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000) after 100 µsREG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set LDO1_VMON and LDO1_EN to '1' after 10 msREG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 REG_WRITE_MASK_SREG Command Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 Description: Write the data from a PFSM storage register, except the masked bits, to the specified register address Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> 'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address and Mask can be in any literal integer format (decimal, hex, and so forth). Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 Description: Write the data from a PFSM storage register, except the masked bits, to the specified register addressAssembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask> REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address> [MASK=]<Mask>'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order.PFSM Storage Register can be R0, R1, R2, or R3.Address and Mask can be in any literal integer format (decimal, hex, and so forth).Examples: REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54 REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address 0x22REG_WRITE_MASK_SREG R2 0x22 0x00 REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage register R0 to address 0x54REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_READ_REG Command Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 Description: Write PFSM storage register (R0-3) with data from a specified address Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order. PFSM Storage Register can be R0, R1, R2, or R3. Address can be in any literal integer format (decimal, hex, and so forth). Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 Description: Write PFSM storage register (R0-3) with data from a specified addressAssembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address> 'REG=' and 'ADDR=' are options. When included, the parameters can be in any order.PFSM Storage Register can be R0, R1, R2, or R3.Address can be in any literal integer format (decimal, hex, and so forth).Examples: SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3 SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage register R2SREG_READ_REG R2 0x15 SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to PFSM storage register R3SREG_READ_REG ADDR=0x077 REG=R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 SREG_WRITE_IMM Command Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 Description: Write the specified data to the scratch register (R0-3) Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth). PFSM Storage Register can be R0, R1, R2, or R3. 'REG=' and 'DATA=' are options. When included, the parameters can be in any order. Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 Description: Write the specified data to the scratch register (R0-3)Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data> Data can be in any literal integer format (decimal, hex, and so forth).PFSM Storage Register can be R0, R1, R2, or R3.'REG=' and 'DATA=' are options. When included, the parameters can be in any order.Examples: SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3 SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2SREG_WRITE_IMM R2 0x15 SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3SREG_WRITE_IMM ADDR=0x077 REG=R3 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 WAIT Command Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed out Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> 'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order. Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1 Type = LOW, HIGH, RISE, or FALL Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay. Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination. Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is met or timed outAssembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout> [DEST=]<Destination> Alternative assembly command: JUMP [DEST=]<Destination> JUMP [DEST=]<Destination>'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order.Condition are listed in #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920. Examples: GPIO1, BUCK1_PG, I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/SLVSEA74920Type = LOW, HIGH, RISE, or FALLTimeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay.Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory.Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID.When using the jump command, the PFSM performs an unconditional jump. The command is be compiled as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is never satisfied and hence always times out. Therefore this command always jumps to the destination.Examples: WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 second WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address when a rise edge is detected at GPIO4, or after 1 secondWAIT GPIO4 RISE 1 s <Destination> 0 WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µsWAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 WAIT Command Conditions COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SEL Condition Name COND_SELCondition NameCOND_SELCondition NameCOND_SELCondition NameCOND_SELCondition Name 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 0 GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 16 LDO1_PG 32 I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 48 LP_STANDBY_SEL 0GPIO1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C916 LDO1_PG LDO1_PG32I2C_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB48 LP_STANDBY_SEL LP_STANDBY_SEL 1 GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 17 LDO2_PG 33 I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 49 N/A 1GPIO2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C917 LDO2_PG LDO2_PG33I2C_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB49N/A 2 GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 18 LDO3_PG 34 I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 50 N/A 2GPIO3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C918 LDO3_PG LDO3_PG34I2C_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB50N/A 3 GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 19 LDO4_PG 35 I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 51 N/A 3GPIO4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C919 LDO4_PG LDO4_PG35I2C_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB51N/A 4 GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 20 PGOOD 36 I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 52 N/A 4GPIO5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C920 PGOOD PGOOD36I2C_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB52N/A 5 GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 21 TWARN_EVENT 37 I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 53 N/A 5GPIO6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C9 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-C417A347-6FAF-4664-9900-C36884A4D9C921TWARN_EVENT37I2C_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB53N/A 6 GPIO7 22 INTERRUPT_PIN 38 I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 54 N/A 6 GPIO7 GPIO722INTERRUPT_PIN38I2C_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB54N/A 7 GPIO8 23 N/A 39 I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB 55 N/A 7 GPIO8 GPIO823 N/A N/A39I2C_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-073C9416-03E5-4473-A579-3C7FA3652ACB55N/A 8 GPIO9 24 N/A 40 SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 56 N/A 8 GPIO9 GPIO924 N/A N/A40SREG0_0#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB756N/A 9 GPIO10 25 N/A 41 SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 57 N/A 9 GPIO10 GPIO1025N/A41SREG0_1#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB757N/A 10 GPIO11 26 N/A 42 SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 58 N/A 10 GPIO11 GPIO1126N/A42SREG0_2#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB758N/A 11 BUCK1_PG 27 N/A 43 SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 59 N/A 11BUCK1_PG27N/A43SREG0_3#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB759N/A 12 BUCK2_PG 28 N/A 44 SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 60 N/A 12BUCK2_PG28N/A44SREG0_4#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB760N/A 13 BUCK3_PG 29 N/A 45 SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 61 N/A 13BUCK3_PG29N/A45SREG0_5#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB761N/A 14 BUCK4_PG 30 N/A 46 SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 62 0 14BUCK4_PG30N/A46SREG0_6#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7620 15 BUCK5_PG(use for EXT_VMON PowerGood) 31 N/A 47 SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 63 1 15 BUCK5_PG(use for EXT_VMON PowerGood) BUCK5_PG(use for EXT_VMON PowerGood)31N/A47SREG0_7#GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7 #GUID-7E4B8711-0499-4448-BFE4-B3A80B168C5B/GUID-F2425724-D866-47A8-8CE9-4FFFAD773FB7631 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIOConditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGERConditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0 DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_IMM Command Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step Description: Delay the execution by a specified time Assembly command: DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay. Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step Description: Delay the execution by a specified timeAssembly command: DELAY_IMM <Delay> DELAY_IMM <Delay> Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63. Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error if the step size is too large or too small to meet the delay.Examples: DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_IMM 100 µs — Delay execution by 100 µs DELAY_IMM 10 ms — Delay execution by 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step DELAY_IMM 100 µs — Delay execution by 100 µsDELAY_IMM 100 µs DELAY_IMM 10 ms — Delay execution by 10 msDELAY_IMM 10 ms DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time stepDELAY_IMM 8 DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 DELAY_SREG Command Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command. Assembly command: DELAY_SREG <PFSM Storage Register> PFSM Storage Register can be R0, R1, R2, or R3. Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from a previous command.Assembly command: DELAY_SREG <PFSM Storage Register> DELAY_SREG <PFSM Storage Register>PFSM Storage Register can be R0, R1, R2, or R3.Examples: DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0 DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0DELAY_SREG R0 TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_SET Command Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory. Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order. Destination is the label where this trigger starts executing. Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger. Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID. Trig_type = LOW, HIGH, RISE, or FALL. IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence. REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again. Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID. Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. Description: Set a trigger destination address for a given input signal or condition. These commands must be defined at the beginning of PFSM configuration memory.Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel> [TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space> 'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any order.Destination is the label where this trigger starts executing.Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in numeric order based on the priority of the trigger.27Trig_Sel is the 'Trigger Name' from the . This 'Trigger Name' is the trigger signal to be associated with the specified TRIG_ID.Trig_type = LOW, HIGH, RISE, or FALL.IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the trigger is activated immediately and can abort a sequence.REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-branching trigger to execute the current sequence again.Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1' indicates the destination address is external and represents a FSM state ID.Examples: TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label. TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label. TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered, start executing at ‘seq1’ label.TRIG_SET seq1 20 GPIO_1 LOW 0 0 TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label.TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 TRIG_MASK Command Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger. Assembly command: TRIG_MASK <Mask value> Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth). Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger, setting a ‘1’ disables (masks) the trigger.Assembly command: TRIG_MASK <Mask value> TRIG_MASK <Mask value>Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth).28Examples: TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0 TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0TRIG_MASK 0x5FF82F0 END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END END Command #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands. END Command Format Bit[3:0] CMD 4 bits Description: Marks the final instruction in a sequential task Fields: CMD: Command opcode (0xC) Assembly command: END #GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 shows the format of the END commands.#GUID-829AAD39-C301-4ED7-A234-62018DE2CD53/X6385 END Command Format Bit[3:0] CMD 4 bits END Command Format Bit[3:0] CMD 4 bits Bit[3:0] Bit[3:0] Bit[3:0] CMD 4 bits CMD CMD 4 bits 4 bitsDescription: Marks the final instruction in a sequential taskFields: CMD: Command opcode (0xC) CMD: Command opcode (0xC) CMD: Command opcode (0xC)Assembly command: END END Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Configuration Memory Organization and Sequence Execution The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under . When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs. The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior. The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state. The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' The configuration memory is loaded from NVM into an SRAM. shows an example configuration memory with only two configured sequences. Configuration Memory Script Example Configuration Memory Script ExampleAs soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under .28When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs.The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior.The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state.28The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state. PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' PFSM Trigger Selections Trigger Name Trigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' Trigger Name Trigger Source Trigger Name Trigger Source Trigger NameTrigger Source IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 0 Always '0' 1 Always '1' IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device. IMMEDIATE_SHUTDOWNAn error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device.immediate shutdown MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). MCU_POWER_ERROROutput failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01'). ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'. ORDERLY_SHUTDOWNAn event which causes MODERATE_ERR_INT = '1'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'. FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'.nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00' SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST. SPMI_WD_BIST_DONECompletion of SPMI WatchDog BIST. ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT. ESM_MCU_ERRORAn event that causes ESM_MCU_RST_INT. WD_ERROR An event that causes WD_RST_INT. WD_ERRORAn event that causes WD_RST_INT. SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10'). SOC_POWER_ERRORSOCOutput failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10').SOC ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT ESM_SOC_ERRORAn event that causes ESM_SOC_RST_INT A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under .NSLEEP2 and NSLEEP1 = '11'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1. WKUP1 1A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1.1 or LP_WKUP1 SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'. SU_ACTIVEA valid On-Request detection when STARTUP_DEST = '11'. B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under .NSLEEP2 and NSLEEP1 = '10'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2. WKUP2A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2.or LP_WKUP2 SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'. SU_MCU_ONLY SU_MCU_ONLYA valid On-Request detection when STARTUP_DEST = '10'. C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . CNSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under .. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under . DNSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under .. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'. SU_STANDBYA valid On-Request detection when STARTUP_DEST = '00'. SU_X A valid On-Request detection when STARTUP_DEST = '01'. SU_XA valid On-Request detection when STARTUP_DEST = '01'. WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . WAIT_TIMEOUTPFSM WAIT command condition timed out. More information regarding the WAIT command can be found under . GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO1Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO. GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO2Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO. GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO3Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO. GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO4Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO. GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO5Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO. GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO6Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO. GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO7Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO. GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO8Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO. GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO9Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO. GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO10Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO. GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. GPIO11Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO. I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_0Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS) I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_1Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS) I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_2Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS) I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_3Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS) I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_4Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS) I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_5Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS) I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_6Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS) I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) I2C_7Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS) SREG0_0 Input detection of bit 0 in PFSM storage register R0 SREG0_0Input detection of bit 0 in PFSM storage register R0 SREG0_1 Input detection of bit 1 in PFSM storage register R0 SREG0_1Input detection of bit 1 in PFSM storage register R0 SREG0_2 Input detection of bit 2 in PFSM storage register R0 SREG0_2Input detection of bit 2 in PFSM storage register R0 SREG0_3 Input detection of bit 3 in PFSM storage register R0 SREG0_3Input detection of bit 3 in PFSM storage register R0 SREG0_4 Input detection of bit 4 in PFSM storage register R0 SREG0_4Input detection of bit 4 in PFSM storage register R0 SREG0_5 Input detection of bit 5 in PFSM storage register R0 SREG0_5Input detection of bit 5 in PFSM storage register R0 SREG0_6 Input detection of bit 6 in PFSM storage register R0 SREG0_6Input detection of bit 6 in PFSM storage register R0 SREG0_7 Input detection of bit 7 in PFSM storage register R0 SREG0_7Input detection of bit 7 in PFSM storage register R0 0 Always '0' 0Always '0' 1 Always '1' 1Always '1' Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Mission State Configuration The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Each power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY The transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in the user defined states. The is used as an example state machine that is defined through the configuration memory using the configuration FSM instructions. Example of a Mission State-Machine Example of a Mission State-MachineEach power state (light blue bubbles in ) defines the ON or OFF state and the sequencing timing of the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority order of these states is as follows: ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY four power states: STANDBY, ACTIVE, MCU ONLY, and DEEP_SLEEP/S2Rthree power states: STANDBY, ACTIVE and RETENTION ACTIVE MCU ONLY DEEP SLEEP/S2R STANDBY ACTIVE MCU ONLY MCU ONLYDEEP SLEEP/S2RSTANDBYThe transitions between each power state is determined by the trigger signals source pre-selected from . These triggers are then placed in the order of priority through the trigger ID assignment of each trigger source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an on-going sequence. The non-error triggers, which are used to enable state transitions during normal device operation, are then placed according to the priority order of the state the device is transitioning to. list the trigger signal sources, in the order of priority, used to define the power states and transitions of the example mission state machine shown in . This table also helps to determine which triggers must be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior. List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 List of Trigger Used in Example Mission State Machine Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R Trigger ID Trigger Signal State Transitions Trigger Masked In Each User Defined Power State Trigger IDTrigger SignalState TransitionsTrigger Masked In Each User Defined Power State STANDBY ACTIVE MCU ONLY DEEP SLEEP / S2R STANDBYACTIVEMCU ONLYDEEP SLEEP / S2R 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 13 TRIGGER_WKUP1 Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 21 Not Used Mask Masked Masked Masked 22 Not Used Mask Masked Masked Masked 23 Not Used Mask Masked Masked Masked 24 Not Used Mask Masked Masked Masked 25 Not Used Mask Masked Masked Masked 26 Not Used Mask Masked Masked Masked 27 Not Used Mask Masked Masked Masked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 0 IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 0IMMEDIATE_SHUTDOWN From any state to SAFE RECOVERY 1 MCU_POWER_ERROR From any state to SAFE RECOVERY 1MCU_POWER_ERROR From any state to SAFE RECOVERY 2 ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 2ORDERLY_SHUTDOWN From any state to SAFE RECOVERY 3 TRIGGER_FORCE_STANDBY From any state to STANDBY or LP_STANDBY Masked 3TRIGGER_FORCE_STANDBYFrom any state to STANDBY or LP_STANDBYMasked 4 WD_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 4WD_ERRORPerform warm reset of all power rails and return to ACTIVE MaskedMaskedMasked 5 ESM_MCU_ERROR Perform warm reset of all power rails and return to ACTIVE Masked Masked Masked 5ESM_MCU_ERRORPerform warm reset of all power rails and return to ACTIVEMaskedMaskedMasked 6 ESM_SOC_ERROR Perform warm reset of power rails in SOC domain and return to ACTIVE Masked Masked Masked 6ESM_SOC_ERRORPerform warm reset of power rails in SOC domain and return to ACTIVEMaskedMaskedMasked 7 WD_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 7WD_ERRORPerform warm reset of all power rails and return to MCU ONLY MaskedMaskedMasked 8 ESM_MCU_ERROR Perform warm reset of all power rails and return to MCU ONLY Masked Masked Masked 8ESM_MCU_ERRORPerform warm reset of all power rails and return to MCU ONLYMaskedMaskedMasked 9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked 9SOC_POWER_ERRORACTIVE to MCU ONLYMaskedMaskedMasked 10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked 10TRIGGER _I2C_1 (self-cleared)Start RUNTIME_BISTMaskedMasked 11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC Function Masked Masked 11TRIGGER_I2C_2 (self-cleared)Enable I2C CRC FunctionMaskedMasked 12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked 12TRIGGER_SU_ACTIVESTANDBY to ACTIVEMaskedMasked 13 TRIGGER_WKUP1 Any State to ACTIVE 13TRIGGER_WKUP1Any State to ACTIVE 14 TRIGGER_A (NSLEEP2&NSLEEP1 = '11') MCU ONLY or DEEP SLEEP/S2R to ACTIVE Masked 14TRIGGER_A (NSLEEP2&NSLEEP1 = '11')MCU ONLY or DEEP SLEEP/S2R to ACTIVEMasked 15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked 15TRIGGER_SU_MCU_ONLYSTANDBY to MCU ONLYMaskedMasked 16 TRIGGER_WKUP2 STANDBY or DEEP SLEEP/S2R to MCU ONLY Masked 16TRIGGER_WKUP2STANDBY or DEEP SLEEP/S2R to MCU ONLYMasked 17 TRIGGER_B (NSLEEP2&NSLEEP1 = '10') ACTIVE or DEEP SLEEP/S2R to MCU ONLY Masked 17TRIGGER_B (NSLEEP2&NSLEEP1 = '10')ACTIVE or DEEP SLEEP/S2R to MCU ONLYMasked 18 TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' ) ACTIVE or MCU ONLY to DEEP SLEEP/S2R Masked Masked 18TRIGGER_D or TRIGGER_C (NSLEEP2 = '0' )ACTIVE or MCU ONLY to DEEP SLEEP/S2RMaskedMasked 19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked 19TRIGGER_I2C_0 (self-cleared)Any state to STANDBYMaskedMasked 20 Always '1' STANDBY to SAFE RECOVERY Mask Masked Masked Masked 20Always '1' STANDBY to SAFE RECOVERYMaskMaskedMaskedMasked 21 Not Used Mask Masked Masked Masked 21 Not UsedMaskMaskedMaskedMasked 22 Not Used Mask Masked Masked Masked 22 Not UsedMaskMaskedMaskedMasked 23 Not Used Mask Masked Masked Masked 23Not UsedMaskMaskedMaskedMasked 24 Not Used Mask Masked Masked Masked 24Not UsedMaskMaskedMaskedMasked 25 Not Used Mask Masked Masked Masked 25Not UsedMaskMaskedMaskedMasked 26 Not Used Mask Masked Masked Masked 26Not UsedMaskMaskedMaskedMasked 27 Not Used Mask Masked Masked Masked 27Not UsedMaskMaskedMaskedMasked 28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0 28-bit TRIG_MASK Value in Hex format:0xFFE4FF8 0xFF18180 0xFF181800xFF012700xFFC9FF0 This is an immediate trigger. When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. This is an immediate trigger.When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes over control of the device power states once this trigger is executed. Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram Pre-Configured Hardware Transitions There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with the combination of hardware input signals and register bits settings. This section provides more detail to these pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to state transitions. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. ON Requests ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests. ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A If one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present. ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button. The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. ON requests are used to switch on the device, which then transitions the device from the STANDBY or the LP_STANDBY to the state specified by STARTUP_DEST[1:0]. or the LP_STANDBYAfter the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as specified in . SLEEP1 and NSLEEP2 signals as specified in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 lists the available ON requests.#GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A ON Requests EVENT MASKABLE COMMENT DEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A EVENT MASKABLE COMMENT DEBOUNCE EVENT MASKABLE COMMENT DEBOUNCE EVENTMASKABLECOMMENTDEBOUNCE nPWRON (pin) Yes Edge sensitive 50 ms ENABLE (pin) Yes Level sensitive 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A RTC ALARM Interrupt Yes N/A RTC TIMER Interrupt Yes N/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A nPWRON (pin) Yes Edge sensitive 50 ms nPWRON (pin) nPWRON (pin)YesEdge sensitive 50 ms 50 ms ENABLE (pin) Yes Level sensitive 8 µs ENABLE (pin) ENABLE (pin)YesLevel sensitive 8 µs 8 µs First Supply Detection (FSD) Yes VCCA > VCCA_UV and FSD unmasked N/A First Supply Detection (FSD)YesVCCA > VCCA_UV and FSD unmaskedN/A RTC ALARM Interrupt Yes N/A RTC ALARM InterruptYesN/A RTC TIMER Interrupt Yes N/A RTC TIMER InterruptYesN/A WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs WKUP1 or WKUP2 Detection1 or WKUP2YesEdge sensitive8 µs LP_WKUP1 or LP_WKUP2 Detection Yes Edge sensitive N/A LP_WKUP1 or LP_WKUP2 DetectionYesEdge sensitiveN/A Recovery from Immediate and Orderly Shutdown No Recover from system errors which caused immediate or orderly shutdown of the device N/A Recovery from Immediate and Orderly ShutdownNoRecover from system errors which caused immediate or orderly shutdown of the deviceN/AIf one of the events listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972 occurs, then the event powers on the device unless one of the gating conditions listed in #GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 is present.#GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA76972#GUID-CF09F512-F01B-4591-9EAD-EE716C2976A4/SLVSEA71946 ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level ON Requests Gating Conditions EVENT MASKABLE COMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level EVENT MASKABLE COMMENT EVENT MASKABLE COMMENT EVENTMASKABLECOMMENT VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level VCCA_OVP (event) No VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_OVP (event)NoVCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA < VCCA_OVP VCCA_OVP VCCA_UVLO (event) No VCCA < VCCA_UVLO VCCA_UVLO (event)NoVCCA < VCCA_UVLO VINT_OVP (event) No LDOVINT > 1.98 V VINT_OVP (event)NoLDOVINT > 1.98 V VINT_UVLO (event) No LDOVINT < 1.62 V VINT_UVLO (event)NoLDOVINT < 1.62 V TSD (event) No Device stays in SAFE RECOVERY until temperature decreases below TWARN level TSD (event)No Device stays in SAFE RECOVERY until temperature decreases below TWARN levelThe NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the nPWRON press button.The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer react to the changing state of the pin as the ENABLE switch. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. OFF Requests An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state. OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state. When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit. #GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 lists the conditions to generate the OFF requests and the corresponding destination state.#GUID-117B0898-2FEC-4E9D-9F33-06019819BC63/SLVSEA7991 OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY OFF Requests EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE EVENT DEBOUNCE LP_STANDBY_SEL BIT SETTING DESTINATION STATE EVENTDEBOUNCELP_STANDBY_SEL BIT SETTINGDESTINATION STATE nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY LP_STANDBY_SEL = 1 LP_STANDBY nPWRON (pin) (long press key event) 8 s LP_STANDBY_SEL = 0 STANDBY nPWRON (pin) (long press key event)8 sLP_STANDBY_SEL = 0STANDBY LP_STANDBY_SEL = 1 LP_STANDBY LP_STANDBY_SEL = 1LP_STANDBY ENABLE (pin) 8 µs LP_STANDBY_SEL = 0 STANDBY ENABLE (pin)8 µsLP_STANDBY_SEL = 0STANDBY LP_STANDBY_SEL = 1 LP_STANDBY LP_STANDBY_SEL = 1LP_STANDBY I2C_TRIGGER_0 NA LP_STANDBY_SEL = 0 STANDBY I2C_TRIGGER_0NALP_STANDBY_SEL = 0STANDBY LP_STANDBY_SEL = 1 LP_STANDBY LP_STANDBY_SEL = 1LP_STANDBYThe long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in a mission state.LPK_TIMEWhen the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request. Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'. NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY NSLEEP1 and NSLEEP2 Functions The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal. A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state. The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1. When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0. The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device. The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states. shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal.11ORA 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from . When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state.The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1.TPS6593-Q1When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0.The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device.The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states.LDOn_CTRL and shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from . NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY NSLEEPn Transitions and Mission State Assignments Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State Current StateNSLEEP1NSLEEP2NSLEEP1 MASKNSLEEP2 MASKTrigger to FSMNext State DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY DEEP SLEEP/S2R 0 0 → 1 0 0 TRIGGER B MCU ONLY DEEP SLEEP/S2R00 → 100TRIGGER BMCU ONLY DEEP SLEEP/S2R 0 → 1 0 → 1 0 0 TRIGGER A ACTIVE DEEP SLEEP/S2R0 → 10 → 100TRIGGER AACTIVE DEEP SLEEP/S2R Don't care 0 → 1 1 0 TRIGGER A ACTIVE DEEP SLEEP/S2RDon't care0 → 110TRIGGER AACTIVE DEEP SLEEP/S2R or MCU ONLY 0 → 1 Don't care 0 1 TRIGGER A ACTIVE DEEP SLEEP/S2R or MCU ONLY0 → 1Don't care01TRIGGER AACTIVE MCU ONLY 0 → 1 1 0 0 TRIGGER A ACTIVE MCU ONLY0 → 1100TRIGGER AACTIVE MCU ONLY 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R MCU ONLY01 → 000TRIGGER DDEEP SLEEP or S2R MCU ONLY Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R MCU ONLYDon't care1 → 010TRIGGER DDEEP SLEEP or S2R ACTIVE 1 → 0 1 0 0 TRIGGER B MCU ONLY ACTIVE1 → 0100TRIGGER BMCU ONLY ACTIVE 1 → 0 1 → 0 0 0 TRIGGER D DEEP SLEEP or S2R ACTIVE1 → 01 → 000TRIGGER DDEEP SLEEP or S2R ACTIVE Don't care 1 → 0 1 0 TRIGGER D DEEP SLEEP or S2R ACTIVEDon't care1 → 010TRIGGER DDEEP SLEEP or S2R ACTIVE 1 → 0 Don't care 0 1 TRIGGER B MCU ONLY ACTIVE1 → 0Don't care01TRIGGER BMCU ONLY WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . WKUP1 and WKUP2 Functions The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in , when a GPIO pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following priority order: ACTIVE MCU ONLY ACTIVE MCU ONLY ACTIVEMCU ONLYWhen a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals as shown in . LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram LP_WKUP Pins for Waking Up from LP STANDBY The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state. The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table. In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4 pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following priority order: ACTIVE MCU ONLY ACTIVE MCU ONLY ACTIVEMCU ONLY Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly wake up the device to the MCU_ONLY state.The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down to the recommenced GPIO input voltage level specified in the electrical characteristics table.TPS6593-Q1WK_PW_MINTPS6593-Q1In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The wake request remains active until the interrupt bit is cleared by the MCU. shows how the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled. illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the internal wake-up signal. CAN Wake-Up Timing Diagram CAN Wake-Up Timing Diagram Error Handling Operations The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Error Handling Operations The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the operation: Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings TPS6593-Q1 Power Rail Output Error Boot BIST Error Runtime BIST Error Catastrophic Error Watchdog Error Error Signal Monitor (ESM) Error Warnings Power Rail Output ErrorBoot BIST ErrorRuntime BIST ErrorCatastrophic ErrorWatchdog ErrorError Signal Monitor (ESM) ErrorWarnings Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Power Rail Output Error A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups. shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled. The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals. The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". A power rail output error occurs when an error condition is detected on the output rails of the device that are used to power the attached MCU or SoC. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. These errors include the following: Rails not reaching or maintaining within the power good voltage level threshold. A short condition that is detected at a regulator output. The load current that exceeds the forward current limit. Rails not reaching or maintaining within the power good voltage level threshold.A short condition that is detected at a regulator output.The load current that exceeds the forward current limit.The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react differently when an error is detected from a power resource assigned to the different rail groups., LDOn_GRP_SEL, LDOs,SoC, or OTHER rail groupTPS6593-Q1 shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0] register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be configured to execute the appropriate error handling sequence for the following error handling sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the device is power-cycled.SOC,, and OTHER_RAIL_TRIG[1:0]Immediate Shutdown Trigger MaskOrderly Shutdown Trigger MaskMCU Power Error Trigger Mask SoC Power Error Trigger MaskSoCimmediate shutdownorderly shutdownMCU power error SOC power errorSOCimmediate shutdown and nRSTOUT_SoC(GPO1 or GPIO11) MCU and SOC and the EN_DRV pin is forced lowThe power resources assigned to the SoC rail group are typically assigned to the SOC power error handling sequence. In this PFSM example depicted in , when a power resource in this group is detected, the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the SoC power up. Refer to for information regarding the setting of the NSLEEP1 and NSLEEP2 signals.(GPO1 or GPIO11) . The EN_DRV pin also remains unchanged,TPS6593-Q1The power resources used for peripheral devices in the system, for which no error-handling action is required, the rail mapping needs to be selected as "no group assigned". Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Catastrophic Error Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. Following errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage, LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence. errors on internal clock signals, error detected on the SPMI bus,Following errors are grouped as severe errors: VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state. VCCA > OVP threshold Junction temperature > immediate shutdown level Error in PFSM Sequence VCCA > OVP thresholdJunction temperature > immediate shutdown levelError in PFSM SequenceFollowing errors are grouped as moderate errors: Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin Junction temperature > orderly shutdown level BIST failure CRC error in register map Recovery counter exceeding the threshold value Error on SPMI bus Readback error on nRSTOUT pin or nINT pin Junction temperature > orderly shutdown levelBIST failureCRC error in register mapRecovery counter exceeding the threshold valueError on SPMI busReadback error on nRSTOUT pin or nINT pinFor these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY state.For following errors, the device performs an immediate shutdown and resets all internal logic circuits: VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM VCCA < UVLO threshold Error on LDOVINT supply Errors on internal clock signals Unrecoverable CRC error in the SRAM memory of the PFSM VCCA < UVLO thresholdError on LDOVINT supplyErrors on internal clock signalsUnrecoverable CRC error in the SRAM memory of the PFSMFor all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. and and the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins the GPIO pin used as (GPO1 or GPIO11)andThe nINT pin is driven low to signal an interrupt event has occurred, and the EN_DRV pin is forced low. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Watchdog (WDOG) Error Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms. Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms.Watchdog (WDOG) Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Warnings Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the device detects the error and handles the error through the interrupt handler. These are errors such as thermal warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the power resources, and the reset outputs remain unchanged. the state of the EN_DRV pin, The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it is handled as a Power Rail Output Error as described in . Device Start-up Timing shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. Device Start-up Timing shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. shows the timing diagram of the TPS6593-Q1 after the first supply detection. Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM. The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details. The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. shows the timing diagram of the TPS6593-Q1 after the first supply detection.TPS6593-Q1 Device Start-up Timing Diagram Device Start-up Timing Diagram tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table. tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table.INIT_REFCLK_LDOINIT_NVM_ANALOGINIT_REFCLK_LDOINIT_NVM_ANALOG BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM.BOOT_BISTLBISTrunThe Power Sequence time is the total time for the device to complete the power up sequence. Please refer to for more details.The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed. and the nRSTOUT_SoC Power Sequences A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. Power Sequences A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins). shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition. A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions. A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources, which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins).TPS6593-Q1, LDOs, 32-kHz clock , 32-kHz clockGeneral-Purpose I/Os (GPIO Pins) shows an example of a power up transition followed by a power down transition. The power up sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request. The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition.BUCK2GPIO1, LDO4,A resource not assigned to any power sequence remains in off mode during the power-up sequence. The attached MCU or SoC can enable and configure this resource independently when the power-up sequence completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no pending interrupt bits). Power Sequence Example Power Sequence ExampleAs the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the total time for the completion of the power sequence varies across various system definitions.TPS6593-Q1 First Supply Detection The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . First Supply Detection The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory. When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in . The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD) event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this feature is loaded into the device memory.TPS6593-Q1, and setting the NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pinWhen the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2 signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2 signals as specified in .NSLEEP1 and NSLEEP2 signalsNSLEEP1 and NSLEEP2 signalsas specified in Register Power Domains and Reset Levels The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT Register Power Domains and Reset Levels The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT The TPS6593-Q1 registers are defined by the following categories: LDOVINT registers LDOVRTC registers (registers in RTC domain) TPS6593-Q1 LDOVINT registers LDOVRTC registers (registers in RTC domain) LDOVINT registersLDOVRTC registers (registers in RTC domain) LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT LDOVINT registers The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT. LDOVINT registersThe LDOVINT registers are powered by the internal LDOVINT, and retain their values until the device enters the LP_STANDBY state or the BACKUP state after the device was fully powered up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including the VSET registers which store the output voltage levels for all of the external power rails) are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain), are powered by LDOVINT.or the BACKUP state LDOVRTC registers (registers in RTC domain) The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT LDOVRTC registers (registers in RTC domain)The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset. Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT Following are the LDOVRTC registers: All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT All RTC registers RTC and Crystal Oscillator bits Status registers for the following events: TSD and RTC reset Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state) Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT All RTC registersRTC and Crystal Oscillator bitsStatus registers for the following events: TSD and RTC resetControl registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor during LP_STANDBY state)Following interrupt registers: FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT FSD_INT RECOV_CNT_INT TSD_ORD_INT TSD_IMM_INT PFSM_ERR_INT VCCA_OVP_INT ESM_MCU_RST_INT ESM_SOC_RST_INT WD_RST_INT WD_LONGWIN_TIMEOUT_INT NPWRON_LONG_INT FSD_INTRECOV_CNT_INTTSD_ORD_INTTSD_IMM_INTPFSM_ERR_INTVCCA_OVP_INTESM_MCU_RST_INTESM_SOC_RST_INTWD_RST_INTWD_LONGWIN_TIMEOUT_INTNPWRON_LONG_INT Multi-PMIC Synchronization A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation SPMI Interface System Setup An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. Transmission Protocol and CRC The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. SPMI Target Device Communication to SPMI Controller Device An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. SPMI-BIST Overview The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) Multi-PMIC Synchronization A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A 20220110 Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes A20220110Changed all instances of legacy terminology into "controller" and "target", also in all sub-sectionsyes yes A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus. Multi-PMIC Power State Synchronization Block Diagram In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip. Multi-PMIC Pin Connections The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required between the application processor or the microcontroller and multiple PMICs in the system. The control interface consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition or power state information. is the block diagram of the power state synchronization scheme. The primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data, and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.TPS6593-Q1controllertarget Multi-PMIC Power State Synchronization Block Diagram Multi-PMIC Power State Synchronization Block DiagramIn this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or SPI interface to find out the source of the error that is reported. To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. illustrates the pin connections between the primary, the secondary, and the application processor or the System-on-Chip.To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the target devices in the SPMI interface bus. TPS6593-Q1 Multi-PMIC Pin Connections Multi-PMIC Pin ConnectionsThe power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation from different PMIC rails is up to ±10% of the target delay time. illustrates the creation of this timing variation between PMICs. Multi-PMIC Rail Sequencing Timing Variation Multi-PMIC Rail Sequencing Timing Variation SPMI Interface System Setup An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. SPMI Interface System Setup An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101. Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health. TPS6593-Q1controllertarget As the SPMI controller it initiates SPMI interface BIST and executes periodic checking of the SPMI bus health.The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary PMIC has a target-ID (TID) = 0101.Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs are: 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 1st target device: 0011 2nd target device: 1100 3rd target device: 1001 4th target device: 0110 5th target device: 1010 1st target device: 00112nd target device: 11003rd target device: 10014th target device: 01105th target device: 1010All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate all power state transition information in broadcast mode to all connected devices on the SPMI bus. Transmission Protocol and CRC The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. Transmission Protocol and CRC The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits. Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device. Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames). shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command The communication between the devices on the network utilizes Extended Register Write command to GTID address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame carries the data payload of 5 bits and 3 filler bits.1111Communication over the SPMI interface may contain information regarding the power state transition or the unique TID of one or more target devices. In the case of power state information, the data payload contains 5 bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of the target device.Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is calculated over the SPMI command frame, the address frame, and the first data frame (which contains the payload and excludes the parity bits in these three frames).82 shows the data format of the SPMI Extended Register Write Command. SPMI Extended Register Write Command SPMI Extended Register Write Command Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Operation with Transmission Errors If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard. If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device. If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/NACK per SPMI standard.If the transmitting device sees NACK response, it tries to resend the message as many times as indicated by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each successful transmission by the device.If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the controller device on the SPMI bus detects a missing target device on the network during the periodic testing of SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has occurred after the retry limit has been exceeded. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. Transmitted Information The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device The SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. The SPMI bus is used to carry two types of information: PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device PFSM Trigger ID between the SPMI controller and target devices TID from SPMI target devices to SPMI controller device PFSM Trigger ID between the SPMI controller and target devicesTID from SPMI target devices to SPMI controller deviceThe SPMI controller device reads the TID of the target devices periodically to check the health of the interface. Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the SPMI network in synchronization. Device interrupts explain reason for the power state transitions. SPMI Target Device Communication to SPMI Controller Device An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. SPMI Target Device Communication to SPMI Controller Device An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID. An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only if there is an internal error that is not SPMI related. The target device initiates the error communication using Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation with multiple target devices requesting error communication at the same time, by using the target arbitration process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the protocol described in for communicating PFSM trigger ID.1111 Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. Incomplete Communication from SPMI Target Device to SPMI Controller Device In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation. SPMI-BIST Overview The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) SPMI-BIST Overview The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor. A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state. The SPMI-BIST is performed during BIST state and regularly during runtime operation. below illustrates how the SPMI-BIST operates during device power-up. SPMI-BIST Operation SPMI-BIST OperationAfter the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor.TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-Q1 enters the configured mission state.TPS6593-Q1 SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. SPMI Bus during Boot BIST and RUNTIME BIST During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC. The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of target devices. This process of checking the TID of each target device ensures that: All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order All SPMI target devices are present in the system as expected The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices The pins and wires on the ICs and PCB are in working order All SPMI target devices are present in the system as expectedThe SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devicesThe pins and wires on the ICs and PCB are in working orderThe SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the SPMI target block of the primary PMIC.The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on the SPMI Bus. Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . Periodic Checking of the SPMI The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device. During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval. During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error. If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating. The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor 1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target device.During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the TID request within the factory-configured polling time-out period . In other words, from the polling start command each SPMI target device must respond within this factory-configured time interval.During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from polling the SPMI target devices too often while one or more of these recovering from a system error such as a thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond to the SPMI controller device before he SPMI controller device reports an error.If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown if one or more devices on the SPMI bus cause a violating of the polling time-out period . SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) SPMI Message Priorities The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message. SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) The SPMI Bus uses the protocol priority levels listed in #GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 for each type of communication message.#GUID-F91E50E4-0CEA-4F17-B748-4E3A03F33999/SLVSE824332 SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) SPMI Message Types and Priorities SPMI protocol priority level Name of priority level in SPMI standard Message types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) SPMI protocol priority level Name of priority level in SPMI standard Message types SPMI protocol priority level Name of priority level in SPMI standard Message types SPMI protocol priority levelName of priority level in SPMI standardMessage types Highest A-bit arbitration State transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) Highest A-bit arbitration State transition messages from target device(s) to controller device HighestA-bit arbitrationState transition messages from target device(s) to controller device priority arbitration State transition messages from controller device to target device(s) priority arbitrationState transition messages from controller device to target device(s) SR-bit arbitration target device TID to controller device SR-bit arbitrationtarget device TID to controller device Lowest secondary arbitration Controller device request of TIDs from target device(s) Lowestsecondary arbitrationController device request of TIDs from target device(s) Control Interfaces A 20220110 For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . CRC Calculation for I²C and SPI Interface Protocols A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1. For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1. and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) I²C-Compatible Interface The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram Start and Stop Conditions The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK Serial Peripheral Interface (SPI) The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. Control Interfaces A 20220110 For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes A 20220110 For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes A 20220110 For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes A20220110For I2C, changed all instances of legacy terminology into "controller" and "target". For SPI, changed all instances of legacy terminology into "controller" and "peripheral". For the CRC, changed all instances of legacy terminology into "CRC on received data (R_CRC)", and "CRC on transmitted data" (T_CRC). These changes also applies to all sub-sections.yes yes The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide of the orderable part number which option has been selected. The first selection is up to two high-speed I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the configuration registers and Watchdog registers. During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. . up to two 2s1During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. .212 CRC Calculation for I²C and SPI Interface Protocols A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1. For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1. and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) CRC Calculation for I²C and SPI Interface Protocols2 A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes A 20220110 Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes A20220110Corrected figure on Calculation of 8-Bit Controller CRC (R_CRC) Output, corrected figure on Calculation of 8-Bit Target CRC (T_CRC) Inputyes yes For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1. For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1. and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1. For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1. and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC algorithm details are as follows: Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied TPS6593-Q1TPS6593-Q182 Initial value for the remainder is all 1s Big-endian bit stream order Result inversion is not applied Initial value for the remainder is all 1sBig-endian bit stream orderResult inversion is not appliedFor I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives, except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC checksum value that it receives from the TPS6593-Q1.2TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16 bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1.TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1TPS6593-Q1 and are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus. Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Received Data (R_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) Calculation of 8-Bit CRC on Transmitted Data (T_CRC) I²C-Compatible Interface The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram Start and Stop Conditions The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK I²C-Compatible Interface2 The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under . The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC. 2TPS6593-Q1TPS6593-Q1The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC.2TPS6593-Q1 The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V. The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a controller or a target depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.2 Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. Data Validity Diagram Data Validity Diagram Start and Stop Conditions The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing Start and Stop Conditions The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. I²C-Compatible Timing The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device always generates the START and STOP conditions.222 Start and Stop Sequences Start and Stop SequencesThe I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section. 222Specification I²C-Compatible Timing I²C-Compatible Timing2 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down. After the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit. When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit. I²C Write Cycle without CRC I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received.There is one exception to the acknowledge after every byte rule. When the controller device is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse (generated by the controller device), but the SDA line is not pulled down.acknowledge after every bytenegative acknowledgenegative acknowledgeAfter the START condition, the bus controller device sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. shows an example bit format of device address 110000-Bin = 60Hex. Example Device Address Example Device AddressFor safety applications, the device supports read and write protocols with embedded CRC data fields. In a write cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation for I2C and SPI Interface Protocols.If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low. 2TPS6593-Q12If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not process the write request. The device does not set any interrupt bit and does not pull the nINT pin low.The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.I2C1_SPI_CRC_ENIn case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected, the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit.2COMM_CRC_ERR_INTCOMM_CRC_ERR_MASKCOMM_CRC_ERR_INTWhen the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT bit.COMM_ADR_ERR_INTCOMM_ADR_ERR_MASKCOMM_ADR_ERR_INT I²C Write Cycle without CRC I²C Write Cycle without CRC2 I²C Write Cycle with CRC The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C Write Cycle with CRC2The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits). See CRC Calculation for I2C and SPI Interface Protocols.2 I²C Read Cycle without CRC When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C Read Cycle without CRC2When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. I²C READ Cycle with CRC The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. I²C READ Cycle with CRC2The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols. 2TPS6593-Q1 Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol. Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is written. #GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 lists the writing sequence to two consecutive registers. Note that auto increment feature does not support CRC protocol.#GUID-9513D4D5-9FCE-433D-8352-4E7C139123AC/SNVSA484054 Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK Auto-Increment Example ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP PMIC device ACK ACK ACK ACK ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP ACTION START DEVICE ADDRESS = 0x60 WRITE REGISTER ADDRESS DATA DATA STOP ACTIONSTARTDEVICE ADDRESS = 0x60WRITEREGISTER ADDRESSDATADATASTOP PMIC device ACK ACK ACK ACK PMIC device ACK ACK ACK ACK PMIC deviceACKACKACKACK Serial Peripheral Interface (SPI) The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. Serial Peripheral Interface (SPI) The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM. The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly. The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal. The SPI Timing diagram shows the timing information for these signals. SPI Write Cycle SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle with CRC Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin. The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order: Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . Bits 1-8: ADDR[7:0], Register address Bits 9-11: PAGE[2:0], Page address for register Bit 12: Read/Write definition, 0 = WRITE, 1 = READ. Bits 13-16: RESERVED[4:0], Reserved, use all zeros. For Write: Bits 17-24: WDATA[7:0], write data For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See . For Read: Bits 17-24: RDATA[7:0], read data For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See . Bits 1-8: ADDR[7:0], Register addressBits 9-11: PAGE[2:0], Page address for registerBit 12: Read/Write definition, 0 = WRITE, 1 = READ.Bits 13-16: RESERVED[4:0], Reserved, use all zeros.For Write: Bits 17-24: WDATA[7:0], write dataFor Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (the MCU). See .For Read: Bits 17-24: RDATA[7:0], read dataFor Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See .TPS6593-Q1The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO output is driven accordingly.SDOCSCSSDOSDOThe address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the falling edge of SCLK clock signal.CSCSSCLKSCLKThe SPI Timing diagram shows the timing information for these signals. SPI Timing SPI Write Cycle SPI Write Cycle SPI Write Cycle with CRC SPI Write Cycle with CRC SPI Read Cycle SPI Read Cycle SPI Read Cycle with CRC SPI Read Cycle with CRCDue to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high after completion of the device power-up sequence. After system start-up, the MCU must clear this COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin.TPS6593-Q1TPS6593-Q1 Configurable Registers Register Page Partitioning A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses. When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 CRC Protection for Configuration, Control, and Test Registers The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. . The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1. The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. CRC Protection for User Registers A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM. After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion. The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance. If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h. Register Write Protection For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections. Watchdog and ESM Configuration Registers The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) User Registers User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. Configurable Registers Register Page Partitioning A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses. When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 Register Page Partitioning A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes A 20220110 Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes A20220110Added note which explains the I2C addresses for each register map page on the I2C bus. Added note which explains how each register map page is addressed when using SPI.yes 22yes The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses. When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses. When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different type of register. The below list shows the pages with their register types: Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers TPS6593-Q1 Page 0: User Registers Page 1: NVM Control, Configuration, and Test Registers Page 2: Trim Registers Page 3: SRAM for PFSM Registers Page 4: Watchdog Registers Page 0: User RegistersPage 1: NVM Control, Configuration, and Test RegistersPage 2: Trim RegistersPage 3: SRAM for PFSM RegistersPage 4: Watchdog RegistersWhen I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26 (0100110b) , Page 0 to 3 have following addresses: Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1 and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page 0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses.2201001 Page 0: 0100100 Page 1: 0100101 Page 2: 0100110 Page 3: 0100111 Page 0: 010010001001Page 1: 010010101001Page 2: 010011001001Page 3: 010011101001222TPS6593-Q122222TPS6593-Q12222When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits: 0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3 CRC Protection for Configuration, Control, and Test Registers The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. . The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1. The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. CRC Protection for Configuration, Control, and Test Registers The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. . The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1. The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. . The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1. The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. .TPS6593-Q1TPS6593-Q1The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1.16141312108643The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. CRC Protection for User Registers A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM. After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion. The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance. If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h. CRC Protection for User Registers A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes A 20220110 Added note about writing to RESERVED bits causing a Register Map CRC erroryes A20220110Added note about writing to RESERVED bits causing a Register Map CRC erroryes yes At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM. After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion. The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance. If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h. At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM. After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion. The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance. If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h. At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as described in , and compares the calculated CRC-16 values against the reference CRC-16 values read from the NVM.TPS6593-Q1TPS6593-Q1 After power-up, the content of these User Registers can change due to a write-access through an I2C or SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in the accessed segment before the update to confirm that the data in the access segment before the update is still correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with the new data inserted at the intended register address. If the checksum on the current data before the update is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum value are continuously computed and verified in a round-robin fashion.TPS6593-Q1The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming distance.8632If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the word RESERVED in the Register Field Description tables in the Register Map section at 0h.TPS6593-Q1TPS6593-Q1 Register Write Protection For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections. Watchdog and ESM Configuration Registers The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) User Registers User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. Register Write Protection For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections. For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections. For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device implements locking and unlocking mechanisms to many of its configuration/control registers described in the following subsections.TPS6593-Q1 Watchdog and ESM Configuration Registers The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) Watchdog and ESM Configuration Registersand ESM The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in operation. The locking mechanism and the list of the locked watchdog register is described under . The locking mechanism and the list of the locked ESM registers is described under and the ESM The locking mechanism and the list of the locked ESM registers is described under Error Signal Monitor (ESM) User Registers User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. User Registers User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically. User registers in page 0, except the ESM and the WDOG configuration registers described in , and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any value other than '0x9B' activates the lock again. To check the register lock status, user must read the REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically.the ESM and , waking up from LP_STANDBY Register Maps A 20220314 Corrected description of register DEV_REVyes A 20220314 Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes TPS6593-Q1 Registers lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in . Return to the Summary Table. DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in . Return to the Summary Table. NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in . Return to the Summary Table. NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in . Return to the Summary Table. BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in . Return to the Summary Table. BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in . Return to the Summary Table. BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in . Return to the Summary Table. BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in . Return to the Summary Table. BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in . Return to the Summary Table. BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in . Return to the Summary Table. BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in . Return to the Summary Table. BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in . Return to the Summary Table. BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in . Return to the Summary Table. BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in . Return to the Summary Table. LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in . Return to the Summary Table. LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in . Return to the Summary Table. LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in . Return to the Summary Table. LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in . Return to the Summary Table. LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in . Return to the Summary Table. LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in . Return to the Summary Table. LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in . Return to the Summary Table. LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in . Return to the Summary Table. LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in . Return to the Summary Table. VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in . Return to the Summary Table. VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in . Return to the Summary Table. GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in . Return to the Summary Table. GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in . Return to the Summary Table. GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in . Return to the Summary Table. GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in . Return to the Summary Table. GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in . Return to the Summary Table. GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in . Return to the Summary Table. GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in . Return to the Summary Table. GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in . Return to the Summary Table. GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in . Return to the Summary Table. GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in . Return to the Summary Table. GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in . Return to the Summary Table. NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in . Return to the Summary Table. GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in . Return to the Summary Table. GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in . Return to the Summary Table. GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in . Return to the Summary Table. GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in . Return to the Summary Table. RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in . Return to the Summary Table. RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in . Return to the Summary Table. RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in . Return to the Summary Table. MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in . Return to the Summary Table. MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in . Return to the Summary Table. MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in . Return to the Summary Table. MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in . Return to the Summary Table. MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in . Return to the Summary Table. MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in . Return to the Summary Table. MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in . Return to the Summary Table. MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in . Return to the Summary Table. MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in . Return to the Summary Table. MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in . Return to the Summary Table. MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in . Return to the Summary Table. MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in . Return to the Summary Table. MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in . Return to the Summary Table. MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in . Return to the Summary Table. INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in . Return to the Summary Table. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in . Return to the Summary Table. INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in . Return to the Summary Table. INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in . Return to the Summary Table. INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in . Return to the Summary Table. INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in . Return to the Summary Table. INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in . Return to the Summary Table. INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in . Return to the Summary Table. INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in . Return to the Summary Table. INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in . Return to the Summary Table. INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in . Return to the Summary Table. INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in . Return to the Summary Table. INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in . Return to the Summary Table. INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in . Return to the Summary Table. INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in . Return to the Summary Table. INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in . Return to the Summary Table. INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in . Return to the Summary Table. INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in . Return to the Summary Table. INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in . Return to the Summary Table. STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in . Return to the Summary Table. STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in . Return to the Summary Table. STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in . Return to the Summary Table. STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in . Return to the Summary Table. STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in . Return to the Summary Table. STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in . Return to the Summary Table. STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in . Return to the Summary Table. STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in . Return to the Summary Table. STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in . Return to the Summary Table. STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in . Return to the Summary Table. STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in . Return to the Summary Table. PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in . Return to the Summary Table. PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in . Return to the Summary Table. PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in . Return to the Summary Table. PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in . Return to the Summary Table. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in . Return to the Summary Table. CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in . Return to the Summary Table. CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in . Return to the Summary Table. ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in . Return to the Summary Table. MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in . Return to the Summary Table. ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in . Return to the Summary Table. BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in . Return to the Summary Table. SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in . Return to the Summary Table. FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in . Return to the Summary Table. FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in . Return to the Summary Table. USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in . Return to the Summary Table. ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in . Return to the Summary Table. ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in . Return to the Summary Table. REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in . Return to the Summary Table. MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in . Return to the Summary Table. CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in . Return to the Summary Table. SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in . Return to the Summary Table. RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in . Return to the Summary Table. RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in . Return to the Summary Table. RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in . Return to the Summary Table. RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in . Return to the Summary Table. RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in . Return to the Summary Table. RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in . Return to the Summary Table. RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in . Return to the Summary Table. ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in . Return to the Summary Table. ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in . Return to the Summary Table. ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in . Return to the Summary Table. ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in . Return to the Summary Table. ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in . Return to the Summary Table. ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in . Return to the Summary Table. RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in . Return to the Summary Table. RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in . Return to the Summary Table. RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in . Return to the Summary Table. RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in . Return to the Summary Table. RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in . Return to the Summary Table. RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in . Return to the Summary Table. RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in . Return to the Summary Table. WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in . Return to the Summary Table. WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in . Return to the Summary Table. WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in . Return to the Summary Table. WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in . Return to the Summary Table. WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in . Return to the Summary Table. WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in . Return to the Summary Table. WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in . Return to the Summary Table. WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in . Return to the Summary Table. WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in . Return to the Summary Table. WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. Register Maps A 20220314 Corrected description of register DEV_REVyes A 20220314 Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes A 20220314 Corrected description of register DEV_REVyes A 20220314 Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes A 20220314 Corrected description of register DEV_REVyes A20220314Corrected description of register DEV_REVyes yes A 20220314 Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes A20220314Changed bit 7 to RESERVED in registers BUCK1_CTRL, BUCK2_CTRL, BUCK3_CTRL, BUCK4_CTRL, BUCK5_CTRL, LDO1_CTRL, LDO2_CTRL, LDO3_CTRL and LDO4_CTRLyes yes TPS6593-Q1 Registers lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in . Return to the Summary Table. DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in . Return to the Summary Table. NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in . Return to the Summary Table. NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in . Return to the Summary Table. BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in . Return to the Summary Table. BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in . Return to the Summary Table. BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in . Return to the Summary Table. BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in . Return to the Summary Table. BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in . Return to the Summary Table. BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in . Return to the Summary Table. BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in . Return to the Summary Table. BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in . Return to the Summary Table. BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in . Return to the Summary Table. BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in . Return to the Summary Table. LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in . Return to the Summary Table. LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in . Return to the Summary Table. LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in . Return to the Summary Table. LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in . Return to the Summary Table. LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in . Return to the Summary Table. LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in . Return to the Summary Table. LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in . Return to the Summary Table. LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in . Return to the Summary Table. LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in . Return to the Summary Table. VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in . Return to the Summary Table. VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in . Return to the Summary Table. GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in . Return to the Summary Table. GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in . Return to the Summary Table. GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in . Return to the Summary Table. GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in . Return to the Summary Table. GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in . Return to the Summary Table. GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in . Return to the Summary Table. GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in . Return to the Summary Table. GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in . Return to the Summary Table. GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in . Return to the Summary Table. GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in . Return to the Summary Table. GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in . Return to the Summary Table. NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in . Return to the Summary Table. GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in . Return to the Summary Table. GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in . Return to the Summary Table. GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in . Return to the Summary Table. GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in . Return to the Summary Table. RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in . Return to the Summary Table. RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in . Return to the Summary Table. RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in . Return to the Summary Table. MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in . Return to the Summary Table. MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in . Return to the Summary Table. MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in . Return to the Summary Table. MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in . Return to the Summary Table. MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in . Return to the Summary Table. MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in . Return to the Summary Table. MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in . Return to the Summary Table. MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in . Return to the Summary Table. MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in . Return to the Summary Table. MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in . Return to the Summary Table. MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in . Return to the Summary Table. MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in . Return to the Summary Table. MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in . Return to the Summary Table. MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in . Return to the Summary Table. INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in . Return to the Summary Table. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in . Return to the Summary Table. INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in . Return to the Summary Table. INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in . Return to the Summary Table. INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in . Return to the Summary Table. INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in . Return to the Summary Table. INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in . Return to the Summary Table. INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in . Return to the Summary Table. INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in . Return to the Summary Table. INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in . Return to the Summary Table. INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in . Return to the Summary Table. INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in . Return to the Summary Table. INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in . Return to the Summary Table. INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in . Return to the Summary Table. INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in . Return to the Summary Table. INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in . Return to the Summary Table. INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in . Return to the Summary Table. INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in . Return to the Summary Table. INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in . Return to the Summary Table. STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in . Return to the Summary Table. STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in . Return to the Summary Table. STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in . Return to the Summary Table. STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in . Return to the Summary Table. STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in . Return to the Summary Table. STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in . Return to the Summary Table. STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in . Return to the Summary Table. STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in . Return to the Summary Table. STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in . Return to the Summary Table. STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in . Return to the Summary Table. STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in . Return to the Summary Table. PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in . Return to the Summary Table. PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in . Return to the Summary Table. PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in . Return to the Summary Table. PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in . Return to the Summary Table. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in . Return to the Summary Table. CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in . Return to the Summary Table. CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in . Return to the Summary Table. ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in . Return to the Summary Table. MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in . Return to the Summary Table. ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in . Return to the Summary Table. BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in . Return to the Summary Table. SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in . Return to the Summary Table. FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in . Return to the Summary Table. FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in . Return to the Summary Table. USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in . Return to the Summary Table. ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in . Return to the Summary Table. ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in . Return to the Summary Table. REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in . Return to the Summary Table. MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in . Return to the Summary Table. CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in . Return to the Summary Table. SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in . Return to the Summary Table. RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in . Return to the Summary Table. RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in . Return to the Summary Table. RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in . Return to the Summary Table. RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in . Return to the Summary Table. RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in . Return to the Summary Table. RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in . Return to the Summary Table. RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in . Return to the Summary Table. ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in . Return to the Summary Table. ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in . Return to the Summary Table. ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in . Return to the Summary Table. ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in . Return to the Summary Table. ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in . Return to the Summary Table. ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in . Return to the Summary Table. RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in . Return to the Summary Table. RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in . Return to the Summary Table. RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in . Return to the Summary Table. RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in . Return to the Summary Table. RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in . Return to the Summary Table. RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in . Return to the Summary Table. RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in . Return to the Summary Table. WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in . Return to the Summary Table. WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in . Return to the Summary Table. WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in . Return to the Summary Table. WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in . Return to the Summary Table. WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in . Return to the Summary Table. WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in . Return to the Summary Table. WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in . Return to the Summary Table. WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in . Return to the Summary Table. WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in . Return to the Summary Table. WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. TPS6593-Q1 Registers lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in . Return to the Summary Table. DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in . Return to the Summary Table. NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in . Return to the Summary Table. NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in . Return to the Summary Table. BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in . Return to the Summary Table. BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in . Return to the Summary Table. BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in . Return to the Summary Table. BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in . Return to the Summary Table. BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in . Return to the Summary Table. BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in . Return to the Summary Table. BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in . Return to the Summary Table. BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in . Return to the Summary Table. BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in . Return to the Summary Table. BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in . Return to the Summary Table. LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in . Return to the Summary Table. LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in . Return to the Summary Table. LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in . Return to the Summary Table. LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in . Return to the Summary Table. LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in . Return to the Summary Table. LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in . Return to the Summary Table. LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in . Return to the Summary Table. LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in . Return to the Summary Table. LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in . Return to the Summary Table. VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in . Return to the Summary Table. VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in . Return to the Summary Table. GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in . Return to the Summary Table. GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in . Return to the Summary Table. GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in . Return to the Summary Table. GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in . Return to the Summary Table. GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in . Return to the Summary Table. GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in . Return to the Summary Table. GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in . Return to the Summary Table. GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in . Return to the Summary Table. GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in . Return to the Summary Table. GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in . Return to the Summary Table. GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in . Return to the Summary Table. NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in . Return to the Summary Table. GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in . Return to the Summary Table. GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in . Return to the Summary Table. GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in . Return to the Summary Table. GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in . Return to the Summary Table. RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in . Return to the Summary Table. RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in . Return to the Summary Table. RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in . Return to the Summary Table. MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in . Return to the Summary Table. MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in . Return to the Summary Table. MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in . Return to the Summary Table. MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in . Return to the Summary Table. MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in . Return to the Summary Table. MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in . Return to the Summary Table. MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in . Return to the Summary Table. MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in . Return to the Summary Table. MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in . Return to the Summary Table. MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in . Return to the Summary Table. MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in . Return to the Summary Table. MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in . Return to the Summary Table. MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in . Return to the Summary Table. MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in . Return to the Summary Table. INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in . Return to the Summary Table. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in . Return to the Summary Table. INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in . Return to the Summary Table. INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in . Return to the Summary Table. INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in . Return to the Summary Table. INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in . Return to the Summary Table. INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in . Return to the Summary Table. INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in . Return to the Summary Table. INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in . Return to the Summary Table. INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in . Return to the Summary Table. INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in . Return to the Summary Table. INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in . Return to the Summary Table. INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in . Return to the Summary Table. INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in . Return to the Summary Table. INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in . Return to the Summary Table. INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in . Return to the Summary Table. INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in . Return to the Summary Table. INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in . Return to the Summary Table. INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in . Return to the Summary Table. STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in . Return to the Summary Table. STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in . Return to the Summary Table. STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in . Return to the Summary Table. STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in . Return to the Summary Table. STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in . Return to the Summary Table. STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in . Return to the Summary Table. STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in . Return to the Summary Table. STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in . Return to the Summary Table. STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in . Return to the Summary Table. STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in . Return to the Summary Table. STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in . Return to the Summary Table. PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in . Return to the Summary Table. PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in . Return to the Summary Table. PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in . Return to the Summary Table. PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in . Return to the Summary Table. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in . Return to the Summary Table. CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in . Return to the Summary Table. CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in . Return to the Summary Table. ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in . Return to the Summary Table. MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in . Return to the Summary Table. ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in . Return to the Summary Table. BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in . Return to the Summary Table. SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in . Return to the Summary Table. FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in . Return to the Summary Table. FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in . Return to the Summary Table. USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in . Return to the Summary Table. ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in . Return to the Summary Table. ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in . Return to the Summary Table. REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in . Return to the Summary Table. MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in . Return to the Summary Table. CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in . Return to the Summary Table. SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in . Return to the Summary Table. RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in . Return to the Summary Table. RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in . Return to the Summary Table. RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in . Return to the Summary Table. RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in . Return to the Summary Table. RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in . Return to the Summary Table. RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in . Return to the Summary Table. RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in . Return to the Summary Table. ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in . Return to the Summary Table. ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in . Return to the Summary Table. ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in . Return to the Summary Table. ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in . Return to the Summary Table. ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in . Return to the Summary Table. ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in . Return to the Summary Table. RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in . Return to the Summary Table. RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in . Return to the Summary Table. RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in . Return to the Summary Table. RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in . Return to the Summary Table. RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in . Return to the Summary Table. RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in . Return to the Summary Table. RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in . Return to the Summary Table. WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in . Return to the Summary Table. WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in . Return to the Summary Table. WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in . Return to the Summary Table. WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in . Return to the Summary Table. WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in . Return to the Summary Table. WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in . Return to the Summary Table. WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in . Return to the Summary Table. WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in . Return to the Summary Table. WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in . Return to the Summary Table. WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG TPS6593-Q1 Registers Offset Acronym Register Name Section 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 1h DEV_REV 2h NVM_CODE_1 3h NVM_CODE_2 4h BUCK1_CTRL 5h BUCK1_CONF 6h BUCK2_CTRL 7h BUCK2_CONF 8h BUCK3_CTRL 9h BUCK3_CONF Ah BUCK4_CTRL Bh BUCK4_CONF Ch BUCK5_CTRL Dh BUCK5_CONF Eh BUCK1_VOUT_1 Fh BUCK1_VOUT_2 10h BUCK2_VOUT_1 11h BUCK2_VOUT_2 12h BUCK3_VOUT_1 13h BUCK3_VOUT_2 14h BUCK4_VOUT_1 15h BUCK4_VOUT_2 16h BUCK5_VOUT_1 17h BUCK5_VOUT_2 18h BUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1Dh LDO1_CTRL 1Eh LDO2_CTRL 1Fh LDO3_CTRL 20h LDO4_CTRL 22h LDORTC_CTRL 23h LDO1_VOUT 24h LDO2_VOUT 25h LDO3_VOUT 26h LDO4_VOUT 27h LDO1_PG_WINDOW 28h LDO2_PG_WINDOW 29h LDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 31h GPIO1_CONF 32h GPIO2_CONF 33h GPIO3_CONF 34h GPIO4_CONF 35h GPIO5_CONF 36h GPIO6_CONF 37h GPIO7_CONF 38h GPIO8_CONF 39h GPIO9_CONF 3Ah GPIO10_CONF 3Bh GPIO11_CONF 3Ch NPWRON_CONF 3Dh GPIO_OUT_1 3Eh GPIO_OUT_2 3Fh GPIO_IN_1 40h GPIO_IN_2 41h RAIL_SEL_1 42h RAIL_SEL_2 43h RAIL_SEL_3 44h FSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 49h MASK_BUCK1_2 4Ah MASK_BUCK3_4 4Bh MASK_BUCK5 4Ch MASK_LDO1_2 4Dh MASK_LDO3_4 4Eh MASK_VMON 4Fh MASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 51h MASK_GPIO9_11 52h MASK_STARTUP 53h MASK_MISC 54h MASK_MODERATE_ERR 56h MASK_FSM_ERR 57h MASK_COMM_ERR 58h MASK_READBACK_ERR 59h MASK_ESM 5Ah INT_TOP 5Bh INT_BUCK 5Ch INT_BUCK1_2 5Dh INT_BUCK3_4 5Eh INT_BUCK5 5Fh INT_LDO_VMON 60h INT_LDO1_2 61h INT_LDO3_4 62h INT_VMON 63h INT_GPIO 64h INT_GPIO1_8 65h INT_STARTUP 66h INT_MISC 67h INT_MODERATE_ERR 68h INT_SEVERE_ERR 69h INT_FSM_ERR 6Ah INT_COMM_ERR 6Bh INT_READBACK_ERR 6Ch INT_ESM 6Dh STAT_BUCK1_2 6Eh STAT_BUCK3_4 6Fh STAT_BUCK5 70h STAT_LDO1_2 71h STAT_LDO3_4 72h STAT_VMON 73h STAT_STARTUP 74h STAT_MISC 75h STAT_MODERATE_ERR 76h STAT_SEVERE_ERR 77h STAT_READBACK_ERR 78h PGOOD_SEL_1 79h PGOOD_SEL_2 7Ah PGOOD_SEL_3 7Bh PGOOD_SEL_4 7Ch PLL_CTRL 7Dh CONFIG_1 7Eh CONFIG_2 80h ENABLE_DRV_REG 81h MISC_CTRL 82h ENABLE_DRV_STAT 83h RECOV_CNT_REG_1 84h RECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 88h SPREAD_SPECTRUM_1 8Ah FREQ_SEL 8Bh FSM_STEP_SIZE 8Eh USER_SPARE_REGS 8Fh ESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A6h MANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG B5h RTC_SECONDS B6h RTC_MINUTES B7h RTC_HOURS B8h RTC_DAYS B9h RTC_MONTHS BAh RTC_YEARS BBh RTC_WEEKS BCh ALARM_SECONDS BDh ALARM_MINUTES BEh ALARM_HOURS BFh ALARM_DAYS C0h ALARM_MONTHS C1h ALARM_YEARS C2h RTC_CTRL_1 C3h RTC_CTRL_2 C4h RTC_STATUS C5h RTC_INTERRUPTS C6h RTC_COMP_LSB C7h RTC_COMP_MSB C8h RTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 401h WD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 404h WD_WIN2_CFG 405h WD_LONGWIN_CFG 406h WD_MODE_REG 407h WD_QA_CFG 408h WD_ERR_STATUS 409h WD_THR_CFG 40Ah WD_FAIL_CNT_REG 1h DEV_REV 1hDEV_REV 2h NVM_CODE_1 2hNVM_CODE_1 3h NVM_CODE_2 3hNVM_CODE_2 4h BUCK1_CTRL 4hBUCK1_CTRL 5h BUCK1_CONF 5hBUCK1_CONF 6h BUCK2_CTRL 6hBUCK2_CTRL 7h BUCK2_CONF 7hBUCK2_CONF 8h BUCK3_CTRL 8hBUCK3_CTRL 9h BUCK3_CONF 9hBUCK3_CONF Ah BUCK4_CTRL AhBUCK4_CTRL Bh BUCK4_CONF BhBUCK4_CONF Ch BUCK5_CTRL ChBUCK5_CTRL Dh BUCK5_CONF DhBUCK5_CONF Eh BUCK1_VOUT_1 EhBUCK1_VOUT_1 Fh BUCK1_VOUT_2 FhBUCK1_VOUT_2 10h BUCK2_VOUT_1 10hBUCK2_VOUT_1 11h BUCK2_VOUT_2 11hBUCK2_VOUT_2 12h BUCK3_VOUT_1 12hBUCK3_VOUT_1 13h BUCK3_VOUT_2 13hBUCK3_VOUT_2 14h BUCK4_VOUT_1 14hBUCK4_VOUT_1 15h BUCK4_VOUT_2 15hBUCK4_VOUT_2 16h BUCK5_VOUT_1 16hBUCK5_VOUT_1 17h BUCK5_VOUT_2 17hBUCK5_VOUT_2 18h BUCK1_PG_WINDOW 18hBUCK1_PG_WINDOW 19h BUCK2_PG_WINDOW 19hBUCK2_PG_WINDOW 1Ah BUCK3_PG_WINDOW 1AhBUCK3_PG_WINDOW 1Bh BUCK4_PG_WINDOW 1BhBUCK4_PG_WINDOW 1Ch BUCK5_PG_WINDOW 1ChBUCK5_PG_WINDOW 1Dh LDO1_CTRL 1DhLDO1_CTRL 1Eh LDO2_CTRL 1EhLDO2_CTRL 1Fh LDO3_CTRL 1FhLDO3_CTRL 20h LDO4_CTRL 20hLDO4_CTRL 22h LDORTC_CTRL 22hLDORTC_CTRL 23h LDO1_VOUT 23hLDO1_VOUT 24h LDO2_VOUT 24hLDO2_VOUT 25h LDO3_VOUT 25hLDO3_VOUT 26h LDO4_VOUT 26hLDO4_VOUT 27h LDO1_PG_WINDOW 27hLDO1_PG_WINDOW 28h LDO2_PG_WINDOW 28hLDO2_PG_WINDOW 29h LDO3_PG_WINDOW 29hLDO3_PG_WINDOW 2Ah LDO4_PG_WINDOW 2AhLDO4_PG_WINDOW 2Bh VCCA_VMON_CTRL 2BhVCCA_VMON_CTRL 2Ch VCCA_PG_WINDOW 2ChVCCA_PG_WINDOW 31h GPIO1_CONF 31hGPIO1_CONF 32h GPIO2_CONF 32hGPIO2_CONF 33h GPIO3_CONF 33hGPIO3_CONF 34h GPIO4_CONF 34hGPIO4_CONF 35h GPIO5_CONF 35hGPIO5_CONF 36h GPIO6_CONF 36hGPIO6_CONF 37h GPIO7_CONF 37hGPIO7_CONF 38h GPIO8_CONF 38hGPIO8_CONF 39h GPIO9_CONF 39hGPIO9_CONF 3Ah GPIO10_CONF 3AhGPIO10_CONF 3Bh GPIO11_CONF 3BhGPIO11_CONF 3Ch NPWRON_CONF 3ChNPWRON_CONF 3Dh GPIO_OUT_1 3DhGPIO_OUT_1 3Eh GPIO_OUT_2 3EhGPIO_OUT_2 3Fh GPIO_IN_1 3FhGPIO_IN_1 40h GPIO_IN_2 40hGPIO_IN_2 41h RAIL_SEL_1 41hRAIL_SEL_1 42h RAIL_SEL_2 42hRAIL_SEL_2 43h RAIL_SEL_3 43hRAIL_SEL_3 44h FSM_TRIG_SEL_1 44hFSM_TRIG_SEL_1 45h FSM_TRIG_SEL_2 45hFSM_TRIG_SEL_2 46h FSM_TRIG_MASK_1 46hFSM_TRIG_MASK_1 47h FSM_TRIG_MASK_2 47hFSM_TRIG_MASK_2 48h FSM_TRIG_MASK_3 48hFSM_TRIG_MASK_3 49h MASK_BUCK1_2 49hMASK_BUCK1_2 4Ah MASK_BUCK3_4 4AhMASK_BUCK3_4 4Bh MASK_BUCK5 4BhMASK_BUCK5 4Ch MASK_LDO1_2 4ChMASK_LDO1_2 4Dh MASK_LDO3_4 4DhMASK_LDO3_4 4Eh MASK_VMON 4EhMASK_VMON 4Fh MASK_GPIO1_8_FALL 4FhMASK_GPIO1_8_FALL 50h MASK_GPIO1_8_RISE 50hMASK_GPIO1_8_RISE 51h MASK_GPIO9_11 51hMASK_GPIO9_11 52h MASK_STARTUP 52hMASK_STARTUP 53h MASK_MISC 53hMASK_MISC 54h MASK_MODERATE_ERR 54hMASK_MODERATE_ERR 56h MASK_FSM_ERR 56hMASK_FSM_ERR 57h MASK_COMM_ERR 57hMASK_COMM_ERR 58h MASK_READBACK_ERR 58hMASK_READBACK_ERR 59h MASK_ESM 59hMASK_ESM 5Ah INT_TOP 5AhINT_TOP 5Bh INT_BUCK 5BhINT_BUCK 5Ch INT_BUCK1_2 5ChINT_BUCK1_2 5Dh INT_BUCK3_4 5DhINT_BUCK3_4 5Eh INT_BUCK5 5EhINT_BUCK5 5Fh INT_LDO_VMON 5FhINT_LDO_VMON 60h INT_LDO1_2 60hINT_LDO1_2 61h INT_LDO3_4 61hINT_LDO3_4 62h INT_VMON 62hINT_VMON 63h INT_GPIO 63hINT_GPIO 64h INT_GPIO1_8 64hINT_GPIO1_8 65h INT_STARTUP 65hINT_STARTUP 66h INT_MISC 66hINT_MISC 67h INT_MODERATE_ERR 67hINT_MODERATE_ERR 68h INT_SEVERE_ERR 68hINT_SEVERE_ERR 69h INT_FSM_ERR 69hINT_FSM_ERR 6Ah INT_COMM_ERR 6AhINT_COMM_ERR 6Bh INT_READBACK_ERR 6BhINT_READBACK_ERR 6Ch INT_ESM 6ChINT_ESM 6Dh STAT_BUCK1_2 6DhSTAT_BUCK1_2 6Eh STAT_BUCK3_4 6EhSTAT_BUCK3_4 6Fh STAT_BUCK5 6FhSTAT_BUCK5 70h STAT_LDO1_2 70hSTAT_LDO1_2 71h STAT_LDO3_4 71hSTAT_LDO3_4 72h STAT_VMON 72hSTAT_VMON 73h STAT_STARTUP 73hSTAT_STARTUP 74h STAT_MISC 74hSTAT_MISC 75h STAT_MODERATE_ERR 75hSTAT_MODERATE_ERR 76h STAT_SEVERE_ERR 76hSTAT_SEVERE_ERR 77h STAT_READBACK_ERR 77hSTAT_READBACK_ERR 78h PGOOD_SEL_1 78hPGOOD_SEL_1 79h PGOOD_SEL_2 79hPGOOD_SEL_2 7Ah PGOOD_SEL_3 7AhPGOOD_SEL_3 7Bh PGOOD_SEL_4 7BhPGOOD_SEL_4 7Ch PLL_CTRL 7ChPLL_CTRL 7Dh CONFIG_1 7DhCONFIG_1 7Eh CONFIG_2 7EhCONFIG_2 80h ENABLE_DRV_REG 80hENABLE_DRV_REG 81h MISC_CTRL 81hMISC_CTRL 82h ENABLE_DRV_STAT 82hENABLE_DRV_STAT 83h RECOV_CNT_REG_1 83hRECOV_CNT_REG_1 84h RECOV_CNT_REG_2 84hRECOV_CNT_REG_2 85h FSM_I2C_TRIGGERS 85hFSM_I2C_TRIGGERS 86h FSM_NSLEEP_TRIGGERS 86hFSM_NSLEEP_TRIGGERS 87h BUCK_RESET_REG 87hBUCK_RESET_REG 88h SPREAD_SPECTRUM_1 88hSPREAD_SPECTRUM_1 8Ah FREQ_SEL 8AhFREQ_SEL 8Bh FSM_STEP_SIZE 8BhFSM_STEP_SIZE 8Eh USER_SPARE_REGS 8EhUSER_SPARE_REGS 8Fh ESM_MCU_START_REG 8FhESM_MCU_START_REG 90h ESM_MCU_DELAY1_REG 90hESM_MCU_DELAY1_REG 91h ESM_MCU_DELAY2_REG 91hESM_MCU_DELAY2_REG 92h ESM_MCU_MODE_CFG 92hESM_MCU_MODE_CFG 93h ESM_MCU_HMAX_REG 93hESM_MCU_HMAX_REG 94h ESM_MCU_HMIN_REG 94hESM_MCU_HMIN_REG 95h ESM_MCU_LMAX_REG 95hESM_MCU_LMAX_REG 96h ESM_MCU_LMIN_REG 96hESM_MCU_LMIN_REG 97h ESM_MCU_ERR_CNT_REG 97hESM_MCU_ERR_CNT_REG 98h ESM_SOC_START_REG 98hESM_SOC_START_REG 99h ESM_SOC_DELAY1_REG 99hESM_SOC_DELAY1_REG 9Ah ESM_SOC_DELAY2_REG 9AhESM_SOC_DELAY2_REG 9Bh ESM_SOC_MODE_CFG 9BhESM_SOC_MODE_CFG 9Ch ESM_SOC_HMAX_REG 9ChESM_SOC_HMAX_REG 9Dh ESM_SOC_HMIN_REG 9DhESM_SOC_HMIN_REG 9Eh ESM_SOC_LMAX_REG 9EhESM_SOC_LMAX_REG 9Fh ESM_SOC_LMIN_REG 9FhESM_SOC_LMIN_REG A0h ESM_SOC_ERR_CNT_REG A0hESM_SOC_ERR_CNT_REG A1h REGISTER_LOCK A1hREGISTER_LOCK A6h MANUFACTURING_VER A6hMANUFACTURING_VER A7h CUSTOMER_NVM_ID_REG A7hCUSTOMER_NVM_ID_REG ABh SOFT_REBOOT_REG ABhSOFT_REBOOT_REG B5h RTC_SECONDS B5hRTC_SECONDS B6h RTC_MINUTES B6hRTC_MINUTES B7h RTC_HOURS B7hRTC_HOURS B8h RTC_DAYS B8hRTC_DAYS B9h RTC_MONTHS B9hRTC_MONTHS BAh RTC_YEARS BAhRTC_YEARS BBh RTC_WEEKS BBhRTC_WEEKS BCh ALARM_SECONDS BChALARM_SECONDS BDh ALARM_MINUTES BDhALARM_MINUTES BEh ALARM_HOURS BEhALARM_HOURS BFh ALARM_DAYS BFhALARM_DAYS C0h ALARM_MONTHS C0hALARM_MONTHS C1h ALARM_YEARS C1hALARM_YEARS C2h RTC_CTRL_1 C2hRTC_CTRL_1 C3h RTC_CTRL_2 C3hRTC_CTRL_2 C4h RTC_STATUS C4hRTC_STATUS C5h RTC_INTERRUPTS C5hRTC_INTERRUPTS C6h RTC_COMP_LSB C6hRTC_COMP_LSB C7h RTC_COMP_MSB C7hRTC_COMP_MSB C8h RTC_RESET_STATUS C8hRTC_RESET_STATUS C9h SCRATCH_PAD_REG_1 C9hSCRATCH_PAD_REG_1 CAh SCRATCH_PAD_REG_2 CAhSCRATCH_PAD_REG_2 CBh SCRATCH_PAD_REG_3 CBhSCRATCH_PAD_REG_3 CCh SCRATCH_PAD_REG_4 CChSCRATCH_PAD_REG_4 CDh PFSM_DELAY_REG_1 CDhPFSM_DELAY_REG_1 CEh PFSM_DELAY_REG_2 CEhPFSM_DELAY_REG_2 CFh PFSM_DELAY_REG_3 CFhPFSM_DELAY_REG_3 D0h PFSM_DELAY_REG_4 D0hPFSM_DELAY_REG_4 401h WD_ANSWER_REG 401hWD_ANSWER_REG 402h WD_QUESTION_ANSW_CNT 402hWD_QUESTION_ANSW_CNT 403h WD_WIN1_CFG 403hWD_WIN1_CFG 404h WD_WIN2_CFG 404hWD_WIN2_CFG 405h WD_LONGWIN_CFG 405hWD_LONGWIN_CFG 406h WD_MODE_REG 406hWD_MODE_REG 407h WD_QA_CFG 407hWD_QA_CFG 408h WD_ERR_STATUS 408hWD_ERR_STATUS 409h WD_THR_CFG 409hWD_THR_CFG 40Ah WD_FAIL_CNT_REG 40AhWD_FAIL_CNT_REG Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value TPS6593-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write W1C W1C Write1 to clear WSelfClrF W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite W1C W1C Write1 to clear W1CW1CWrite1 to clear WSelfClrF W Write WSelfClrFWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in . Return to the Summary Table. DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) DEV_REV Register (Offset = 1h) [Reset = 00h] DEV_REV is shown in and described in .Return to the Summary Table.Summary Table DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h DEV_REV Register 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h 7 6 5 4 3 2 1 0 TI_DEVICE_ID R/W-0h 7 6 5 4 3 2 1 0 76543210 TI_DEVICE_ID TI_DEVICE_ID R/W-0h R/W-0h DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) DEV_REV Register Field Descriptions Bit Field Type Reset Description 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0TI_DEVICE_IDR/W0hRefer to Technical Reference Manual / User's Guide for specific numbering. Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in . Return to the Summary Table. NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register (Offset = 2h) [Reset = 00h] NVM_CODE_1 is shown in and described in .Return to the Summary Table.Summary Table NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h NVM_CODE_1 Register 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h 7 6 5 4 3 2 1 0 TI_NVM_ID R/W-0h 7 6 5 4 3 2 1 0 76543210 TI_NVM_ID TI_NVM_ID R/W-0h R/W-0h NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_1 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0TI_NVM_IDR/W0h0x00 - 0xF0 are reserved for TI manufactured NVM variants 0xF1 - 0xFF are reserved for special use 0xF1 = Engineering sample, blank NVM [trim and basic defaults only], customer programmable for engineering use only 0xF2 = Production unit, blank NVM [trim and basic defaults only], customer programmable in volume production 0xF3-FF = Reserved, do not use Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in . Return to the Summary Table. NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register (Offset = 3h) [Reset = 00h] NVM_CODE_2 is shown in and described in .Return to the Summary Table.Summary Table NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h NVM_CODE_2 Register 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h 7 6 5 4 3 2 1 0 TI_NVM_REV R/W-0h 7 6 5 4 3 2 1 0 76543210 TI_NVM_REV TI_NVM_REV R/W-0h R/W-0h NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) NVM_CODE_2 Register Field Descriptions Bit Field Type Reset Description 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0 TI_NVM_REV R/W 0h NVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) 7-0TI_NVM_REVR/W0hNVM revision of the IC Note: This register can be programmed only by the manufacturer. (Default from NVM memory) BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in . Return to the Summary Table. BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CTRL Register (Offset = 4h) [Reset = 22h] BUCK1_CTRL is shown in and described in .Return to the Summary Table.Summary Table BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK1_PLDN BUCK1_VMON_EN BUCK1_VSEL BUCK1_FPWM_MP BUCK1_FPWM BUCK1_EN RESERVEDBUCK1_PLDNBUCK1_VMON_ENBUCK1_VSELBUCK1_FPWM_MPBUCK1_FPWMBUCK1_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 5BUCK1_PLDNR/W1hEnable output pull-down resistor when BUCK1 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 4BUCK1_VMON_ENR/W0hEnable BUCK1 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 3BUCK1_VSELR/W0hSelect output voltage register for BUCK1: (Default from NVM memory) 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 0h = BUCK1_VOUT_1 1h = BUCK1_VOUT_2 2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 2BUCK1_FPWM_MPR/W0hForces the BUCK1 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 1BUCK1_FPWMR/W1hForces the BUCK1 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK1_EN R/W 0h Enable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0BUCK1_ENR/W0hEnable BUCK1 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in . Return to the Summary Table. BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_CONF Register (Offset = 5h) [Reset = 22h] BUCK1_CONF is shown in and described in .Return to the Summary Table.Summary Table BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK1_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK1_ILIM BUCK1_SLEW_RATE RESERVEDBUCK1_ILIMBUCK1_SLEW_RATE R/W-0h R/W-4h R/W-2h R/W-0hR/W-4hR/W-2h BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 5-3BUCK1_ILIMR/W4hSets the switch peak current limit of BUCK1. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 2-0BUCK1_SLEW_RATER/W2hSets the output voltage slew rate for BUCK1 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in . Return to the Summary Table. BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CTRL Register (Offset = 6h) [Reset = 22h] BUCK2_CTRL is shown in and described in .Return to the Summary Table.Summary Table BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK2_PLDN BUCK2_VMON_EN BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN RESERVEDBUCK2_PLDNBUCK2_VMON_ENBUCK2_VSELRESERVEDBUCK2_FPWMBUCK2_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 5BUCK2_PLDNR/W1hEnable output pull-down resistor when BUCK2 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 4BUCK2_VMON_ENR/W0hEnable BUCK2 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 3BUCK2_VSELR/W0hSelect output voltage register for BUCK2: (Default from NVM memory) 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 0h = BUCK2_VOUT_1 1h = BUCK2_VOUT_2 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 1BUCK2_FPWMR/W1hForces the BUCK2 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK2_EN R/W 0h Enable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0BUCK2_ENR/W0hEnable BUCK2 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in . Return to the Summary Table. BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CONF Register (Offset = 7h) [Reset = 22h] BUCK2_CONF is shown in and described in .Return to the Summary Table.Summary Table BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK2_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK2_ILIM BUCK2_SLEW_RATE RESERVEDBUCK2_ILIMBUCK2_SLEW_RATE R/W-0h R/W-4h R/W-2h R/W-0hR/W-4hR/W-2h BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK2_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 5-3BUCK2_ILIMR/W4hSets the switch peak current limit of BUCK2. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 2-0BUCK2_SLEW_RATER/W2hSets the output voltage slew rate for BUCK2 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in . Return to the Summary Table. BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CTRL Register (Offset = 8h) [Reset = 22h] BUCK3_CTRL is shown in and described in .Return to the Summary Table.Summary Table BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK3_PLDN BUCK3_VMON_EN BUCK3_VSEL BUCK3_FPWM_MP BUCK3_FPWM BUCK3_EN RESERVEDBUCK3_PLDNBUCK3_VMON_ENBUCK3_VSELBUCK3_FPWM_MPBUCK3_FPWMBUCK3_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 5BUCK3_PLDNR/W1hEnable output pull-down resistor when BUCK3 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 4BUCK3_VMON_ENR/W0hEnable BUCK3 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 3BUCK3_VSELR/W0hSelect output voltage register for BUCK3: (Default from NVM memory) 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 0h = BUCK3_VOUT_1 1h = BUCK3_VOUT_2 2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 2BUCK3_FPWM_MPR/W0hForces the BUCK3 regulator to operate always in multi-phase and forced PWM operation mode: (Default from NVM memory) 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 0h = Automatic phase adding and shedding. 1h = Forced to multi-phase operation, all phases in the multi-phase configuration. 1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 1BUCK3_FPWMR/W1hForces the BUCK3 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK3_EN R/W 0h Enable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0BUCK3_ENR/W0hEnable BUCK3 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in . Return to the Summary Table. BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CONF Register (Offset = 9h) [Reset = 22h] BUCK3_CONF is shown in and described in .Return to the Summary Table.Summary Table BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK3_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK3_ILIM BUCK3_SLEW_RATE RESERVEDBUCK3_ILIMBUCK3_SLEW_RATE R/W-0h R/W-4h R/W-2h R/W-0hR/W-4hR/W-2h BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK3_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 5-3BUCK3_ILIMR/W4hSets the switch peak current limit of BUCK3. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 2-0BUCK3_SLEW_RATER/W2hSets the output voltage slew rate for BUCK3 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in . Return to the Summary Table. BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CTRL Register (Offset = Ah) [Reset = 22h] BUCK4_CTRL is shown in and described in .Return to the Summary Table.Summary Table BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK4_PLDN BUCK4_VMON_EN BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN RESERVEDBUCK4_PLDNBUCK4_VMON_ENBUCK4_VSELRESERVEDBUCK4_FPWMBUCK4_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 5BUCK4_PLDNR/W1hEnable output pull-down resistor when BUCK4 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 4BUCK4_VMON_ENR/W0hEnable BUCK4 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 3BUCK4_VSELR/W0hSelect output voltage register for BUCK4: (Default from NVM memory) 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 0h = BUCK4_VOUT_1 1h = BUCK4_VOUT_2 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 1BUCK4_FPWMR/W1hForces the BUCK4 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK4_EN R/W 0h Enable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0BUCK4_ENR/W0hEnable BUCK4 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in . Return to the Summary Table. BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CONF Register (Offset = Bh) [Reset = 22h] BUCK4_CONF is shown in and described in .Return to the Summary Table.Summary Table BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK4_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK4_ILIM BUCK4_SLEW_RATE RESERVEDBUCK4_ILIMBUCK4_SLEW_RATE R/W-0h R/W-4h R/W-2h R/W-0hR/W-4hR/W-2h BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK4_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 5-3BUCK4_ILIMR/W4hSets the switch peak current limit of BUCK4. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = 4.5 A 5h = 5.5 A 6h = Reserved 7h = Reserved 2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 2-0BUCK4_SLEW_RATER/W2hSets the output voltage slew rate for BUCK4 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in . Return to the Summary Table. BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CTRL Register (Offset = Ch) [Reset = 22h] BUCK5_CTRL is shown in and described in .Return to the Summary Table.Summary Table BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h BUCK5_CTRL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_PLDN BUCK5_VMON_EN BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN RESERVEDBUCK5_PLDNBUCK5_VMON_ENBUCK5_VSELRESERVEDBUCK5_FPWMBUCK5_EN R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 5BUCK5_PLDNR/W1hEnable output pull-down resistor when BUCK5 is disabled: (Default from NVM memory) 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 0h = Pull-down resistor disabled 1h = Pull-down resistor enabled 4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 4BUCK5_VMON_ENR/W0hEnable BUCK5 OV, UV, SC and ILIM comparators: (Default from NVM memory) 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 0h = OV, UV, SC and ILIM comparators are disabled 1h = OV, UV, SC and ILIM comparators are enabled 3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 3BUCK5_VSELR/W0hSelect output voltage register for BUCK5: (Default from NVM memory) 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 0h = BUCK5_VOUT_1 1h = BUCK5_VOUT_2 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 1BUCK5_FPWMR/W1hForces the BUCK5 regulator to operate in PWM mode: (Default from NVM memory) 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0h = Automatic transitions between PFM and PWM modes (AUTO mode). 1h = Forced to PWM operation. 0 BUCK5_EN R/W 0h Enable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0BUCK5_ENR/W0hEnable BUCK5 regulator: (Default from NVM memory) 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled 0h = BUCK regulator is disabled 1h = BUCK regulator is enabled BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in . Return to the Summary Table. BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CONF Register (Offset = Dh) [Reset = 22h] BUCK5_CONF is shown in and described in .Return to the Summary Table.Summary Table BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h BUCK5_CONF Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_ILIM BUCK5_SLEW_RATE RESERVEDBUCK5_ILIMBUCK5_SLEW_RATE R/W-0h R/W-4h R/W-2h R/W-0hR/W-4hR/W-2h BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK5_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 5-3BUCK5_ILIMR/W4hSets the switch peak current limit of BUCK5. Can be programmed at any time during operation: (Default from NVM memory) 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 0h = Reserved 1h = Reserved 2h = 2.5 A 3h = 3.5 A 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved 2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 2-0BUCK5_SLEW_RATER/W2hSets the output voltage slew rate for BUCK5 regulator (rising and falling edges): (Default from NVM memory) 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs 0h = 33 mV/μs 1h = 20 mV/μs 2h = 10 mV/μs 3h = 5.0 mV/μs 4h = 2.5 mV/μs 5h = 1.3 mV/μs 6h = 0.63 mV/μs 7h = 0.31 mV/μs BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h] BUCK1_VOUT_1 is shown in and described in .Return to the Summary Table.Summary Table BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h BUCK1_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h 7 6 5 4 3 2 1 0 BUCK1_VSET1 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK1_VSET1 BUCK1_VSET1 R/W-0h R/W-0h BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK1_VSET1R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h] BUCK1_VOUT_2 is shown in and described in .Return to the Summary Table.Summary Table BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h BUCK1_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h 7 6 5 4 3 2 1 0 BUCK1_VSET2 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK1_VSET2 BUCK1_VSET2 R/W-0h R/W-0h BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK1_VSET2R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h] BUCK2_VOUT_1 is shown in and described in .Return to the Summary Table.Summary Table BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h BUCK2_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h 7 6 5 4 3 2 1 0 BUCK2_VSET1 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK2_VSET1 BUCK2_VSET1 R/W-0h R/W-0h BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK2_VSET1R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h] BUCK2_VOUT_2 is shown in and described in .Return to the Summary Table.Summary Table BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h BUCK2_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h 7 6 5 4 3 2 1 0 BUCK2_VSET2 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK2_VSET2 BUCK2_VSET2 R/W-0h R/W-0h BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK2_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK2_VSET2R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h] BUCK3_VOUT_1 is shown in and described in .Return to the Summary Table.Summary Table BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h BUCK3_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h 7 6 5 4 3 2 1 0 BUCK3_VSET1 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK3_VSET1 BUCK3_VSET1 R/W-0h R/W-0h BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK3_VSET1R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h] BUCK3_VOUT_2 is shown in and described in .Return to the Summary Table.Summary Table BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h BUCK3_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h 7 6 5 4 3 2 1 0 BUCK3_VSET2 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK3_VSET2 BUCK3_VSET2 R/W-0h R/W-0h BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK3_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK3_VSET2R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h] BUCK4_VOUT_1 is shown in and described in .Return to the Summary Table.Summary Table BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h BUCK4_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h 7 6 5 4 3 2 1 0 BUCK4_VSET1 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_VSET1 BUCK4_VSET1 R/W-0h R/W-0h BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK4_VSET1R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h] BUCK4_VOUT_2 is shown in and described in .Return to the Summary Table.Summary Table BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h BUCK4_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h 7 6 5 4 3 2 1 0 BUCK4_VSET2 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_VSET2 BUCK4_VSET2 R/W-0h R/W-0h BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK4_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK4_VSET2R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h] BUCK5_VOUT_1 is shown in and described in .Return to the Summary Table.Summary Table BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h BUCK5_VOUT_1 Register 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h 7 6 5 4 3 2 1 0 BUCK5_VSET1 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK5_VSET1 BUCK5_VSET1 R/W-0h R/W-0h BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_1 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK5_VSET1R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in . Return to the Summary Table. BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h] BUCK5_VOUT_2 is shown in and described in .Return to the Summary Table.Summary Table BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h BUCK5_VOUT_2 Register 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h 7 6 5 4 3 2 1 0 BUCK5_VSET2 R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK5_VSET2 BUCK5_VSET2 R/W-0h R/W-0h BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK5_VOUT_2 Register Field Descriptions Bit Field Type Reset Description 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) 7-0BUCK5_VSET2R/W0hVoltage selection for buck regulator. See Buck regulators chapter for voltage levels. (Default from NVM memory) BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h] BUCK1_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h BUCK1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK1_UV_THR BUCK1_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK1_UV_THR BUCK1_OV_THR RESERVEDBUCK1_UV_THRBUCK1_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3BUCK1_UV_THRR/W0hPowergood low threshold level for BUCK1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0BUCK1_OV_THRR/W0hPowergood high threshold level for BUCK1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h] BUCK2_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h BUCK2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK2_UV_THR BUCK2_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK2_UV_THR BUCK2_OV_THR RESERVEDBUCK2_UV_THRBUCK2_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3BUCK2_UV_THRR/W0hPowergood low threshold level for BUCK2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0BUCK2_OV_THRR/W0hPowergood high threshold level for BUCK2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in . 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BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h] BUCK3_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h BUCK3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK3_UV_THR BUCK3_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK3_UV_THR BUCK3_OV_THR RESERVEDBUCK3_UV_THRBUCK3_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3BUCK3_UV_THRR/W0hPowergood low threshold level for BUCK3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0BUCK3_OV_THRR/W0hPowergood high threshold level for BUCK3: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h] BUCK4_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h BUCK4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK4_UV_THR BUCK4_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK4_UV_THR BUCK4_OV_THR RESERVEDBUCK4_UV_THRBUCK4_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3BUCK4_UV_THRR/W0hPowergood low threshold level for BUCK4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0BUCK4_OV_THRR/W0hPowergood high threshold level for BUCK4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in . Return to the Summary Table. BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h] BUCK5_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h BUCK5_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_UV_THR BUCK5_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_UV_THR BUCK5_OV_THR RESERVEDBUCK5_UV_THRBUCK5_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV BUCK5_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3BUCK5_UV_THRR/W0hPowergood low threshold level for BUCK5: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0BUCK5_OV_THRR/W0hPowergood high threshold level for BUCK5: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in . Return to the Summary Table. LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h] LDO1_CTRL is shown in and described in .Return to the Summary Table.Summary Table LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO1_PLDN LDO1_VMON_EN RESERVED LDO1_SLOW_RAMP LDO1_EN RESERVEDLDO1_PLDNLDO1_VMON_ENRESERVEDLDO1_SLOW_RAMPLDO1_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-3hR/W-0hR/W-0hR/W-0hR/W-0h LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 6-5LDO1_PLDNR/W3hEnable output pull-down resistor when LDO1 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 4LDO1_VMON_ENR/W0hEnable LDO1 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 3-2RESERVEDR/W0h 1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1LDO1_SLOW_RAMPR/W0hLDO1 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO1_EN R/W 0h Enable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0LDO1_ENR/W0hEnable LDO1 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in . Return to the Summary Table. LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h] LDO2_CTRL is shown in and described in .Return to the Summary Table.Summary Table LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO2_PLDN LDO2_VMON_EN RESERVED LDO2_SLOW_RAMP LDO2_EN RESERVEDLDO2_PLDNLDO2_VMON_ENRESERVEDLDO2_SLOW_RAMPLDO2_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-3hR/W-0hR/W-0hR/W-0hR/W-0h LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 6-5LDO2_PLDNR/W3hEnable output pull-down resistor when LDO2 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 4LDO2_VMON_ENR/W0hEnable LDO2 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 3-2RESERVEDR/W0h 1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1LDO2_SLOW_RAMPR/W0hLDO2 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO2_EN R/W 0h Enable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0LDO2_ENR/W0hEnable LDO2 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in . Return to the Summary Table. LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h] LDO3_CTRL is shown in and described in .Return to the Summary Table.Summary Table LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO3_PLDN LDO3_VMON_EN RESERVED LDO3_SLOW_RAMP LDO3_EN RESERVEDLDO3_PLDNLDO3_VMON_ENRESERVEDLDO3_SLOW_RAMPLDO3_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-3hR/W-0hR/W-0hR/W-0hR/W-0h LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 6-5LDO3_PLDNR/W3hEnable output pull-down resistor when LDO3 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 4LDO3_VMON_ENR/W0hEnable LDO3 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 3-2RESERVEDR/W0h 1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1LDO3_SLOW_RAMPR/W0hLDO3 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO3_EN R/W 0h Enable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0LDO3_ENR/W0hEnable LDO3 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in . Return to the Summary Table. LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register (Offset = 20h) [Reset = 60h] LDO4_CTRL is shown in and described in .Return to the Summary Table.Summary Table LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h LDO4_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO4_PLDN LDO4_VMON_EN RESERVED LDO4_SLOW_RAMP LDO4_EN RESERVEDLDO4_PLDNLDO4_VMON_ENRESERVEDLDO4_SLOW_RAMPLDO4_EN R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-3hR/W-0hR/W-0hR/W-0hR/W-0h LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 6-5LDO4_PLDNR/W3hEnable output pull-down resistor when LDO4 is disabled: (Default from NVM memory) 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 0h = 50 kOhm 1h = 125 Ohm 2h = 250 Ohm 3h = 500 Ohm 4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 4LDO4_VMON_ENR/W0hEnable LDO4 OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 3-2 RESERVED R/W 0h 3-2RESERVEDR/W0h 1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1LDO4_SLOW_RAMPR/W0hLDO4 start-up slew rate selection 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to 90% of LDOn_VSET 0 LDO4_EN R/W 0h Enable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0LDO4_ENR/W0hEnable LDO4 regulator: (Default from NVM memory) 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. 0h = LDO1 regulator is disabled 1h = LDO1 regulator is enabled. LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in . Return to the Summary Table. LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDORTC_CTRL Register (Offset = 22h) [Reset = 00h] LDORTC_CTRL is shown in and described in .Return to the Summary Table.Summary Table LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h LDORTC_CTRL Register 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDORTC_DIS R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDORTC_DIS RESERVEDLDORTC_DIS R/W-0h R/W-0h R/W-0hR/W-0h LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDORTC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 LDORTC_DIS R/W 0h Disable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled 0LDORTC_DISR/W0hDisable LDORTC regulator: 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled 0h = LDORTC regulator is enabled 1h = LDORTC regulator is disabled LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in . Return to the Summary Table. LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO1_VOUT Register (Offset = 23h) [Reset = 00h] LDO1_VOUT is shown in and described in .Return to the Summary Table.Summary Table LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO1_VOUT Register 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO1_BYPASS LDO1_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO1_BYPASS LDO1_VSET RESERVED LDO1_BYPASSLDO1_VSETRESERVED R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO1_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 7LDO1_BYPASSR/W0hSet LDO1 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 6-1LDO1_VSETR/W0hVoltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 0RESERVEDR/W0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in . Return to the Summary Table. LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register (Offset = 24h) [Reset = 00h] LDO2_VOUT is shown in and described in .Return to the Summary Table.Summary Table LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO2_VOUT Register 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO2_BYPASS LDO2_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO2_BYPASS LDO2_VSET RESERVED LDO2_BYPASSLDO2_VSETRESERVED R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO2_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 7LDO2_BYPASSR/W0hSet LDO2 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 6-1LDO2_VSETR/W0hVoltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 0RESERVEDR/W0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in . Return to the Summary Table. LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register (Offset = 25h) [Reset = 00h] LDO3_VOUT is shown in and described in .Return to the Summary Table.Summary Table LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h LDO3_VOUT Register 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO3_BYPASS LDO3_VSET RESERVED R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO3_BYPASS LDO3_VSET RESERVED LDO3_BYPASSLDO3_VSETRESERVED R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h LDO3_VOUT Register Field Descriptions Bit Field Type Reset Description 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 7LDO3_BYPASSR/W0hSet LDO3 to bypass mode: (Default from NVM memory) 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 0h = LDO is set to linear regulator mode. 1h = LDO is set to bypass mode. 6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 6-1LDO3_VSETR/W0hVoltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 0 RESERVED R/W 0h 0RESERVEDR/W0h LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in . Return to the Summary Table. LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO4_VOUT Register (Offset = 26h) [Reset = 00h] LDO4_VOUT is shown in and described in .Return to the Summary Table.Summary Table LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h LDO4_VOUT Register 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO4_VSET R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO4_VSET RESERVEDLDO4_VSET R/W-0h R/W-0h R/W-0hR/W-0h LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO4_VOUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) 6-0LDO4_VSETR/W0hVoltage selection for LDO regulator. See LDO regulators chapter for voltage levels. (Default from NVM memory) LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h] LDO1_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h LDO1_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO1_UV_THR LDO1_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO1_UV_THR LDO1_OV_THR RESERVEDLDO1_UV_THRLDO1_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO1_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3LDO1_UV_THRR/W0hPowergood low threshold level for LDO1: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0LDO1_OV_THRR/W0hPowergood high threshold level for LDO1: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h] LDO2_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h LDO2_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO2_UV_THR LDO2_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO2_UV_THR LDO2_OV_THR RESERVEDLDO2_UV_THRLDO2_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO2_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3LDO2_UV_THRR/W0hPowergood low threshold level for LDO2: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0LDO2_OV_THRR/W0hPowergood high threshold level for LDO2: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h] LDO3_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h LDO3_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO3_UV_THR LDO3_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO3_UV_THR LDO3_OV_THR RESERVEDLDO3_UV_THRLDO3_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO3_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3LDO3_UV_THRR/W0hPowergood low threshold level for LDO3: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0LDO3_OV_THRR/W0hPowergood high threshold level for LDO3: Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in . Return to the Summary Table. LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h] LDO4_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h LDO4_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED LDO4_UV_THR LDO4_OV_THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED LDO4_UV_THR LDO4_OV_THR RESERVEDLDO4_UV_THRLDO4_OV_THR R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV LDO4_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 5-3LDO4_UV_THRR/W0hPowergood low threshold level for LDO4: (Default from NVM memory) 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 0h = -3% / -30mV 1h = -3.5% / -35 mV 2h = -4% / -40 mV 3h = -5% / -50 mV 4h = -6% / -60 mV 5h = -7% / -70 mV 6h = -8% / -80 mV 7h = -10% / -100mV 2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 2-0LDO4_OV_THRR/W0hPowergood high threshold level for LDO4: (Default from NVM memory) 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV 0h = +3% / +30mV 1h = +3.5% / +35 mV 2h = +4% / +40 mV 3h = +5% / +50 mV 4h = +6% / +60 mV 5h = +7% / +70 mV 6h = +8% / +80 mV 7h = +10% / +100mV VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in . Return to the Summary Table. VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h] VCCA_VMON_CTRL is shown in and described in .Return to the Summary Table.Summary Table VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h VCCA_VMON_CTRL Register 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VMON_DEGLITCH_SEL RESERVED VCCA_VMON_EN RESERVEDVMON_DEGLITCH_SELRESERVEDVCCA_VMON_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_VMON_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 5VMON_DEGLITCH_SELR/W0hDeglitch time select for BUCKx_VMON, LDOx_VMON and VCCA_VMON (Default from NVM memory) 0h = 4 us 1h = 20 us 0h = 4 us 1h = 20 us 4-1 RESERVED R/W 0h 4-1RESERVEDR/W0h 0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0VCCA_VMON_ENR/W0hEnable VCCA OV and UV comparators: (Default from NVM memory) 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. 0h = OV and UV comparators are disabled 1h = OV and UV comparators are enabled. VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in . Return to the Summary Table. VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h] VCCA_PG_WINDOW is shown in and described in .Return to the Summary Table.Summary Table VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h VCCA_PG_WINDOW Register 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_PG_SET VCCA_UV_THR VCCA_OV_THR RESERVEDVCCA_PG_SETVCCA_UV_THRVCCA_OV_THR R/W-0h R/W-1h R/W-0h R/W-0h R/W-0hR/W-1hR/W-0hR/W-0h VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% VCCA_PG_WINDOW Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% 7 RESERVED R/W 0h 7RESERVEDR/W0h 6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 6VCCA_PG_SETR/W1hPowergood level for VCCA pin: (Default from NVM memory) 0h = 3.3 V 1h = 5.0 V 0h = 3.3 V 1h = 5.0 V 5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 5-3VCCA_UV_THRR/W0hPowergood low threshold level for VCCA pin: (Default from NVM memory) 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 0h = -3% 1h = -3.5% 2h = -4% 3h = -5% 4h = -6% 5h = -7% 6h = -8% 7h = -10% 2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% 2-0VCCA_OV_THRR/W0hPowergood high threshold level for VCCA pin: (Default from NVM memory) 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% 0h = +3% 1h = +3.5% 2h = +4% 3h = +5% 4h = +6% 5h = +7% 6h = +8% 7h = +10% GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in . Return to the Summary Table. GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah] GPIO1_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO1_CONF Register 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR GPIO1_SELGPIO1_DEGLITCH_ENGPIO1_PU_PD_ENGPIO1_PU_SELGPIO1_ODGPIO1_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO1_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO1_SEL R/W 0h GPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO1_SELR/W0hGPIO1 signal function: (Default from NVM memory) 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO1 1h = SCL_I2C2/CS_SPI 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO1_DEGLITCH_ENR/W0hGPIO1 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO1_PU_PD_ENR/W1hControl for GPIO1 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO1_PU_SELR/W0hControl for GPIO1 pin pull-up/pull-down resistor: GPIO1_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO1_ODR/W1hGPIO1 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO1_DIR R/W 0h GPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO1_DIRR/W0hGPIO1 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in . Return to the Summary Table. GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah] GPIO2_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO2_CONF Register 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR GPIO2_SELGPIO2_DEGLITCH_ENGPIO2_PU_PD_ENGPIO2_PU_SELGPIO2_ODGPIO2_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO2_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO2_SEL R/W 0h GPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO2_SELR/W0hGPIO2 signal function: (Default from NVM memory) 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO2 1h = TRIG_WDOG 2h = SDA_I2C2/SDO_SPI 3h = SDA_I2C2/SDO_SPI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO2_DEGLITCH_ENR/W0hGPIO2 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO2_PU_PD_ENR/W1hControl for GPIO2 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO2_PU_SELR/W0hControl for GPIO2 pin pull-up/pull-down resistor: GPIO2_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO2_ODR/W1hGPIO2 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO2_DIR R/W 0h GPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO2_DIRR/W0hGPIO2 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in . Return to the Summary Table. GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah] GPIO3_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO3_CONF Register 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR GPIO3_SELGPIO3_DEGLITCH_ENGPIO3_PU_PD_ENGPIO3_PU_SELGPIO3_ODGPIO3_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO3_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO3_SEL R/W 0h GPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 7-5GPIO3_SELR/W0hGPIO3 signal function: (Default from NVM memory) 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 0h = GPIO3 1h = CLK32KOUT 2h = NERR_SOC 3h = NERR_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO3_DEGLITCH_ENR/W0hGPIO3 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO3_PU_PD_ENR/W1hControl for GPIO3 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO3_PU_SELR/W0hControl for GPIO3 pin pull-up/pull-down resistor: GPIO3_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO3_ODR/W1hGPIO3 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO3_DIR R/W 0h GPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO3_DIRR/W0hGPIO3 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in . Return to the Summary Table. GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah] GPIO4_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO4_CONF Register 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR GPIO4_SELGPIO4_DEGLITCH_ENGPIO4_PU_PD_ENGPIO4_PU_SELGPIO4_ODGPIO4_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO4_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO4_SEL R/W 0h GPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 7-5GPIO4_SELR/W0hGPIO4 signal function: (Default from NVM memory) 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 0h = GPIO4 1h = CLK32KOUT 2h = CLK32KOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = LP_WKUP1 7h = LP_WKUP2 4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO4_DEGLITCH_ENR/W0hGPIO4 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO4_PU_PD_ENR/W1hControl for GPIO4 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO4_PU_SELR/W0hControl for GPIO4 pin pull-up/pull-down resistor: GPIO4_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO4_ODR/W1hGPIO4 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO4_DIR R/W 0h GPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO4_DIRR/W0hGPIO4 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in . Return to the Summary Table. GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah] GPIO5_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO5_CONF Register 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR GPIO5_SELGPIO5_DEGLITCH_ENGPIO5_PU_PD_ENGPIO5_PU_SELGPIO5_ODGPIO5_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO5_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO5_SEL R/W 0h GPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO5_SELR/W0hGPIO5 signal function: (Default from NVM memory) 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO5 1h = SCLK_SPMI 2h = SCLK_SPMI 3h = SCLK_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO5_DEGLITCH_ENR/W0hGPIO5 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO5_PU_PD_ENR/W1hControl for GPIO5 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO5_PU_SELR/W0hControl for GPIO5 pin pull-up/pull-down resistor: GPIO5_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO5_ODR/W1hGPIO5 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO5_DIR R/W 0h GPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO5_DIRR/W0hGPIO5 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in . Return to the Summary Table. GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah] GPIO6_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO6_CONF Register 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR GPIO6_SELGPIO6_DEGLITCH_ENGPIO6_PU_PD_ENGPIO6_PU_SELGPIO6_ODGPIO6_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO6_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO6_SEL R/W 0h GPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO6_SELR/W0hGPIO6 signal function: (Default from NVM memory) 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO6 1h = SDATA_SPMI 2h = SDATA_SPMI 3h = SDATA_SPMI 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO6_DEGLITCH_ENR/W0hGPIO6 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO6_PU_PD_ENR/W1hControl for GPIO6 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO6_PU_SELR/W0hControl for GPIO6 pin pull-up/pull-down resistor: GPIO6_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO6_ODR/W1hGPIO6 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO6_DIR R/W 0h GPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO6_DIRR/W0hGPIO6 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in . Return to the Summary Table. GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah] GPIO7_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO7_CONF Register 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR GPIO7_SELGPIO7_DEGLITCH_ENGPIO7_PU_PD_ENGPIO7_PU_SELGPIO7_ODGPIO7_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO7_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO7_SEL R/W 0h GPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO7_SELR/W0hGPIO7 signal function: (Default from NVM memory) 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO7 1h = NERR_MCU 2h = NERR_MCU 3h = NERR_MCU 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO7_DEGLITCH_ENR/W0hGPIO7 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO7_PU_PD_ENR/W1hControl for GPIO7 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO7_PU_SELR/W0hControl for GPIO7 pin pull-up/pull-down resistor: GPIO7_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO7_ODR/W1hGPIO7 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO7_DIR R/W 0h GPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO7_DIRR/W0hGPIO7 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in . Return to the Summary Table. GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah] GPIO8_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO8_CONF Register 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR GPIO8_SELGPIO8_DEGLITCH_ENGPIO8_PU_PD_ENGPIO8_PU_SELGPIO8_ODGPIO8_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO8_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO8_SEL R/W 0h GPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO8_SELR/W0hGPIO8 signal function: (Default from NVM memory) 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO8 1h = CLK32KOUT 2h = SYNCCLKOUT 3h = DISABLE_WDOG 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO8_DEGLITCH_ENR/W0hGPIO8 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO8_PU_PD_ENR/W1hControl for GPIO8 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO8_PU_SELR/W0hControl for GPIO8 pin pull-up/pull-down resistor: GPIO8_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO8_ODR/W1hGPIO8 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO8_DIR R/W 0h GPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO8_DIRR/W0hGPIO8 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in . Return to the Summary Table. GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah] GPIO9_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO9_CONF Register 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR GPIO9_SELGPIO9_DEGLITCH_ENGPIO9_PU_PD_ENGPIO9_PU_SELGPIO9_ODGPIO9_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO9_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO9_SEL R/W 0h GPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO9_SELR/W0hGPIO9 signal function: (Default from NVM memory) 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO9 1h = PGOOD 2h = DISABLE_WDOG 3h = SYNCCLKOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO9_DEGLITCH_ENR/W0hGPIO9 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO9_PU_PD_ENR/W1hControl for GPIO9 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO9_PU_SELR/W0hControl for GPIO9 pin pull-up/pull-down resistor: GPIO9_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO9_ODR/W1hGPIO9 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO9_DIR R/W 0h GPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO9_DIRR/W0hGPIO9 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in . Return to the Summary Table. GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah] GPIO10_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO10_CONF Register 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR GPIO10_SELGPIO10_DEGLITCH_ENGPIO10_PU_PD_ENGPIO10_PU_SELGPIO10_ODGPIO10_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO10_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO10_SEL R/W 0h GPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO10_SELR/W0hGPIO10 signal function: (Default from NVM memory) 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO10 1h = SYNCCLKIN 2h = SYNCCLKOUT 3h = CLK32KOUT 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO10_DEGLITCH_ENR/W0hGPIO10 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO10_PU_PD_ENR/W1hControl for GPIO10 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO10_PU_SELR/W0hControl for GPIO10 pin pull-up/pull-down resistor: GPIO10_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO10_ODR/W1hGPIO10 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO10_DIR R/W 0h GPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO10_DIRR/W0hGPIO10 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in . Return to the Summary Table. GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah] GPIO11_CONF is shown in and described in .Return to the Summary Table.Summary Table GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h GPIO11_CONF Register 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO11_SEL GPIO11_DEGLITCH_EN GPIO11_PU_PD_EN GPIO11_PU_SEL GPIO11_OD GPIO11_DIR GPIO11_SELGPIO11_DEGLITCH_ENGPIO11_PU_PD_ENGPIO11_PU_SELGPIO11_ODGPIO11_DIR R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0h GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output GPIO11_CONF Register Field Descriptions Bit Field Type Reset Description 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output 7-5 GPIO11_SEL R/W 0h GPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 7-5GPIO11_SELR/W0hGPIO11 signal function: (Default from NVM memory) 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 0h = GPIO11 1h = TRIG_WDOG 2h = NRSTOUT_SOC 3h = NRSTOUT_SOC 4h = NSLEEP1 5h = NSLEEP2 6h = WKUP1 7h = WKUP2 4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 4GPIO11_DEGLITCH_ENR/W0hGPIO11 signal deglitch time when signal direction is input: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time. 3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3GPIO11_PU_PD_ENR/W1hControl for GPIO11 pin pull-up/pull-down resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2GPIO11_PU_SELR/W0hControl for GPIO11 pin pull-up/pull-down resistor: GPIO11_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 1GPIO11_ODR/W1hGPIO11 signal type when configured to output: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output 0 GPIO11_DIR R/W 0h GPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0GPIO11_DIRR/W0hGPIO11 signal direction: (Default from NVM memory) 0h = Input 1h = Output 0h = Input 1h = Output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in . Return to the Summary Table. NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h] NPWRON_CONF is shown in and described in .Return to the Summary Table.Summary Table NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h NPWRON_CONF Register 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 NPWRON_SEL ENABLE_POL ENABLE_DEGLITCH_EN ENABLE_PU_PD_EN ENABLE_PU_SEL RESERVED NRSTOUT_OD NPWRON_SELENABLE_POLENABLE_DEGLITCH_ENENABLE_PU_PD_ENENABLE_PU_SELRESERVEDNRSTOUT_OD R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-2hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output NPWRON_CONF Register Field Descriptions Bit Field Type Reset Description 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 7-6NPWRON_SELR/W2hNPWRON/ENABLE signal function: (Default from NVM memory) 0h = ENABLE 1h = NPWRON 2h = None 3h = None 0h = ENABLE 1h = NPWRON 2h = None 3h = None 5 ENABLE_POL R/W 0h Control for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 5ENABLE_POLR/W0hControl for ENABLE pin polarity: (Default from NVM memory) 0h = Active high 1h = Active low 0h = Active high 1h = Active low 4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 4ENABLE_DEGLITCH_ENR/W0hNPWRON/ENABLE signal deglitch time: (Default from NVM memory) 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 0h = No deglitch, only synchronization. 1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when NPWRON. 3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 3ENABLE_PU_PD_ENR/W1hControl for NPWRON/ENABLE pin pull-up resistor: (Default from NVM memory) 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 0h = Pull-up/pull-down resistor disabled 1h = Pull-up/pull-down resistor enabled 2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 2ENABLE_PU_SELR/W0hControl for NPWRON/ENABLE pin pull-down resistor: ENABLE_PU_PD_EN must be 1 to select the resistor. (Default from NVM memory) 0h = Pull-down resistor selected 1h = Pull-up resistor selected 0h = Pull-down resistor selected 1h = Pull-up resistor selected 1 RESERVED R/W 0h 1RESERVEDR/W0h 0 NRSTOUT_OD R/W 0h NRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0NRSTOUT_ODR/W0hNRSTOUT signal type: (Default from NVM memory) 0h = Push-pull output 1h = Open-drain output 0h = Push-pull output 1h = Open-drain output GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in . Return to the Summary Table. GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h] GPIO_OUT_1 is shown in and described in .Return to the Summary Table.Summary Table GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_1 Register 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT GPIO8_OUTGPIO7_OUTGPIO6_OUTGPIO5_OUTGPIO4_OUTGPIO3_OUTGPIO2_OUTGPIO1_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 7GPIO8_OUTR/W0hControl for GPIO8 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 6GPIO7_OUTR/W0hControl for GPIO7 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 5GPIO6_OUTR/W0hControl for GPIO6 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 4GPIO5_OUTR/W0hControl for GPIO5 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 3GPIO4_OUTR/W0hControl for GPIO4 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2GPIO3_OUTR/W0hControl for GPIO3 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1GPIO2_OUTR/W0hControl for GPIO2 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0GPIO1_OUTR/W0hControl for GPIO1 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in . Return to the Summary Table. GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h] GPIO_OUT_2 is shown in and described in .Return to the Summary Table.Summary Table GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h GPIO_OUT_2 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT RESERVEDGPIO11_OUTGPIO10_OUTGPIO9_OUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High GPIO_OUT_2 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R/W 0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 7-3 RESERVED R/W 0h 7-3RESERVEDR/W0h 2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 2GPIO11_OUTR/W0hControl for GPIO11 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 1GPIO10_OUTR/W0hControl for GPIO10 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High 0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0GPIO9_OUTR/W0hControl for GPIO9 signal when configured to GPIO Output: (Default from NVM memory) 0h = Low 1h = High 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in . Return to the Summary Table. GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h] GPIO_IN_1 is shown in and described in .Return to the Summary Table.Summary Table GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h GPIO_IN_1 Register 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN GPIO8_INGPIO7_INGPIO6_INGPIO5_INGPIO4_INGPIO3_INGPIO2_INGPIO1_IN R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High GPIO_IN_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High 7 GPIO8_IN R 0h Level of GPIO8 signal: 0h = Low 1h = High 7GPIO8_INR0hLevel of GPIO8 signal: 0h = Low 1h = High 0h = Low 1h = High 6 GPIO7_IN R 0h Level of GPIO7 signal: 0h = Low 1h = High 6GPIO7_INR0hLevel of GPIO7 signal: 0h = Low 1h = High 0h = Low 1h = High 5 GPIO6_IN R 0h Level of GPIO6 signal: 0h = Low 1h = High 5GPIO6_INR0hLevel of GPIO6 signal: 0h = Low 1h = High 0h = Low 1h = High 4 GPIO5_IN R 0h Level of GPIO5 signal: 0h = Low 1h = High 4GPIO5_INR0hLevel of GPIO5 signal: 0h = Low 1h = High 0h = Low 1h = High 3 GPIO4_IN R 0h Level of GPIO4 signal: 0h = Low 1h = High 3GPIO4_INR0hLevel of GPIO4 signal: 0h = Low 1h = High 0h = Low 1h = High 2 GPIO3_IN R 0h Level of GPIO3 signal: 0h = Low 1h = High 2GPIO3_INR0hLevel of GPIO3 signal: 0h = Low 1h = High 0h = Low 1h = High 1 GPIO2_IN R 0h Level of GPIO2 signal: 0h = Low 1h = High 1GPIO2_INR0hLevel of GPIO2 signal: 0h = Low 1h = High 0h = Low 1h = High 0 GPIO1_IN R 0h Level of GPIO1 signal: 0h = Low 1h = High 0GPIO1_INR0hLevel of GPIO1 signal: 0h = Low 1h = High 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in . Return to the Summary Table. GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High GPIO_IN_2 Register (Offset = 40h) [Reset = 00h] GPIO_IN_2 is shown in and described in .Return to the Summary Table.Summary Table GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h GPIO_IN_2 Register 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN RESERVEDNPWRON_INGPIO11_INGPIO10_INGPIO9_IN R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0h GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High GPIO_IN_2 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R 0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High 7-4 RESERVED R 0h 7-4RESERVEDR0h 3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal: 0h = Low 1h = High 3NPWRON_INR0hLevel of NPWRON/ENABLE signal: 0h = Low 1h = High 0h = Low 1h = High 2 GPIO11_IN R 0h Level of GPIO11 signal: 0h = Low 1h = High 2GPIO11_INR0hLevel of GPIO11 signal: 0h = Low 1h = High 0h = Low 1h = High 1 GPIO10_IN R 0h Level of GPIO10 signal: 0h = Low 1h = High 1GPIO10_INR0hLevel of GPIO10 signal: 0h = Low 1h = High 0h = Low 1h = High 0 GPIO9_IN R 0h Level of GPIO9 signal: 0h = Low 1h = High 0GPIO9_INR0hLevel of GPIO9 signal: 0h = Low 1h = High 0h = Low 1h = High RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in . Return to the Summary Table. RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h] RAIL_SEL_1 is shown in and described in .Return to the Summary Table.Summary Table RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_1 Register 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL BUCK4_GRP_SELBUCK3_GRP_SELBUCK2_GRP_SELBUCK1_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 7-6BUCK4_GRP_SELR/W0hRail group selection for BUCK4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4BUCK3_GRP_SELR/W0hRail group selection for BUCK3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2BUCK2_GRP_SELR/W0hRail group selection for BUCK2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0BUCK1_GRP_SELR/W0hRail group selection for BUCK1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in . Return to the Summary Table. RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h] RAIL_SEL_2 is shown in and described in .Return to the Summary Table.Summary Table RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h RAIL_SEL_2 Register 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL LDO3_GRP_SELLDO2_GRP_SELLDO1_GRP_SELBUCK5_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 7-6LDO3_GRP_SELR/W0hRail group selection for LDO3: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 5-4LDO2_GRP_SELR/W0hRail group selection for LDO2: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2LDO1_GRP_SELR/W0hRail group selection for LDO1: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0BUCK5_GRP_SELR/W0hRail group selection for BUCK5: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in . Return to the Summary Table. RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h] RAIL_SEL_3 is shown in and described in .Return to the Summary Table.Summary Table RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h RAIL_SEL_3 Register 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_GRP_SEL LDO4_GRP_SEL RESERVEDVCCA_GRP_SELLDO4_GRP_SEL R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group RAIL_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 3-2VCCA_GRP_SELR/W0hRail group selection for VCCA monitoring: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 1-0LDO4_GRP_SELR/W0hRail group selection for LDO4: (Default from NVM memory) 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group 0h = No group assigned 1h = MCU rail group 2h = SOC rail group 3h = OTHER rail group FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h] FSM_TRIG_SEL_1 is shown in and described in .Return to the Summary Table.Summary Table FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_SEL_1 Register 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG SEVERE_ERR_TRIGOTHER_RAIL_TRIGSOC_RAIL_TRIGMCU_RAIL_TRIG R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 7-6SEVERE_ERR_TRIGR/W0hTrigger selection for Severe Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 5-4OTHER_RAIL_TRIGR/W0hTrigger selection for OTHER rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 3-2SOC_RAIL_TRIGR/W0hTrigger selection for SOC rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0MCU_RAIL_TRIGR/W0hTrigger selection for MCU rail group: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h] FSM_TRIG_SEL_2 is shown in and described in .Return to the Summary Table.Summary Table FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h FSM_TRIG_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED MODERATE_ERR_TRIG R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED MODERATE_ERR_TRIG RESERVEDMODERATE_ERR_TRIG R/W-0h R/W-0h R/W-0hR/W-0h FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 1-0MODERATE_ERR_TRIGR/W0hTrigger selection for Moderate Error: (Default from NVM memory) 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error 0h = Immediate shutdown 1h = Orderly shutdown 2h = MCU power error 3h = SOC power error FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h] FSM_TRIG_MASK_1 is shown in and described in .Return to the Summary Table.Summary Table FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_1 Register 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO4_FSM_MASK_POL GPIO4_FSM_MASK GPIO3_FSM_MASK_POL GPIO3_FSM_MASK GPIO2_FSM_MASK_POL GPIO2_FSM_MASK GPIO1_FSM_MASK_POL GPIO1_FSM_MASK GPIO4_FSM_MASK_POLGPIO4_FSM_MASKGPIO3_FSM_MASK_POLGPIO3_FSM_MASKGPIO2_FSM_MASK_POLGPIO2_FSM_MASKGPIO1_FSM_MASK_POLGPIO1_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 7GPIO4_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 6GPIO4_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 5GPIO3_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 4GPIO3_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 3GPIO2_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 2GPIO2_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 1GPIO1_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0GPIO1_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h] FSM_TRIG_MASK_2 is shown in and described in .Return to the Summary Table.Summary Table FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_2 Register 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_FSM_MASK_POL GPIO8_FSM_MASK GPIO7_FSM_MASK_POL GPIO7_FSM_MASK GPIO6_FSM_MASK_POL GPIO6_FSM_MASK GPIO5_FSM_MASK_POL GPIO5_FSM_MASK GPIO8_FSM_MASK_POLGPIO8_FSM_MASKGPIO7_FSM_MASK_POLGPIO7_FSM_MASKGPIO6_FSM_MASK_POLGPIO6_FSM_MASKGPIO5_FSM_MASK_POLGPIO5_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 7GPIO8_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 6GPIO8_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 5GPIO7_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 4GPIO7_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 3GPIO6_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 2GPIO6_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 1GPIO5_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0GPIO5_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in . Return to the Summary Table. FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h] FSM_TRIG_MASK_3 is shown in and described in .Return to the Summary Table.Summary Table FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FSM_TRIG_MASK_3 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED GPIO11_FSM_MASK_POL GPIO11_FSM_MASK GPIO10_FSM_MASK_POL GPIO10_FSM_MASK GPIO9_FSM_MASK_POL GPIO9_FSM_MASK RESERVEDGPIO11_FSM_MASK_POLGPIO11_FSM_MASKGPIO10_FSM_MASK_POLGPIO10_FSM_MASKGPIO9_FSM_MASK_POLGPIO9_FSM_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked FSM_TRIG_MASK_3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 GPIO11_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 5GPIO11_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 4GPIO11_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 3 GPIO10_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 3GPIO10_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 2GPIO10_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked 1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 1GPIO9_FSM_MASK_POLR/W0hFSM trigger masking polarity select for GPIOx: (Default from NVM memory) 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0h = Masking sets signal value to '0' 1h = Masking sets signal value to '1' 0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0GPIO9_FSM_MASKR/W0hFSM trigger mask for GPIOx: (Default from NVM memory) 0h = Not masked 1h = Masked 0h = Not masked 1h = Masked MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in . Return to the Summary Table. MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h] MASK_BUCK1_2 is shown in and described in .Return to the Summary Table.Summary Table MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK2_ILIM_MASK RESERVED BUCK2_UV_MASK BUCK2_OV_MASK BUCK1_ILIM_MASK RESERVED BUCK1_UV_MASK BUCK1_OV_MASK BUCK2_ILIM_MASKRESERVEDBUCK2_UV_MASKBUCK2_OV_MASKBUCK1_ILIM_MASKRESERVEDBUCK1_UV_MASKBUCK1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7BUCK2_ILIM_MASKR/W0hMasking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5BUCK2_UV_MASKR/W0hMasking of BUCK2 under-voltage detection interrupt BUCK2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4BUCK2_OV_MASKR/W0hMasking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3BUCK1_ILIM_MASKR/W0hMasking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1BUCK1_UV_MASKR/W0hMasking of BUCK1 under-voltage detection interrupt BUCK1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0BUCK1_OV_MASKR/W0hMasking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in . Return to the Summary Table. MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h] MASK_BUCK3_4 is shown in and described in .Return to the Summary Table.Summary Table MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_ILIM_MASK RESERVED BUCK4_UV_MASK BUCK4_OV_MASK BUCK3_ILIM_MASK RESERVED BUCK3_UV_MASK BUCK3_OV_MASK BUCK4_ILIM_MASKRESERVEDBUCK4_UV_MASKBUCK4_OV_MASKBUCK3_ILIM_MASKRESERVEDBUCK3_UV_MASKBUCK3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7BUCK4_ILIM_MASKR/W0hMasking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5BUCK4_UV_MASKR/W0hMasking of BUCK4 under-voltage detection interrupt BUCK4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4BUCK4_OV_MASKR/W0hMasking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3BUCK3_ILIM_MASKR/W0hMasking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1BUCK3_UV_MASKR/W0hMasking of BUCK3 under-voltage detection interrupt BUCK3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0BUCK3_OV_MASKR/W0hMasking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in . Return to the Summary Table. MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h] MASK_BUCK5 is shown in and described in .Return to the Summary Table.Summary Table MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_ILIM_MASK RESERVED BUCK5_UV_MASK BUCK5_OV_MASK RESERVEDBUCK5_ILIM_MASKRESERVEDBUCK5_UV_MASKBUCK5_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3BUCK5_ILIM_MASKR/W0hMasking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1BUCK5_UV_MASKR/W0hMasking of BUCK5 under-voltage detection interrupt BUCK5_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0BUCK5_OV_MASKR/W0hMasking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in . Return to the Summary Table. MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h] MASK_LDO1_2 is shown in and described in .Return to the Summary Table.Summary Table MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO2_ILIM_MASK RESERVED LDO2_UV_MASK LDO2_OV_MASK LDO1_ILIM_MASK RESERVED LDO1_UV_MASK LDO1_OV_MASK LDO2_ILIM_MASKRESERVEDLDO2_UV_MASKLDO2_OV_MASKLDO1_ILIM_MASKRESERVEDLDO1_UV_MASKLDO1_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7LDO2_ILIM_MASKR/W0hMasking for LDO2 current monitoring interrupt LDO2_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5LDO2_UV_MASKR/W0hMasking of LDO2 under-voltage detection interrupt LDO2_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4LDO2_OV_MASKR/W0hMasking of LDO2 over-voltage detection interrupt LDO2_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3LDO1_ILIM_MASKR/W0hMasking for LDO1 current monitoring interrupt LDO1_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1LDO1_UV_MASKR/W0hMasking of LDO1 under-voltage detection interrupt LDO1_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0LDO1_OV_MASKR/W0hMasking of LDO1 over-voltage detection interrupt LDO1_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in . Return to the Summary Table. MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h] MASK_LDO3_4 is shown in and described in .Return to the Summary Table.Summary Table MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 LDO4_ILIM_MASK RESERVED LDO4_UV_MASK LDO4_OV_MASK LDO3_ILIM_MASK RESERVED LDO3_UV_MASK LDO3_OV_MASK LDO4_ILIM_MASKRESERVEDLDO4_UV_MASKLDO4_OV_MASKLDO3_ILIM_MASKRESERVEDLDO3_UV_MASKLDO3_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7LDO4_ILIM_MASKR/W0hMasking for LDO4 current monitoring interrupt LDO4_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5LDO4_UV_MASKR/W0hMasking of LDO4 under-voltage detection interrupt LDO4_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4LDO4_OV_MASKR/W0hMasking of LDO4 over-voltage detection interrupt LDO4_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3LDO3_ILIM_MASKR/W0hMasking for LDO3 current monitoring interrupt LDO3_ILIM_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1LDO3_UV_MASKR/W0hMasking of LDO3 under-voltage detection interrupt LDO3_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0LDO3_OV_MASKR/W0hMasking of LDO3 over-voltage detection interrupt LDO3_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in . Return to the Summary Table. MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register (Offset = 4Eh) [Reset = 00h] MASK_VMON is shown in and described in .Return to the Summary Table.Summary Table MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h MASK_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_MASK VCCA_OV_MASK R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_UV_MASK VCCA_OV_MASK RESERVEDVCCA_UV_MASKVCCA_OV_MASK R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1VCCA_UV_MASKR/W0hMasking of VCCA under-voltage detection interrupt VCCA_UV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0VCCA_OV_MASKR/W0hMasking of VCCA over-voltage detection interrupt VCCA_OV_INT: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h] MASK_GPIO1_8_FALL is shown in and described in .Return to the Summary Table.Summary Table MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_FALL Register 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_FALL_MASK GPIO7_FALL_MASK GPIO6_FALL_MASK GPIO5_FALL_MASK GPIO4_FALL_MASK GPIO3_FALL_MASK GPIO2_FALL_MASK GPIO1_FALL_MASK GPIO8_FALL_MASKGPIO7_FALL_MASKGPIO6_FALL_MASKGPIO5_FALL_MASKGPIO4_FALL_MASKGPIO3_FALL_MASKGPIO2_FALL_MASKGPIO1_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_FALL Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7GPIO8_FALL_MASKR/W0hMasking of interrupt for GPIO8 low state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6GPIO7_FALL_MASKR/W0hMasking of interrupt for GPIO7 low state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5GPIO6_FALL_MASKR/W0hMasking of interrupt for GPIO6 low state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4GPIO5_FALL_MASKR/W0hMasking of interrupt for GPIO5 low state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3GPIO4_FALL_MASKR/W0hMasking of interrupt for GPIO4 low state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2GPIO3_FALL_MASKR/W0hMasking of interrupt for GPIO3 low state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1GPIO2_FALL_MASKR/W0hMasking of interrupt for GPIO2 low state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0GPIO1_FALL_MASKR/W0hMasking of interrupt for GPIO1 low state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in . Return to the Summary Table. MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h] MASK_GPIO1_8_RISE is shown in and described in .Return to the Summary Table.Summary Table MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO1_8_RISE Register 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_RISE_MASK GPIO7_RISE_MASK GPIO6_RISE_MASK GPIO5_RISE_MASK GPIO4_RISE_MASK GPIO3_RISE_MASK GPIO2_RISE_MASK GPIO1_RISE_MASK GPIO8_RISE_MASKGPIO7_RISE_MASKGPIO6_RISE_MASKGPIO5_RISE_MASKGPIO4_RISE_MASKGPIO3_RISE_MASKGPIO2_RISE_MASKGPIO1_RISE_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO1_8_RISE Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7GPIO8_RISE_MASKR/W0hMasking of interrupt for GPIO8 high state transition: This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6GPIO7_RISE_MASKR/W0hMasking of interrupt for GPIO7 high state transition: This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5GPIO6_RISE_MASKR/W0hMasking of interrupt for GPIO6 high state transition: This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4GPIO5_RISE_MASKR/W0hMasking of interrupt for GPIO5 high state transition: This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3GPIO4_RISE_MASKR/W0hMasking of interrupt for GPIO4 high state transition: This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2GPIO3_RISE_MASKR/W0hMasking of interrupt for GPIO3 high state transition: This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1GPIO2_RISE_MASKR/W0hMasking of interrupt for GPIO2 high state transition: This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0GPIO1_RISE_MASKR/W0hMasking of interrupt for GPIO1 high state transition: This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in . Return to the Summary Table. MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h] MASK_GPIO9_11 is shown in and described in .Return to the Summary Table.Summary Table MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_GPIO9_11 Register 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED GPIO11_RISE_MASK GPIO10_RISE_MASK GPIO9_RISE_MASK GPIO11_FALL_MASK GPIO10_FALL_MASK GPIO9_FALL_MASK RESERVEDGPIO11_RISE_MASKGPIO10_RISE_MASKGPIO9_RISE_MASKGPIO11_FALL_MASKGPIO10_FALL_MASKGPIO9_FALL_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_GPIO9_11 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5GPIO11_RISE_MASKR/W0hMasking of interrupt for GPIO11 high state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4GPIO10_RISE_MASKR/W0hMasking of interrupt for GPIO10 high state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3GPIO9_RISE_MASKR/W0hMasking of interrupt for GPIO9 high state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2GPIO11_FALL_MASKR/W0hMasking of interrupt for GPIO11 low state transition: This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1GPIO10_FALL_MASKR/W0hMasking of interrupt for GPIO10 low state transition: This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0GPIO9_FALL_MASKR/W0hMasking of interrupt for GPIO9 low state transition: This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register. (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in . Return to the Summary Table. MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register (Offset = 52h) [Reset = 00h] MASK_STARTUP is shown in and described in .Return to the Summary Table.Summary Table MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SOFT_REBOOT_MASK FSD_MASK RESERVED ENABLE_MASK NPWRON_START_MASK RESERVEDSOFT_REBOOT_MASKFSD_MASKRESERVEDENABLE_MASKNPWRON_START_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5SOFT_REBOOT_MASKR/W0hMasking of SOFT_REBOOT_MASK interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 FSD_MASK R/W 0h Masking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4FSD_MASKR/W0hMasking of FSD_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3-2 RESERVED R/W 0h 3-2RESERVEDR/W0h 1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1ENABLE_MASKR/W0hMasking of ENABLE_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0NPWRON_START_MASKR/W0hMasking of NPWRON_START_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in . Return to the Summary Table. MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register (Offset = 53h) [Reset = 00h] MASK_MISC is shown in and described in .Return to the Summary Table.Summary Table MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED TWARN_MASK RESERVED EXT_CLK_MASK BIST_PASS_MASK RESERVEDTWARN_MASKRESERVEDEXT_CLK_MASK BIST_PASS_MASK BIST_PASS_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h R/W-0h R/W-0h MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3TWARN_MASKR/W0hMasking of TWARN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1EXT_CLK_MASKR/W0hMasking of EXT_CLK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0BIST_PASS_MASKR/W0hMasking of BIST_PASS_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in . Return to the Summary Table. MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h] MASK_MODERATE_ERR is shown in and described in .Return to the Summary Table.Summary Table MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 NRSTOUT_READBACK_MASK NINT_READBACK_MASK NPWRON_LONG_MASK SPMI_ERR_MASK RESERVED REG_CRC_ERR_MASK BIST_FAIL_MASK RESERVED NRSTOUT_READBACK_MASKNINT_READBACK_MASKNPWRON_LONG_MASKSPMI_ERR_MASKRESERVEDREG_CRC_ERR_MASK BIST_FAIL_MASK BIST_FAIL_MASKRESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h R/W-0h R/W-0hR/W-0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h MASK_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h 7 NRSTOUT_READBACK_MASK R/W 0h Masking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7NRSTOUT_READBACK_MASKR/W0hMasking of NRSTOUT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6NINT_READBACK_MASKR/W0hMasking of NINT_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5NPWRON_LONG_MASKR/W0hMasking of NPWRON_LONG_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4SPMI_ERR_MASKR/W0hMasking of SPMI_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 RESERVED R/W 0h 3RESERVEDR/W0h 2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2REG_CRC_ERR_MASKR/W0hMasking of REG_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1BIST_FAIL_MASKR/W0hMasking of BIST_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 RESERVED R/W 0h 0RESERVEDR/W0h MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in . Return to the Summary Table. MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h] MASK_FSM_ERR is shown in and described in .Return to the Summary Table.Summary Table MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_FSM_ERR Register 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SOC_PWR_ERR_MASK MCU_PWR_ERR_MASK ORD_SHUTDOWN_MASK IMM_SHUTDOWN_MASK RESERVEDSOC_PWR_ERR_MASKMCU_PWR_ERR_MASKORD_SHUTDOWN_MASKIMM_SHUTDOWN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3SOC_PWR_ERR_MASKR/W0hMasking of SOC_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2MCU_PWR_ERR_MASKR/W0hMasking of MCU_PWR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 ORD_SHUTDOWN_MASK R/W 0h Masking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1ORD_SHUTDOWN_MASKR/W0hMasking of ORD_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0IMM_SHUTDOWN_MASKR/W0hMasking of IMM_SHUTDOWN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in . Return to the Summary Table. MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h] MASK_COMM_ERR is shown in and described in .Return to the Summary Table.Summary Table MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 I2C2_ADR_ERR_MASK RESERVED I2C2_CRC_ERR_MASK RESERVED COMM_ADR_ERR_MASK RESERVED COMM_CRC_ERR_MASK COMM_FRM_ERR_MASK I2C2_ADR_ERR_MASK I2C2_ADR_ERR_MASKRESERVED I2C2_CRC_ERR_MASK I2C2_CRC_ERR_MASKRESERVEDCOMM_ADR_ERR_MASKRESERVEDCOMM_CRC_ERR_MASKCOMM_FRM_ERR_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7I2C2_ADR_ERR_MASKR/W0hMasking of I2C2_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5I2C2_CRC_ERR_MASKR/W0hMasking of I2C2_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 RESERVED R/W 0h 4RESERVEDR/W0h 3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3COMM_ADR_ERR_MASKR/W0hMasking of COMM_ADR_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 COMM_CRC_ERR_MASK R/W 0h Masking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1COMM_CRC_ERR_MASKR/W0hMasking of COMM_CRC_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 COMM_FRM_ERR_MASK R/W 0h Masking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0COMM_FRM_ERR_MASKR/W0hMasking of COMM_FRM_ERR_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in . Return to the Summary Table. MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h] MASK_READBACK_ERR is shown in and described in .Return to the Summary Table.Summary Table MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED NRSTOUT_SOC_READBACK_MASK RESERVED EN_DRV_READBACK_MASK RESERVEDNRSTOUT_SOC_READBACK_MASKRESERVED EN_DRV_READBACK_MASK EN_DRV_READBACK_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h R/W-0h R/W-0h MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 NRSTOUT_SOC_READBACK_MASK R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3NRSTOUT_SOC_READBACK_MASKR/W0hMasking of NRSTOUT_SOC_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2-1 RESERVED R/W 0h 2-1RESERVEDR/W0h 0 EN_DRV_READBACK_MASK R/W 0h Masking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0EN_DRV_READBACK_MASKR/W0hMasking of EN_DRV_READBACK_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in . Return to the Summary Table. MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register (Offset = 59h) [Reset = 00h] MASK_ESM is shown in and described in .Return to the Summary Table.Summary Table MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MASK_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_MCU_RST_MASK ESM_MCU_FAIL_MASK ESM_MCU_PIN_MASK ESM_SOC_RST_MASK ESM_SOC_FAIL_MASK ESM_SOC_PIN_MASK RESERVEDESM_MCU_RST_MASKESM_MCU_FAIL_MASKESM_MCU_PIN_MASKESM_SOC_RST_MASKESM_SOC_FAIL_MASKESM_SOC_PIN_MASK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. MASK_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 5ESM_MCU_RST_MASKR/W0hMasking of ESM_MCU_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 4ESM_MCU_FAIL_MASKR/W0hMasking of ESM_MCU_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 3ESM_MCU_PIN_MASKR/W0hMasking of ESM_MCU_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 2ESM_SOC_RST_MASKR/W0hMasking of ESM_SOC_RST_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 1ESM_SOC_FAIL_MASKR/W0hMasking of ESM_SOC_FAIL_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. 0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0ESM_SOC_PIN_MASKR/W0hMasking of ESM_SOC_PIN_INT interrupt: (Default from NVM memory) 0h = Interrupt generated 1h = Interrupt not generated. 0h = Interrupt generated 1h = Interrupt not generated. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in . Return to the Summary Table. INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_TOP Register (Offset = 5Ah) [Reset = 00h] INT_TOP is shown in and described in .Return to the Summary Table.Summary Table INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h INT_TOP Register 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 FSM_ERR_INT SEVERE_ERR_INT MODERATE_ERR_INT MISC_INT STARTUP_INT GPIO_INT LDO_VMON_INT BUCK_INT FSM_ERR_INTSEVERE_ERR_INTMODERATE_ERR_INTMISC_INTSTARTUP_INTGPIO_INTLDO_VMON_INTBUCK_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_TOP Register Field Descriptions Bit Field Type Reset Description 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. 7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 7FSM_ERR_INTR0hInterrupt indicating that INT_FSM_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_FSM_ERR register. This bit is cleared automatically when INT_FSM_ERR register is cleared to 0x00. 6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 6SEVERE_ERR_INTR0hInterrupt indicating that INT_SEVERE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_SEVERE_ERR register. This bit is cleared automatically when INT_SEVERE_ERR register is cleared to 0x00. 5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 5MODERATE_ERR_INTR0hInterrupt indicating that INT_MODERATE_ERR register has pending interrupt. The reason for the interrupt is indicated in INT_MODERATE_ERR register. This bit is cleared automatically when INT_MODERATE_ERR register is cleared to 0x00. 4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 4MISC_INTR0hInterrupt indicating that INT_MISC register has pending interrupt. The reason for the interrupt is indicated in INT_MISC register. This bit is cleared automatically when INT_MISC register is cleared to 0x00. 3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 3STARTUP_INTR0hInterrupt indicating that INT_STARTUP register has pending interrupt. The reason for the interrupt is indicated in INT_STARTUP register. This bit is cleared automatically when INT_STARTUP register is cleared to 0x00. 2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 2GPIO_INTR0hInterrupt indicating that INT_GPIO register has pending interrupt. The reason for the interrupt is indicated in INT_GPIO register. This bit is cleared automatically when INT_GPIO register is cleared to 0x00. 1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 1LDO_VMON_INTR0hInterrupt indicating that INT_LDO_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_LDO_VMON register. This bit is cleared automatically when INT_LDO_VMON register is cleared to 0x00. 0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. 0BUCK_INTR0hInterrupt indicating that INT_BUCK register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in . Return to the Summary Table. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK Register (Offset = 5Bh) [Reset = 00h] INT_BUCK is shown in and described in .Return to the Summary Table.Summary Table INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT RESERVEDBUCK5_INTBUCK3_4_INTBUCK1_2_INT R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0h INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R 0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. 7-3 RESERVED R 0h 7-3RESERVEDR0h 2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 2BUCK5_INTR0hInterrupt indicating that INT_BUCK5 register has pending interrupt. The reason for the interrupt is indicated in INT_BUCK5 register. This bit is cleared automatically when INT_BUCK5 register is cleared to 0x00. 1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 1BUCK3_4_INTR0hInterrupt indicating that INT_BUCK3_4 register has pending interrupt. This bit is cleared automatically when INT_BUCK3_4 register is cleared to 0x00. 0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. 0BUCK1_2_INTR0hInterrupt indicating that INT_BUCK1_2 register has pending interrupt. This bit is cleared automatically when INT_BUCK1_2 register is cleared to 0x00. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in . Return to the Summary Table. INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h] INT_BUCK1_2 is shown in and described in .Return to the Summary Table.Summary Table INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT BUCK2_ILIM_INTBUCK2_SC_INTBUCK2_UV_INTBUCK2_OV_INTBUCK1_ILIM_INTBUCK1_SC_INTBUCK1_UV_INTBUCK1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. 7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 7BUCK2_ILIM_INTR/W1C0hLatched status bit indicating that BUCK2 output current limit has been triggered. Write 1 to clear. 6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 6BUCK2_SC_INTR/W1C0hLatched status bit indicating that the BUCK2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 5BUCK2_UV_INTR/W1C0hLatched status bit indicating that BUCK2 output under-voltage has been detected. Write 1 to clear. 4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 4BUCK2_OV_INTR/W1C0hLatched status bit indicating that BUCK2 output over-voltage has been detected. Write 1 to clear. 3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 3BUCK1_ILIM_INTR/W1C0hLatched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 2BUCK1_SC_INTR/W1C0hLatched status bit indicating that the BUCK1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 1BUCK1_UV_INTR/W1C0hLatched status bit indicating that BUCK1 output under-voltage has been detected. Write 1 to clear. 0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. 0BUCK1_OV_INTR/W1C0hLatched status bit indicating that BUCK1 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in . Return to the Summary Table. INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h] INT_BUCK3_4 is shown in and described in .Return to the Summary Table.Summary Table INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT BUCK4_ILIM_INTBUCK4_SC_INTBUCK4_UV_INTBUCK4_OV_INTBUCK3_ILIM_INTBUCK3_SC_INTBUCK3_UV_INTBUCK3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. 7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 7BUCK4_ILIM_INTR/W1C0hLatched status bit indicating that BUCK4 output current limit has been triggered. Write 1 to clear. 6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 6BUCK4_SC_INTR/W1C0hLatched status bit indicating that the BUCK4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 5BUCK4_UV_INTR/W1C0hLatched status bit indicating that BUCK4 output under-voltage has been detected. Write 1 to clear. 4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 4BUCK4_OV_INTR/W1C0hLatched status bit indicating that BUCK4 output over-voltage has been detected. Write 1 to clear. 3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 3BUCK3_ILIM_INTR/W1C0hLatched status bit indicating that BUCK3 output current limit has been triggered. Write 1 to clear. 2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 2BUCK3_SC_INTR/W1C0hLatched status bit indicating that the BUCK3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 1BUCK3_UV_INTR/W1C0hLatched status bit indicating that BUCK3 output under-voltage has been detected. Write 1 to clear. 0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. 0BUCK3_OV_INTR/W1C0hLatched status bit indicating that BUCK3 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in . Return to the Summary Table. INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h] INT_BUCK5 is shown in and described in .Return to the Summary Table.Summary Table INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT RESERVEDBUCK5_ILIM_INTBUCK5_SC_INTBUCK5_UV_INTBUCK5_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 3BUCK5_ILIM_INTR/W1C0hLatched status bit indicating that BUCK5 output current limit has been triggered. Write 1 to clear. 2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 2BUCK5_SC_INTR/W1C0hLatched status bit indicating that the BUCK5 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 1BUCK5_UV_INTR/W1C0hLatched status bit indicating that BUCK5 output under-voltage has been detected. Write 1 to clear. 0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. 0BUCK5_OV_INTR/W1C0hLatched status bit indicating that BUCK5 output over-voltage has been detected. Write 1 to clear. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in . Return to the Summary Table. INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h] INT_LDO_VMON is shown in and described in .Return to the Summary Table.Summary Table INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h INT_LDO_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT RESERVEDVCCA_INTRESERVEDLDO3_4_INTLDO1_2_INT R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0h INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO_VMON Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R 0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. 7-5 RESERVED R 0h 7-5RESERVEDR0h 4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 4VCCA_INTR0hInterrupt indicating that INT_VMON register has pending interrupt. The reason for the interrupt is indicated in INT_VMON register. This bit is cleared automatically when INT_VMON register is cleared to 0x00. 3-2 RESERVED R 0h 3-2RESERVEDR0h 1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 1LDO3_4_INTR0hInterrupt indicating that INT_LDO3_4 register has pending interrupt. This bit is cleared automatically when INT_LDO3_4 register is cleared to 0x00. 0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. 0LDO1_2_INTR0hInterrupt indicating that INT_LDO1_2 register has pending interrupt. This bit is cleared automatically when INT_LDO1_2 register is cleared to 0x00. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in . Return to the Summary Table. INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO1_2 Register (Offset = 60h) [Reset = 00h] INT_LDO1_2 is shown in and described in .Return to the Summary Table.Summary Table INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT LDO2_ILIM_INTLDO2_SC_INTLDO2_UV_INTLDO2_OV_INTLDO1_ILIM_INTLDO1_SC_INTLDO1_UV_INTLDO1_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. 7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 7LDO2_ILIM_INTR/W1C0hLatched status bit indicating that LDO2 output current limit has been triggered. Write 1 to clear. 6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 6LDO2_SC_INTR/W1C0hLatched status bit indicating that LDO2 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 5LDO2_UV_INTR/W1C0hLatched status bit indicating that LDO2 output under-voltage has been detected. Write 1 to clear. 4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 4LDO2_OV_INTR/W1C0hLatched status bit indicating that LDO2 output over-voltage has been detected. Write 1 to clear. 3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 3LDO1_ILIM_INTR/W1C0hLatched status bit indicating that LDO1 output current limit has been triggered. Write 1 to clear. 2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 2LDO1_SC_INTR/W1C0hLatched status bit indicating that LDO1 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 1LDO1_UV_INTR/W1C0hLatched status bit indicating that LDO1 output under-voltage has been detected. Write 1 to clear. 0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. 0LDO1_OV_INTR/W1C0hLatched status bit indicating that LDO1 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in . Return to the Summary Table. INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register (Offset = 61h) [Reset = 00h] INT_LDO3_4 is shown in and described in .Return to the Summary Table.Summary Table INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT LDO4_ILIM_INTLDO4_SC_INTLDO4_UV_INTLDO4_OV_INTLDO3_ILIM_INTLDO3_SC_INTLDO3_UV_INTLDO3_OV_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. 7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 7LDO4_ILIM_INTR/W1C0hLatched status bit indicating that LDO4 output current limit has been triggered. Write 1 to clear. 6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 6LDO4_SC_INTR/W1C0hLatched status bit indicating that LDO4 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 5LDO4_UV_INTR/W1C0hLatched status bit indicating that LDO4 output under-voltage has been detected. Write 1 to clear. 4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 4LDO4_OV_INTR/W1C0hLatched status bit indicating that LDO4 output over-voltage has been detected. Write 1 to clear. 3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 3LDO3_ILIM_INTR/W1C0hLatched status bit indicating that LDO3 output current limit has been triggered. Write 1 to clear. 2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 2LDO3_SC_INTR/W1C0hLatched status bit indicating that LDO3 output voltage has fallen below 150 mV level during operation. Write 1 to clear. 1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 1LDO3_UV_INTR/W1C0hLatched status bit indicating that LDO3 output under-voltage has been detected. Write 1 to clear. 0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. 0LDO3_OV_INTR/W1C0hLatched status bit indicating that LDO3 output over-voltage has been detected. Write 1 to clear. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in . Return to the Summary Table. INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_VMON Register (Offset = 62h) [Reset = 00h] INT_VMON is shown in and described in .Return to the Summary Table.Summary Table INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h INT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_INT VCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_UV_INT VCCA_OV_INT RESERVEDVCCA_UV_INTVCCA_OV_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W1C-0h INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 1VCCA_UV_INTR/W1C0hLatched status bit indicating that the VCCA input voltage has decreased below the under-voltage monitoring level. The actual status of the VCCA under-voltage monitoring is indicated by VCCA_UV_STAT bit. Write 1 to clear interrupt. 0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. 0VCCA_OV_INTR/W1C0hLatched status bit indicating that the VCCA input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by VCCA_OV_STAT bit. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in . Return to the Summary Table. INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO Register (Offset = 63h) [Reset = 00h] INT_GPIO is shown in and described in .Return to the Summary Table.Summary Table INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO Register 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT RESERVEDGPIO1_8_INTGPIO11_INTGPIO10_INTGPIO9_INT R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 3GPIO1_8_INTR0hInterrupt indicating that INT_GPIO1_8 has pending interrupt. The reason for the interrupt is indicated in INT_GPIO1_8 register. This bit is cleared automatically when INT_GPIO1_8 register is cleared to 0x00. 2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 2GPIO11_INTR/W1C0hLatched status bit indicating that GPIO11 has pending interrupt. GPIO11_IN bit in GPIO_IN_2 register shows the status of the GPIO11 signal. Write 1 to clear interrupt. 1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 1GPIO10_INTR/W1C0hLatched status bit indicating that GPIO10 has pending interrupt. GPIO10_IN bit in GPIO_IN_2 register shows the status of the GPIO10 signal. Write 1 to clear interrupt. 0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. 0GPIO9_INTR/W1C0hLatched status bit indicating that GPIO9 has pending interrupt. GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in . Return to the Summary Table. INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h] INT_GPIO1_8 is shown in and described in .Return to the Summary Table.Summary Table INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_GPIO1_8 Register 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT GPIO8_INTGPIO7_INTGPIO6_INTGPIO5_INTGPIO4_INTGPIO3_INTGPIO2_INTGPIO1_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_GPIO1_8 Register Field Descriptions Bit Field Type Reset Description 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. 7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 7GPIO8_INTR/W1C0hLatched status bit indicating that GPIO8 has has pending interrupt. GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8 signal. Write 1 to clear interrupt. 6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 6GPIO7_INTR/W1C0hLatched status bit indicating that GPIO7 has has pending interrupt. GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7 signal. Write 1 to clear interrupt. 5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 5GPIO6_INTR/W1C0hLatched status bit indicating that GPIO6 has has pending interrupt. GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6 signal. Write 1 to clear interrupt. 4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 4GPIO5_INTR/W1C0hLatched status bit indicating that GPIO5 has has pending interrupt. GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5 signal. Write 1 to clear interrupt. 3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 3GPIO4_INTR/W1C0hLatched status bit indicating that GPIO4 has has pending interrupt. GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4 signal. Write 1 to clear interrupt. 2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 2GPIO3_INTR/W1C0hLatched status bit indicating that GPIO3 has has pending interrupt. GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3 signal. Write 1 to clear interrupt. 1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 1GPIO2_INTR/W1C0hLatched status bit indicating that GPIO2 has pending interrupt. GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2 signal. Write 1 to clear interrupt. 0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. 0GPIO1_INTR/W1C0hLatched status bit indicating that GPIO1 has pending interrupt. GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1 signal. Write 1 to clear interrupt. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in . Return to the Summary Table. INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_STARTUP Register (Offset = 65h) [Reset = 00h] INT_STARTUP is shown in and described in .Return to the Summary Table.Summary Table INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h INT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SOFT_REBOOT_INT FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_START_INT RESERVEDSOFT_REBOOT_INTFSD_INTRESERVEDRTC_INTENABLE_INTNPWRON_START_INT R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W1C-0hR/W-0hR-0hR/W1C-0hR/W1C-0h INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been detected. Write 1 to clear. 5SOFT_REBOOT_INTR/W1C0hLatched status bit indicating that soft reboot event has been detected. Write 1 to clear. 4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 4FSD_INTR/W1C0hLatched status bit indicating that PMIC has started from NO_SUPPLY or BACKUP state (first supply dectection). Write 1 to clear. 3 RESERVED R/W 0h 3RESERVEDR/W0h 2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 2RTC_INTR0hLatched status bit indicating that RTC_STATUS register has pending interrupt. This bit is cleared automatically when ALARM and TIMER interrupts are cleared. 1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 1ENABLE_INTR/W1C0hLatched status bit indicating that ENABLE pin active event has been detected. Write 1 to clear. 0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. 0NPWRON_START_INTR/W1C0hLatched status bit indicating that NPWRON start-up event has been detected. Write 1 to clear. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in . Return to the Summary Table. INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MISC Register (Offset = 66h) [Reset = 00h] INT_MISC is shown in and described in .Return to the Summary Table.Summary Table INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_INT RESERVEDTWARN_INTRESERVEDEXT_CLK_INT BIST_PASS_INT BIST_PASS_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W-0hR/W1C-0h R/W1C-0h R/W1C-0h INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 3TWARN_INTR/W1C0hLatched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TWARN_STAT bit in STAT_MISC register. Write 1 to clear interrupt. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 1EXT_CLK_INTR/W1C0hLatched status bit indicating that external clock is not valid. Internal clock is automatically taken into use. Write 1 to clear. 0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. 0BIST_PASS_INTR/W1C0hLatched status bit indicating that BOOT_BIST or RUNTIME_BSIT has been completed. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in . Return to the Summary Table. INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h] INT_MODERATE_ERR is shown in and described in .Return to the Summary Table.Summary Table INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 NRSTOUT_READBACK_INT NINT_READBACK_INT NPWRON_LONG_INT SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL_INT TSD_ORD_INT NRSTOUT_READBACK_INTNINT_READBACK_INTNPWRON_LONG_INTSPMI_ERR_INTRECOV_CNT_INTREG_CRC_ERR_INT BIST_FAIL_INT BIST_FAIL_INTTSD_ORD_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0h INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. 7 NRSTOUT_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 7NRSTOUT_READBACK_INTR/W1C0hLatched status bit indicating that NRSTOUT readback error has been detected. Write 1 to clear interrupt. 6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 6NINT_READBACK_INTR/W1C0hLatched status bit indicating that NINT readback error has been detected. Write 1 to clear interrupt. 5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 5NPWRON_LONG_INTR/W1C0hLatched status bit indicating that NPWRON long press has been detected. Write 1 to clear. 4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 4SPMI_ERR_INTR/W1C0hLatched status bit indicating that the SPMI communication interface has detected an error. Write 1 to clear interrupt. 3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 3RECOV_CNT_INTR/W1C0hLatched status bit indicating that RECOV_CNT has reached the limit (RECOV_CNT_THR). Write 1 to clear. 2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 2REG_CRC_ERR_INTR/W1C0hLatched status bit indicating that the register CRC checking has detected an error. Write 1 to clear interrupt. 1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 1BIST_FAIL_INTR/W1C0hLatched status bit indicating that the BOOT_BIST or RUNTIME_BIST has detected an error. Write 1 to clear interrupt. 0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. 0TSD_ORD_INTR/W1C0hLatched status bit indicating that the die junction temperature has exceeded the thermal level causing a sequenced shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_ORD_STAT bit in STAT_MODERATE_ERR register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in . Return to the Summary Table. INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h] INT_SEVERE_ERR is shown in and described in .Return to the Summary Table.Summary Table INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT RESERVEDPFSM_ERR_INTVCCA_OVP_INTTSD_IMM_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R/W 0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. 7-3 RESERVED R/W 0h 7-3RESERVEDR/W0h 2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 2PFSM_ERR_INTR/W1C0hLatched status bit indicating that the PFSM sequencer has detected an error. Write 1 to clear interrupt. 1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 1VCCA_OVP_INTR/W1C0hLatched status bit indicating that the VCCA input voltage has exceeded the over-voltage threshold level causing an immediate shutdown. The regulators have been disabled. Write 1 to clear interrupt. 0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. 0TSD_IMM_INTR/W1C0hLatched status bit indicating that the die junction temperature has exceeded the thermal level causing an immediate shutdown. The regulators have been disabled. The regulators cannot be enabled if this bit is active. The actual status of the temperature is indicated by TSD_IMM_STAT bit in THER_CLK_STATUS register. Write 1 to clear interrupt. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in . Return to the Summary Table. INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_FSM_ERR Register (Offset = 69h) [Reset = 00h] INT_FSM_ERR is shown in and described in .Return to the Summary Table.Summary Table INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_FSM_ERR Register 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 WD_INT ESM_INT READBACK_ERR_INT COMM_ERR_INT SOC_PWR_ERR_INT MCU_PWR_ERR_INT ORD_SHUTDOWN_INT IMM_SHUTDOWN_INT WD_INT ESM_INT ESM_INTREADBACK_ERR_INTCOMM_ERR_INTSOC_PWR_ERR_INTMCU_PWR_ERR_INTORD_SHUTDOWN_INTIMM_SHUTDOWN_INT R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R-0h R-0h R-0hR-0hR-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_FSM_ERR Register Field Descriptions Bit Field Type Reset Description 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. 7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 7WD_INTR0hInterrupt indicating that WD_ERR_STATUS register has pending interrupt. This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT and WD_LONGWIN_TIMEOUT_INT are cleared. 6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 6ESM_INTR0hInterrupt indicating that INT_ESM has pending interrupt. This bit is cleared automatically when INT_ESM register is cleared to 0x00. 5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 5READBACK_ERR_INTR0hInterrupt indicating that INT_READBACK_ERR has pending interrupt. This bit is cleared automatically when INT_READBACK_ERR register is cleared to 0x00. 4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 4COMM_ERR_INTR0hInterrupt indicating that INT_COMM_ERR has pending interrupt. The reason for the interrupt is indicated in INT_COMM_ERR register. This bit is cleared automatically when INT_COMM_ERR register is cleared to 0x00. 3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been detected. Write 1 to clear. 3SOC_PWR_ERR_INTR/W1C0hLatched status bit indicating that SOC power error has been detected. Write 1 to clear. 2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been detected. Write 1 to clear. 2MCU_PWR_ERR_INTR/W1C0hLatched status bit indicating that MCU power error has been detected. Write 1 to clear. 1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 1ORD_SHUTDOWN_INTR/W1C0hLatched status bit indicating that orderly shutdown has been detected. Write 1 to clear. 0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been detected. Write 1 to clear. 0IMM_SHUTDOWN_INTR/W1C0hLatched status bit indicating that immediate shutdown has been detected. Write 1 to clear. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in . Return to the Summary Table. INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h] INT_COMM_ERR is shown in and described in .Return to the Summary Table.Summary Table INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h INT_COMM_ERR Register 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 I2C2_ADR_ERR_INT RESERVED I2C2_CRC_ERR_INT RESERVED COMM_ADR_ERR_INT RESERVED COMM_CRC_ERR_INT COMM_FRM_ERR_INT I2C2_ADR_ERR_INT I2C2_ADR_ERR_INTRESERVED I2C2_CRC_ERR_INT I2C2_CRC_ERR_INTRESERVEDCOMM_ADR_ERR_INTRESERVEDCOMM_CRC_ERR_INTCOMM_FRM_ERR_INT R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W-0h R/W1C-0h R/W1C-0hR/W-0hR/W1C-0hR/W-0hR/W1C-0hR/W1C-0h INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_COMM_ERR Register Field Descriptions Bit Field Type Reset Description 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. 7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 7I2C2_ADR_ERR_INTR/W1C0hLatched status bit indicating that I2C2 write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 6 RESERVED R/W 0h 6RESERVEDR/W0h 5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 5I2C2_CRC_ERR_INTR/W1C0hLatched status bit indicating that I2C2 CRC error has been detected. Write 1 to clear interrupt. 4 RESERVED R/W 0h 4RESERVEDR/W0h 3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 3COMM_ADR_ERR_INTR/W1C0hLatched status bit indicating that I2C1/SPI write to non-existing, protected or read-only register address has been detected. Write 1 to clear interrupt. 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 1COMM_CRC_ERR_INTR/W1C0hLatched status bit indicating that I2C1/SPI CRC error has been detected. Write 1 to clear interrupt. 0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. 0COMM_FRM_ERR_INTR/W1C0hLatched status bit indicating that SPI frame error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in . Return to the Summary Table. INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h] INT_READBACK_ERR is shown in and described in .Return to the Summary Table.Summary Table INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h INT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED NRSTOUT_SOC_READBACK_INT RESERVED EN_DRV_READBACK_INT RESERVEDNRSTOUT_SOC_READBACK_INTRESERVED EN_DRV_READBACK_INT EN_DRV_READBACK_INT R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0hR/W1C-0hR/W-0h R/W1C-0h R/W1C-0h INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 NRSTOUT_SOC_READBACK_INT R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 3NRSTOUT_SOC_READBACK_INTR/W1C0hLatched status bit indicating that NRSTOUT_SOC readback error has been detected. Write 1 to clear interrupt. 2-1 RESERVED R/W 0h 2-1RESERVEDR/W0h 0 EN_DRV_READBACK_INT R/W1C 0h Latched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. 0EN_DRV_READBACK_INTR/W1C0hLatched status bit indicating that EN_DRV readback error has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in . Return to the Summary Table. INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. INT_ESM Register (Offset = 6Ch) [Reset = 00h] INT_ESM is shown in and described in .Return to the Summary Table.Summary Table INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h INT_ESM Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_MCU_RST_INT ESM_MCU_FAIL_INT ESM_MCU_PIN_INT ESM_SOC_RST_INT ESM_SOC_FAIL_INT ESM_SOC_PIN_INT RESERVEDESM_MCU_RST_INTESM_MCU_FAIL_INTESM_MCU_PIN_INTESM_SOC_RST_INTESM_SOC_FAIL_INTESM_SOC_PIN_INT R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. INT_ESM Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 5ESM_MCU_RST_INTR/W1C0hLatched status bit indicating that MCU ESM reset has been detected. Write 1 to clear interrupt. 4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 4ESM_MCU_FAIL_INTR/W1C0hLatched status bit indicating that MCU ESM fail has been detected. Write 1 to clear interrupt. 3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 3ESM_MCU_PIN_INTR/W1C0hLatched status bit indicating that MCU ESM fault has been detected. Write 1 to clear interrupt. 2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 2ESM_SOC_RST_INTR/W1C0hLatched status bit indicating that SOC ESM reset has been detected. Write 1 to clear interrupt. 1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 1ESM_SOC_FAIL_INTR/W1C0hLatched status bit indicating that SOC ESM fail has been detected. Write 1 to clear interrupt. 0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. 0ESM_SOC_PIN_INTR/W1C0hLatched status bit indicating that SOC ESM fault has been detected. Write 1 to clear interrupt. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in . Return to the Summary Table. STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h] STAT_BUCK1_2 is shown in and described in .Return to the Summary Table.Summary Table STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK1_2 Register 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 BUCK2_ILIM_STAT RESERVED BUCK2_UV_STAT BUCK2_OV_STAT BUCK1_ILIM_STAT RESERVED BUCK1_UV_STAT BUCK1_OV_STAT BUCK2_ILIM_STATRESERVEDBUCK2_UV_STATBUCK2_OV_STATBUCK1_ILIM_STATRESERVEDBUCK1_UV_STATBUCK1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK1_2 Register Field Descriptions Bit Field Type Reset Description 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. 7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit level. 7BUCK2_ILIM_STATR0hStatus bit indicating that BUCK2 output current is above current limit level. 6 RESERVED R 0h 6RESERVEDR0h 5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-voltage threshold. 5BUCK2_UV_STATR0hStatus bit indicating that BUCK2 output voltage is below under-voltage threshold. 4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage threshold. 4BUCK2_OV_STATR0hStatus bit indicating that BUCK2 output voltage is above over-voltage threshold. 3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit level. 3BUCK1_ILIM_STATR0hStatus bit indicating that BUCK1 output current is above current limit level. 2 RESERVED R 0h 2RESERVEDR0h 1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-voltage threshold. 1BUCK1_UV_STATR0hStatus bit indicating that BUCK1 output voltage is below under-voltage threshold. 0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage threshold. 0BUCK1_OV_STATR0hStatus bit indicating that BUCK1 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in . Return to the Summary Table. STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h] STAT_BUCK3_4 is shown in and described in .Return to the Summary Table.Summary Table STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_BUCK3_4 Register 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 BUCK4_ILIM_STAT RESERVED BUCK4_UV_STAT BUCK4_OV_STAT BUCK3_ILIM_STAT RESERVED BUCK3_UV_STAT BUCK3_OV_STAT BUCK4_ILIM_STATRESERVEDBUCK4_UV_STATBUCK4_OV_STATBUCK3_ILIM_STATRESERVEDBUCK3_UV_STATBUCK3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK3_4 Register Field Descriptions Bit Field Type Reset Description 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. 7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit level. 7BUCK4_ILIM_STATR0hStatus bit indicating that BUCK4 output current is above current limit level. 6 RESERVED R 0h 6RESERVEDR0h 5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-voltage threshold. 5BUCK4_UV_STATR0hStatus bit indicating that BUCK4 output voltage is below under-voltage threshold. 4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage threshold. 4BUCK4_OV_STATR0hStatus bit indicating that BUCK4 output voltage is above over-voltage threshold. 3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit level. 3BUCK3_ILIM_STATR0hStatus bit indicating that BUCK3 output current is above current limit level. 2 RESERVED R 0h 2RESERVEDR0h 1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-voltage threshold. 1BUCK3_UV_STATR0hStatus bit indicating that BUCK3 output voltage is below under-voltage threshold. 0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage threshold. 0BUCK3_OV_STATR0hStatus bit indicating that BUCK3 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in . Return to the Summary Table. STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h] STAT_BUCK5 is shown in and described in .Return to the Summary Table.Summary Table STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h STAT_BUCK5 Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_ILIM_STAT RESERVED BUCK5_UV_STAT BUCK5_OV_STAT RESERVEDBUCK5_ILIM_STATRESERVEDBUCK5_UV_STATBUCK5_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0h STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_BUCK5 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R 0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. 7-4 RESERVED R 0h 7-4RESERVEDR0h 3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit level. 3BUCK5_ILIM_STATR0hStatus bit indicating that BUCK5 output current is above current limit level. 2 RESERVED R 0h 2RESERVEDR0h 1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-voltage threshold. 1BUCK5_UV_STATR0hStatus bit indicating that BUCK5 output voltage is below under-voltage threshold. 0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage threshold. 0BUCK5_OV_STATR0hStatus bit indicating that BUCK5 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in . Return to the Summary Table. STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h] STAT_LDO1_2 is shown in and described in .Return to the Summary Table.Summary Table STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO1_2 Register 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 LDO2_ILIM_STAT RESERVED LDO2_UV_STAT LDO2_OV_STAT LDO1_ILIM_STAT RESERVED LDO1_UV_STAT LDO1_OV_STAT LDO2_ILIM_STATRESERVEDLDO2_UV_STATLDO2_OV_STATLDO1_ILIM_STATRESERVEDLDO1_UV_STATLDO1_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO1_2 Register Field Descriptions Bit Field Type Reset Description 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. 7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit level. 7LDO2_ILIM_STATR0hStatus bit indicating that LDO2 output current is above current limit level. 6 RESERVED R 0h 6RESERVEDR0h 5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage threshold. 5LDO2_UV_STATR0hStatus bit indicating that LDO2 output voltage is below under-voltage threshold. 4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage threshold. 4LDO2_OV_STATR0hStatus bit indicating that LDO2 output voltage is above over-voltage threshold. 3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit level. 3LDO1_ILIM_STATR0hStatus bit indicating that LDO1 output current is above current limit level. 2 RESERVED R 0h 2RESERVEDR0h 1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage threshold. 1LDO1_UV_STATR0hStatus bit indicating that LDO1 output voltage is below under-voltage threshold. 0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage threshold. 0LDO1_OV_STATR0hStatus bit indicating that LDO1 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in . Return to the Summary Table. STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h] STAT_LDO3_4 is shown in and described in .Return to the Summary Table.Summary Table STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h STAT_LDO3_4 Register 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 LDO4_ILIM_STAT RESERVED LDO4_UV_STAT LDO4_OV_STAT LDO3_ILIM_STAT RESERVED LDO3_UV_STAT LDO3_OV_STAT LDO4_ILIM_STATRESERVEDLDO4_UV_STATLDO4_OV_STATLDO3_ILIM_STATRESERVEDLDO3_UV_STATLDO3_OV_STAT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_LDO3_4 Register Field Descriptions Bit Field Type Reset Description 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. 7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit level. 7LDO4_ILIM_STATR0hStatus bit indicating that LDO4 output current is above current limit level. 6 RESERVED R 0h 6RESERVEDR0h 5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage threshold. 5LDO4_UV_STATR0hStatus bit indicating that LDO4 output voltage is below under-voltage threshold. 4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage threshold. 4LDO4_OV_STATR0hStatus bit indicating that LDO4 output voltage is above over-voltage threshold. 3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit level. 3LDO3_ILIM_STATR0hStatus bit indicating that LDO3 output current is above current limit level. 2 RESERVED R 0h 2RESERVEDR0h 1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage threshold. 1LDO3_UV_STATR0hStatus bit indicating that LDO3 output voltage is below under-voltage threshold. 0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage threshold. 0LDO3_OV_STATR0hStatus bit indicating that LDO3 output voltage is above over-voltage threshold. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in . Return to the Summary Table. STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_VMON Register (Offset = 72h) [Reset = 00h] STAT_VMON is shown in and described in .Return to the Summary Table.Summary Table STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h STAT_VMON Register 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_UV_STAT VCCA_OV_STAT R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_UV_STAT VCCA_OV_STAT RESERVEDVCCA_UV_STATVCCA_OV_STAT R-0h R-0h R-0h R-0hR-0hR-0h STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. STAT_VMON Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R 0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. 7-2 RESERVED R 0h 7-2RESERVEDR0h 1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage level. 1VCCA_UV_STATR0hStatus bit indicating that VCCA input voltage is below under-voltage level. 0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage level. 0VCCA_OV_STATR0hStatus bit indicating that VCCA input voltage is above over-voltage level. STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in . Return to the Summary Table. STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_STARTUP Register (Offset = 73h) [Reset = 00h] STAT_STARTUP is shown in and described in .Return to the Summary Table.Summary Table STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h STAT_STARTUP Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED ENABLE_STAT RESERVED R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ENABLE_STAT RESERVED RESERVEDENABLE_STATRESERVED R-0h R-0h R-0h R-0hR-0hR-0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h STAT_STARTUP Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R 0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 0 RESERVED R 0h 7-2 RESERVED R 0h 7-2RESERVEDR0h 1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status 1ENABLE_STATR0hStatus bit indicating nPWRON / EN pin status 0 RESERVED R 0h 0RESERVEDR0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in . Return to the Summary Table. STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MISC Register (Offset = 74h) [Reset = 00h] STAT_MISC is shown in and described in .Return to the Summary Table.Summary Table STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h STAT_MISC Register 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED TWARN_STAT RESERVED EXT_CLK_STAT RESERVED RESERVEDTWARN_STATRESERVEDEXT_CLK_STATRESERVED R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0hR-0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h STAT_MISC Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R 0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 0 RESERVED R 0h 7-4 RESERVED R 0h 7-4RESERVEDR0h 3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the thermal warning level. 3TWARN_STATR0hStatus bit indicating that die junction temperature is above the thermal warning level. 2 RESERVED R 0h 2RESERVEDR0h 1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid. 1EXT_CLK_STATR0hStatus bit indicating that external clock is not valid. 0 RESERVED R 0h 0RESERVEDR0h STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in . Return to the Summary Table. STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h] STAT_MODERATE_ERR is shown in and described in .Return to the Summary Table.Summary Table STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h STAT_MODERATE_ERR Register 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED TSD_ORD_STAT R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED TSD_ORD_STAT RESERVEDTSD_ORD_STAT R-0h R-0h R-0hR-0h STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_MODERATE_ERR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R 0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. 7-1 RESERVED R 0h 7-1RESERVEDR0h 0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. 0TSD_ORD_STATR0hStatus bit indicating that the die junction temperature is above the thermal level causing a sequenced shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in . Return to the Summary Table. STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h] STAT_SEVERE_ERR is shown in and described in .Return to the Summary Table.Summary Table STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h STAT_SEVERE_ERR Register 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED VCCA_OVP_STAT TSD_IMM_STAT R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED VCCA_OVP_STAT TSD_IMM_STAT RESERVEDVCCA_OVP_STATTSD_IMM_STAT R-0h R-0h R-0h R-0hR-0hR-0h STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_SEVERE_ERR Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R 0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. 7-2 RESERVED R 0h 7-2RESERVEDR0h 1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage protection level. 1VCCA_OVP_STATR0hStatus bit indicating that the VCCA voltage is above overvoltage protection level. 0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. 0TSD_IMM_STATR0hStatus bit indicating that the die junction temperature is above the thermal level causing an immediate shutdown. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in . Return to the Summary Table. STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h] STAT_READBACK_ERR is shown in and described in .Return to the Summary Table.Summary Table STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h STAT_READBACK_ERR Register 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED NRSTOUT_SOC_READBACK_STAT NRSTOUT_READBACK_STAT NINT_READBACK_STAT EN_DRV_READBACK_STAT RESERVEDNRSTOUT_SOC_READBACK_STATNRSTOUT_READBACK_STATNINT_READBACK_STAT EN_DRV_READBACK_STAT EN_DRV_READBACK_STAT R-0h R-0h R-0h R-0h R-0h R-0hR-0hR-0hR-0h R-0h R-0h STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. STAT_READBACK_ERR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R 0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. 7-4 RESERVED R 0h 7-4RESERVEDR0h 3 NRSTOUT_SOC_READBACK_STAT R 0h Status bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 3NRSTOUT_SOC_READBACK_STATR0hStatus bit indicating that NRSTOUT_SOC pin output is high and device is driving it low. 2 NRSTOUT_READBACK_STAT R 0h Status bit indicating that NRSTOUT pin output is high and device is driving it low. 2NRSTOUT_READBACK_STATR0hStatus bit indicating that NRSTOUT pin output is high and device is driving it low. 1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving it low. 1NINT_READBACK_STATR0hStatus bit indicating that NINT pin output is high and device is driving it low. 0 EN_DRV_READBACK_STAT R 0h Status bit indicating that EN_DRV pin output is different than driven. 0EN_DRV_READBACK_STATR0hStatus bit indicating that EN_DRV pin output is different than driven. PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in . Return to the Summary Table. PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h] PGOOD_SEL_1 is shown in and described in .Return to the Summary Table.Summary Table PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_1 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1 PGOOD_SEL_BUCK4PGOOD_SEL_BUCK3PGOOD_SEL_BUCK2PGOOD_SEL_BUCK1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 7-6PGOOD_SEL_BUCK4R/W0hPGOOD signal source control from BUCK4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4PGOOD_SEL_BUCK3R/W0hPGOOD signal source control from BUCK3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2PGOOD_SEL_BUCK2R/W0hPGOOD signal source control from BUCK2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0PGOOD_SEL_BUCK1R/W0hPGOOD signal source control from BUCK1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in . Return to the Summary Table. PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h] PGOOD_SEL_2 is shown in and described in .Return to the Summary Table.Summary Table PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h PGOOD_SEL_2 Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED PGOOD_SEL_BUCK5 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED PGOOD_SEL_BUCK5 RESERVEDPGOOD_SEL_BUCK5 R/W-0h R/W-0h R/W-0hR/W-0h PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_2 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0PGOOD_SEL_BUCK5R/W0hPGOOD signal source control from BUCK5 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in . Return to the Summary Table. PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h] PGOOD_SEL_3 is shown in and described in .Return to the Summary Table.Summary Table PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_3 Register 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1 PGOOD_SEL_LDO4PGOOD_SEL_LDO3PGOOD_SEL_LDO2PGOOD_SEL_LDO1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 7-6PGOOD_SEL_LDO4R/W0hPGOOD signal source control from LDO4 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 5-4PGOOD_SEL_LDO3R/W0hPGOOD signal source control from LDO3 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 3-2PGOOD_SEL_LDO2R/W0hPGOOD signal source control from LDO2 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 1-0PGOOD_SEL_LDO1R/W0hPGOOD signal source control from LDO1 (Default from NVM memory) 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit 0h = Masked 1h = Powergood threshold voltage 2h = Powergood threshold voltage AND current limit 3h = Powergood threshold voltage AND current limit PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in . Return to the Summary Table. PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h] PGOOD_SEL_4 is shown in and described in .Return to the Summary Table.Summary Table PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h PGOOD_SEL_4 Register 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 PGOOD_WINDOW PGOOD_POL PGOOD_SEL_NRSTOUT_SOC PGOOD_SEL_NRSTOUT PGOOD_SEL_TDIE_WARN RESERVED PGOOD_SEL_VCCA PGOOD_WINDOWPGOOD_POLPGOOD_SEL_NRSTOUT_SOCPGOOD_SEL_NRSTOUTPGOOD_SEL_TDIE_WARNRESERVEDPGOOD_SEL_VCCA R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PGOOD_SEL_4 Register Field Descriptions Bit Field Type Reset Description 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal 7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 7PGOOD_WINDOWR/W0hType of voltage monitoring for PGOOD signal: (Default from NVM memory) 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 0h = Only undervoltage is monitored 1h = Both undervoltage and overvoltage are monitored 6 PGOOD_POL R/W 0h PGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 6PGOOD_POLR/W0hPGOOD signal polarity select: (Default from NVM memory) 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 0h = PGOOD signal is high when monitored inputs are valid 1h = PGOOD signal is low when monitored inputs are valid 5 PGOOD_SEL_NRSTOUT_SOC R/W 0h PGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 5PGOOD_SEL_NRSTOUT_SOCR/W0hPGOOD signal source control from nRSTOUT_SOC pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 0h = Masked 1h = nRSTOUT_SOC pin low state forces PGOOD signal to low 4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 4PGOOD_SEL_NRSTOUTR/W0hPGOOD signal source control from nRSTOUT pin: (Default from NVM memory) 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 0h = Masked 1h = nRSTOUT pin low state forces PGOOD signal to low 3 PGOOD_SEL_TDIE_WARN R/W 0h PGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 3PGOOD_SEL_TDIE_WARNR/W0hPGOOD signal source control from thermal warning (Default from NVM memory) 0h = Masked 1h = Thermal warning affecting to PGOOD signal 0h = Masked 1h = Thermal warning affecting to PGOOD signal 2-1 RESERVED R/W 0h 2-1RESERVEDR/W0h 0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal 0PGOOD_SEL_VCCAR/W0hPGOOD signal source control from VCCA monitoring (Default from NVM memory) 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal 0h = Masked 1h = VCCA OV/UV threshold affecting PGOOD signal PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in . Return to the Summary Table. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved PLL_CTRL Register (Offset = 7Ch) [Reset = 00h] PLL_CTRL is shown in and described in .Return to the Summary Table.Summary Table PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED EXT_CLK_FREQ R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED EXT_CLK_FREQ RESERVEDEXT_CLK_FREQ R/W-0h R/W-0h R/W-0hR/W-0h PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved 1-0EXT_CLK_FREQR/W0hFrequency of the external clock (SYNCCLKIN): See electrical specification for input clock frequency tolerance. (Default from NVM memory) 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved 0h = 1.1 MHz 1h = 2.2 MHz 2h = 4.4 MHz 3h = Reserved CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in . Return to the Summary Table. CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_1 Register (Offset = 7Dh) [Reset = C0h] CONFIG_1 is shown in and described in .Return to the Summary Table.Summary Table CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_1 Register 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 NSLEEP2_MASK NSLEEP1_MASK EN_ILIM_FSM_CTRL I2C2_HS I2C1_HS RESERVED TSD_ORD_LEVEL TWARN_LEVEL NSLEEP2_MASKNSLEEP1_MASKEN_ILIM_FSM_CTRL I2C2_HS I2C2_HSI2C1_HSRESERVEDTSD_ORD_LEVELTWARN_LEVEL R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1hR/W-1hR/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C CONFIG_1 Register Field Descriptions Bit Field Type Reset Description 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C 7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 7NSLEEP2_MASKR/W1hMasking for NSLEEP2 pin(s) and NSLEEP2B bit: (Default from NVM memory) 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 0h = NSLEEP2(B) affects FSM state transitions. 1h = NSLEEP2(B) does not affect FSM state transitions. 6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 6NSLEEP1_MASKR/W1hMasking for NSLEEP1 pin(s) and NSLEEP1B bit: (Default from NVM memory) 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 0h = NSLEEP1(B) affects FSM state transitions. 1h = NSLEEP1(B) does not affect FSM state transitions. 5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 5EN_ILIM_FSM_CTRLR/W0h(Default from NVM memory) 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers. 1h = Buck/LDO regulators ILIM interrupts affect FSM triggers. 4 I2C2_HS R/W 0h Select I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 4I2C2_HSR/W0hSelect I2C2 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3 I2C1_HS R/W 0h Select I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 3I2C1_HSR/W0hSelect I2C1 speed (input filter) (Default from NVM memory) 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 0h = Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code. 1h = Forced to Hs-mode 2 RESERVED R/W 0h 2RESERVEDR/W0h 1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 1TSD_ORD_LEVELR/W0hThermal shutdown threshold level. (Default from NVM memory) 0h = 140C 1h = 145C 0h = 140C 1h = 145C 0 TWARN_LEVEL R/W 0h Thermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C 0TWARN_LEVELR/W0hThermal warning threshold level. (Default from NVM memory) 0h = 130C 1h = 140C 0h = 130C 1h = 140C CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in . Return to the Summary Table. CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled CONFIG_2 Register (Offset = 7Eh) [Reset = 00h] CONFIG_2 is shown in and described in .Return to the Summary Table.Summary Table CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h CONFIG_2 Register 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER_EN BB_EOC_RDYRESERVEDBB_VEOCBB_ICHRBB_CHARGER_EN R-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0hR/W-0hR/W-0hR/W-0hR/W-0h CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled 7 BB_EOC_RDY R 0h Backup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 7BB_EOC_RDYR0hBackup end of charge indication 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 0h = Charging active or not enabled 1h = Charger has reached termination voltage set by BB_VEOC register 6-4 RESERVED R/W 0h 6-4RESERVEDR/W0h 3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 3-2BB_VEOCR/W0hEnd of charge voltage for backup battery charger: (Default from NVM memory) 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 0h = 2.5V 1h = 2.8V 2h = 3.0V 3h = 3.3V 1 BB_ICHR R/W 0h Backup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 1BB_ICHRR/W0hBackup battery charging current: (Default from NVM memory) 0h = 100uA 1h = 500uA 0h = 100uA 1h = 500uA 0 BB_CHARGER_EN R/W 0h Backup battery charging: 0h = Disabled 1h = Enabled 0BB_CHARGER_ENR/W0hBackup battery charging: 0h = Disabled 1h = Enabled 0h = Disabled 1h = Enabled ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in . Return to the Summary Table. ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h] ENABLE_DRV_REG is shown in and described in .Return to the Summary Table.Summary Table ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h ENABLE_DRV_REG Register 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ENABLE_DRV R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ENABLE_DRV RESERVEDENABLE_DRV R/W-0h R/W-0h R/W-0hR/W-0h ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High ENABLE_DRV_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 ENABLE_DRV R/W 0h Control for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High 0ENABLE_DRVR/W0hControl for EN_DRV pin: FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin. Otherwise EN_DRV pin is low. 0h = Low 1h = High 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in . Return to the Summary Table. MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High MISC_CTRL Register (Offset = 81h) [Reset = 00h] MISC_CTRL is shown in and described in .Return to the Summary Table.Summary Table MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h MISC_CTRL Register 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SOC NRSTOUT SYNCCLKOUT_FREQ_SELSEL_EXT_CLKAMUXOUT_ENCLKMON_ENLPM_ENNRSTOUT_SOCNRSTOUT R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High MISC_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High 7-6 SYNCCLKOUT_FREQ_SEL R/W 0h SYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 7-6SYNCCLKOUT_FREQ_SELR/W0hSYNCCLKOUT enable/frequency select: 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 0h = SYNCCLKOUT off 1h = 1.1 MHz 2h = 2.2 MHz 3h = 4.4 MHz 5 SEL_EXT_CLK R/W 0h Selection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 5SEL_EXT_CLKR/W0hSelection of external clock: 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 0h = Forced to internal RC oscillator. 1h = Automatic external clock used when available, interrupt is generated if the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range. 4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 4AMUXOUT_ENR/W0hControl bandgap voltage to AMUXOUT pin. 0h = Disabled 1h = Enabled 0h = Disabled 1h = Enabled 3 CLKMON_EN R/W 0h Control of internal clock monitoring. 0h = Disabled 1h = Enabled 3CLKMON_ENR/W0hControl of internal clock monitoring. 0h = Disabled 1h = Enabled 0h = Disabled 1h = Enabled 2 LPM_EN R/W 0h Low power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 2LPM_ENR/W0hLow power mode control. LPM_EN sets device in a low power mode. Intended use case is for the PFSM to set LPM_EN upon entering a deep sleep state. The end objective is to disable the digital oscillator to reduce power consumption. The following functions are disabled when LPM_EN=1. -TSD cycling of all sensors/thresholds -regmap/SRAM CRC continuous checking -SPMI WD NVM_ID request/response polling -Disable clock monitoring 0h = Low power mode disabled 1h = Low power mode enabled 0h = Low power mode disabled 1h = Low power mode enabled 1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal: 0h = Low 1h = High 1NRSTOUT_SOCR/W0hControl for nRSTOUT_SOC signal: 0h = Low 1h = High 0h = Low 1h = High 0 NRSTOUT R/W 0h Control for nRSTOUT signal: 0h = Low 1h = High 0NRSTOUTR/W0hControl for nRSTOUT signal: 0h = Low 1h = High 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in . Return to the Summary Table. ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h] ENABLE_DRV_STAT is shown in and described in .Return to the Summary Table.Summary Table ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h ENABLE_DRV_STAT Register 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SPMI_LPM_EN FORCE_EN_DRV_LOW NRSTOUT_SOC_IN NRSTOUT_IN EN_DRV_IN RESERVEDSPMI_LPM_EN FORCE_EN_DRV_LOW FORCE_EN_DRV_LOWNRSTOUT_SOC_INNRSTOUT_IN EN_DRV_IN EN_DRV_IN R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h R/W-0hR/W-0h R/W-1h R/W-1hR-0hR-0h R-0h R-0h ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High ENABLE_DRV_STAT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 4SPMI_LPM_ENR/W0hThis bit is read/write for PFSM and read-only for I2C/SPI SPMI low power mode control. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar times to prevent SPMI WD failures. Therefore to mitigate clock variations, setting SPMI_LPM_EN=1 must be done early in the sequence. The following functions are disabled when SPMI_LPM_EN=1. -SPMI WD NVM_ID request/response polling 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 0h = SPMI low power mode disabled 1h = SPMI low power mode enabled 3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 3FORCE_EN_DRV_LOWR/W1hThis bit is read/write for PFSM and read-only for I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 0h = ENABLE_DRV bit can be written by I2C/SPI 1h = ENABLE_DRV bit is forced low and cannot be written high by I2C/SPI 2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin: 0h = Low 1h = High 2NRSTOUT_SOC_INR0hLevel of NRSTOUT_SOC pin: 0h = Low 1h = High 0h = Low 1h = High 1 NRSTOUT_IN R 0h Level of NRSTOUT pin: 0h = Low 1h = High 1NRSTOUT_INR0hLevel of NRSTOUT pin: 0h = Low 1h = High 0h = Low 1h = High 0 EN_DRV_IN R 0h Level of EN_DRV pin: 0h = Low 1h = High 0EN_DRV_INR0hLevel of EN_DRV pin: 0h = Low 1h = High 0h = Low 1h = High RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h] RECOV_CNT_REG_1 is shown in and described in .Return to the Summary Table.Summary Table RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h RECOV_CNT_REG_1 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED RECOV_CNT RESERVEDRECOV_CNT R-0h R-0h R-0hR-0h RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R 0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. 7-4 RESERVED R 0h 7-4RESERVEDR0h 3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time PMIC goes through warm reset. 3-0RECOV_CNTR0hRecovery counter status. Counter value is incremented each time PMIC goes through warm reset. RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in . Return to the Summary Table. RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h] RECOV_CNT_REG_2 is shown in and described in .Return to the Summary Table.Summary Table RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h RECOV_CNT_REG_2 Register 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED RECOV_CNT_CLR RECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED RECOV_CNT_CLR RECOV_CNT_THR RESERVEDRECOV_CNT_CLRRECOV_CNT_THR R/W-0h R/WSelfClrF-0h R/W-0h R/W-0hR/WSelfClrF-0hR/W-0h RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) RECOV_CNT_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 4RECOV_CNT_CLRR/WSelfClrF0hRecovery counter clear. Write 1 to clear the counter. This bit is automatically set back to 0. 3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) 3-0RECOV_CNT_THRR/W0hRecovery counter threshold value for immediate power-down of all supply rails. (Default from NVM memory) FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h] FSM_I2C_TRIGGERS is shown in and described in .Return to the Summary Table.Summary Table FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h FSM_I2C_TRIGGERS Register 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h 7 6 5 4 3 2 1 0 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h 7 6 5 4 3 2 1 0 76543210 TRIGGER_I2C_7 TRIGGER_I2C_6 TRIGGER_I2C_5 TRIGGER_I2C_4 TRIGGER_I2C_3 TRIGGER_I2C_2 TRIGGER_I2C_1 TRIGGER_I2C_0 TRIGGER_I2C_7TRIGGER_I2C_6TRIGGER_I2C_5TRIGGER_I2C_4TRIGGER_I2C_3TRIGGER_I2C_2TRIGGER_I2C_1TRIGGER_I2C_0 R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/W-0hR/W-0hR/W-0hR/W-0hR/WSelfClrF-0hR/WSelfClrF-0hR/WSelfClrF-0hR/WSelfClrF-0h FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_I2C_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program. 7TRIGGER_I2C_7R/W0hTrigger for PFSM program. 6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program. 6TRIGGER_I2C_6R/W0hTrigger for PFSM program. 5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program. 5TRIGGER_I2C_5R/W0hTrigger for PFSM program. 4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program. 4TRIGGER_I2C_4R/W0hTrigger for PFSM program. 3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 3TRIGGER_I2C_3R/WSelfClrF0hTrigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 2TRIGGER_I2C_2R/WSelfClrF0hTrigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 1TRIGGER_I2C_1R/WSelfClrF0hTrigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. 0TRIGGER_I2C_0R/WSelfClrF0hTrigger for PFSM program. This bit is automatically cleared. Writing this bit 1 creates PFSM trigger pulse. FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in . Return to the Summary Table. FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h] FSM_NSLEEP_TRIGGERS is shown in and described in .Return to the Summary Table.Summary Table FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h FSM_NSLEEP_TRIGGERS Register 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED NSLEEP2B NSLEEP1B R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED NSLEEP2B NSLEEP1B RESERVEDNSLEEP2BNSLEEP1B R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high FSM_NSLEEP_TRIGGERS Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-2 RESERVED R/W 0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high 7-2 RESERVED R/W 0h 7-2RESERVEDR/W0h 1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 1NSLEEP2BR/W0hParallel register bit for NSLEEP2 function: 0h = NSLEEP2 low 1h = NSLEEP2 high 0h = NSLEEP2 low 1h = NSLEEP2 high 0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high 0NSLEEP1BR/W0hParallel register bit for NSLEEP1 function: 0h = NSLEEP1 low 1h = NSLEEP1 high 0h = NSLEEP1 low 1h = NSLEEP1 high BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in . Return to the Summary Table. BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h] BUCK_RESET_REG is shown in and described in .Return to the Summary Table.Summary Table BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h BUCK_RESET_REG Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET RESERVEDBUCK5_RESETBUCK4_RESETBUCK3_RESETBUCK2_RESETBUCK1_RESET R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. BUCK_RESET_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 BUCK5_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 4BUCK5_RESETR/W0hReset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3 BUCK4_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 3BUCK4_RESETR/W0hReset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2 BUCK3_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 2BUCK3_RESETR/W0hReset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1 BUCK2_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 1BUCK2_RESETR/W0hReset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0 BUCK1_RESET R/W 0h Reset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. 0BUCK1_RESETR/W0hReset signal for Buck logic. Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1' DURING DEVICE OPERATION. SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in . Return to the Summary Table. SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h] SPREAD_SPECTRUM_1 is shown in and described in .Return to the Summary Table.Summary Table SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h SPREAD_SPECTRUM_1 Register 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED SS_EN SS_DEPTH R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SS_EN SS_DEPTH RESERVEDSS_ENSS_DEPTH R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED SPREAD_SPECTRUM_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R/W 0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED 7-3 RESERVED R/W 0h 7-3RESERVEDR/W0h 2 SS_EN R/W 0h Spread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 2SS_ENR/W0hSpread spectrum enable. (Default from NVM memory) 0h = Spread spectrum disabled 1h = Spread spectrum enabled 0h = Spread spectrum disabled 1h = Spread spectrum enabled 1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED 1-0SS_DEPTHR/W0hSpread spectrum modulation depth. (Default from NVM memory) 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED 0h = No modulation 1h = +/- 6.3% 2h = +/- 8.4% 3h = RESERVED FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in . Return to the Summary Table. FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FREQ_SEL Register (Offset = 8Ah) [Reset = 00h] FREQ_SEL is shown in and described in .Return to the Summary Table.Summary Table FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h FREQ_SEL Register 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED BUCK5_FREQ_SEL BUCK4_FREQ_SEL BUCK3_FREQ_SEL BUCK2_FREQ_SEL BUCK1_FREQ_SEL RESERVEDBUCK5_FREQ_SELBUCK4_FREQ_SELBUCK3_FREQ_SELBUCK2_FREQ_SELBUCK1_FREQ_SEL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz FREQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 4BUCK5_FREQ_SELR/W0hBuck5 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0h = 2.2 MHz 1h = 4.4 MHz 3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 3BUCK4_FREQ_SELR/W0hBuck4 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0h = 2.2 MHz 1h = 4.4 MHz 2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 2BUCK3_FREQ_SELR/W0hBuck3 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0h = 2.2 MHz 1h = 4.4 MHz 1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 1BUCK2_FREQ_SELR/W0hBuck2 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0h = 2.2 MHz 1h = 4.4 MHz 0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0BUCK1_FREQ_SELR/W0hBuck1 switching frequency: This bit is Read/Write or Read-Only for I2C/SPI access depending on NVM configuration. See Technical Reference Manual / User's Guide for details. (Default from NVM memory) 0h = 2.2 MHz 1h = 4.4 MHz 0h = 2.2 MHz 1h = 4.4 MHz FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in . Return to the Summary Table. FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h] FSM_STEP_SIZE is shown in and described in .Return to the Summary Table.Summary Table FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h FSM_STEP_SIZE Register 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED PFSM_DELAY_STEP R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED PFSM_DELAY_STEP RESERVEDPFSM_DELAY_STEP R/W-0h R/W-0h R/W-0hR/W-0h FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) FSM_STEP_SIZE Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory) 4-0PFSM_DELAY_STEPR/W0hStep size for PFSM sequence counter. Step size is 50ns * 2PFSM_DELAY_STEP. (Default from NVM memory)PFSM_DELAY_STEP USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in . Return to the Summary Table. USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h] USER_SPARE_REGS is shown in and described in .Return to the Summary Table.Summary Table USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h USER_SPARE_REGS Register 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED USER_SPARE_4 USER_SPARE_3 USER_SPARE_2 USER_SPARE_1 RESERVEDUSER_SPARE_4USER_SPARE_3USER_SPARE_2USER_SPARE_1 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) USER_SPARE_REGS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 USER_SPARE_4 R/W 0h (Default from NVM memory) 3USER_SPARE_4R/W0h(Default from NVM memory) 2 USER_SPARE_3 R/W 0h (Default from NVM memory) 2USER_SPARE_3R/W0h(Default from NVM memory) 1 USER_SPARE_2 R/W 0h (Default from NVM memory) 1USER_SPARE_2R/W0h(Default from NVM memory) 0 USER_SPARE_1 R/W 0h (Default from NVM memory) 0USER_SPARE_1R/W0h(Default from NVM memory) ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in . Return to the Summary Table. ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h] ESM_MCU_START_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h ESM_MCU_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_START R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_MCU_START RESERVEDESM_MCU_START R/W-0h R/W-0h R/W-0hR/W-0h ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. 0ESM_MCU_STARTR/W0hControl bit to start the ESM_MCU: 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. 0h = ESM_MCU not started. Device clears ENABLE_DRV bit when bit ESM_MCU_EN=1 1h = ESM_MCU started. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h] ESM_MCU_DELAY1_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h ESM_MCU_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_DELAY1 ESM_MCU_DELAY1 R/W-0h R/W-0h ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_DELAY1R/W0hThese bits configure the duration of the ESM_MCU delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h] ESM_MCU_DELAY2_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h ESM_MCU_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_DELAY2 ESM_MCU_DELAY2 R/W-0h R/W-0h ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_DELAY2R/W0hThese bits configure the duration of the ESM_MCU delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h] ESM_MCU_MODE_CFG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_MCU_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_MODE ESM_MCU_EN ESM_MCU_ENDRV RESERVED ESM_MCU_ERR_CNT_TH ESM_MCU_MODEESM_MCU_ENESM_MCU_ENDRVRESERVEDESM_MCU_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. 7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 7ESM_MCU_MODER/W0hThis bit selects the mode for the ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = Level Mode 1h = PWM Mode 0h = Level Mode 1h = PWM Mode 6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 6ESM_MCU_ENR/W0hESM_MCU enable configuration bit: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_MCU_START=1, and - (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and - ESM_MCU_RST_INT=0, and - all other interrupt bits are cleared 5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 5ESM_MCU_ENDRVR/W0hConfiguration bit to select ENABLE_DRV clear on ESM-error for ESM_MCU: These bits can be only be written when control bit ESM_MCU_START=0. 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1 4 RESERVED R/W 0h 4RESERVEDR/W0h 3-0 ESM_MCU_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. 3-0ESM_MCU_ERR_CNT_THR/W0hConfiguration bits for the threshold of the ESM_MCU error-counter. The ESM_MCU starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] > ESM_MCU_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h] ESM_MCU_HMAX_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h ESM_MCU_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_HMAX R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_HMAX ESM_MCU_HMAX R/W-0h R/W-0h ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_HMAXR/W0hThese bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h] ESM_MCU_HMIN_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h ESM_MCU_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_HMIN R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_HMIN ESM_MCU_HMIN R/W-0h R/W-0h ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_HMINR/W0hThese bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h] ESM_MCU_LMAX_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h ESM_MCU_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_LMAX R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_LMAX ESM_MCU_LMAX R/W-0h R/W-0h ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_LMAXR/W0hThese bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h] ESM_MCU_LMIN_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h ESM_MCU_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h 7 6 5 4 3 2 1 0 ESM_MCU_LMIN R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_MCU_LMIN ESM_MCU_LMIN R/W-0h R/W-0h ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. 7-0ESM_MCU_LMINR/W0hThese bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_MCU_START=0. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h] ESM_MCU_ERR_CNT_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h ESM_MCU_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED ESM_MCU_ERR_CNT R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_MCU_ERR_CNT RESERVEDESM_MCU_ERR_CNT R-0h R-0h R-0hR-0h ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_MCU_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R 0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. 7-5 RESERVED R 0h 7-5RESERVEDR0h 4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. 4-0ESM_MCU_ERR_CNTR0hStatus bits to indicate the value of the ESM_MCU Error-Counter. The device clears these bits when ESM_MCU_START bit is 0, or when the device resets the MCU. ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in . Return to the Summary Table. ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h] ESM_SOC_START_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h ESM_SOC_START_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_START R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_SOC_START RESERVEDESM_SOC_START R/W-0h R/W-0h R/W-0hR/W-0h ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_START_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started 0ESM_SOC_STARTR/W0hControl bit to start the ESM_SoC: 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started 0h = ESM_SoC not started. Device clears ENABLE_DRV bit when bit ESM_SOC_EN=1 1h = ESM_SoC started ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h] ESM_SOC_DELAY1_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h ESM_SOC_DELAY1_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_DELAY1 ESM_SOC_DELAY1 R/W-0h R/W-0h ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY1_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_DELAY1R/W0hThese bits configure the duration of the ESM_SoC delay-1 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in . Return to the Summary Table. ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h] ESM_SOC_DELAY2_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h ESM_SOC_DELAY2_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_DELAY2 ESM_SOC_DELAY2 R/W-0h R/W-0h ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_DELAY2_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_DELAY2R/W0hThese bits configure the duration of the ESM_SoC delay-2 time-interval (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in . Return to the Summary Table. ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h] ESM_SOC_MODE_CFG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h ESM_SOC_MODE_CFG Register 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_MODE ESM_SOC_EN ESM_SOC_ENDRV RESERVED ESM_SOC_ERR_CNT_TH ESM_SOC_MODEESM_SOC_ENESM_SOC_ENDRVRESERVEDESM_SOC_ERR_CNT_TH R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_MODE_CFG Register Field Descriptions Bit Field Type Reset Description 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. 7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 7ESM_SOC_MODER/W0hThis bit selects the mode for the ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0. 0h = Level Mode 1h = PWM Mode 0h = Level Mode 1h = PWM Mode 6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 6ESM_SOC_ENR/W0hESM_SoC enable configuration bit: These bits can be only be written when control bit ESM_SOC_START=0. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt bits are cleared 1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if: - bit ESM_SOC_START=1, and - (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and - ESM_SOC_RST_INT=0, and - all other interrupt bits are cleared. 5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 5ESM_SOC_ENDRVR/W0hConfiguration bit to select ENABLE_DRV clear on ESM-error for ESM_SoC: These bits can be only be written when control bit ESM_SOC_START=0 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1 1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1. 4 RESERVED R/W 0h 4RESERVEDR/W0h 3-0 ESM_SOC_ERR_CNT_TH R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. 3-0ESM_SOC_ERR_CNT_THR/W0hConfiguration bits for the threshold of the ESM_SoC error-counter The ESM_SoC starts the Error Handling Procedure (see Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] > ESM_SOC_ERR_CNT_TH[3:0]. These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h] ESM_SOC_HMAX_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h ESM_SOC_HMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_HMAX R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_HMAX ESM_SOC_HMAX R/W-0h R/W-0h ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_HMAXR/W0hThese bits configure the the maximum high-pulse time-threshold (tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h] ESM_SOC_HMIN_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h ESM_SOC_HMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_HMIN R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_HMIN ESM_SOC_HMIN R/W-0h R/W-0h ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_HMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_HMINR/W0hThese bits configure the the minimum high-pulse time-threshold (tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h] ESM_SOC_LMAX_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h ESM_SOC_LMAX_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_LMAX R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_LMAX ESM_SOC_LMAX R/W-0h R/W-0h ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMAX_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_LMAXR/W0hThese bits configure the the maximum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in . Return to the Summary Table. ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h] ESM_SOC_LMIN_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h ESM_SOC_LMIN_REG Register 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h 7 6 5 4 3 2 1 0 ESM_SOC_LMIN R/W-0h 7 6 5 4 3 2 1 0 76543210 ESM_SOC_LMIN ESM_SOC_LMIN R/W-0h R/W-0h ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_LMIN_REG Register Field Descriptions Bit Field Type Reset Description 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. 7-0ESM_SOC_LMINR/W0hThese bits configure the the minimum low-pulse time-threshold (tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter). These bits can be only be written when control bit ESM_SOC_START=0. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in . Return to the Summary Table. ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h] ESM_SOC_ERR_CNT_REG is shown in and described in .Return to the Summary Table.Summary Table ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h ESM_SOC_ERR_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED ESM_SOC_ERR_CNT R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ESM_SOC_ERR_CNT RESERVEDESM_SOC_ERR_CNT R-0h R-0h R-0hR-0h ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. ESM_SOC_ERR_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R 0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. 7-5 RESERVED R 0h 7-5RESERVEDR0h 4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. 4-0ESM_SOC_ERR_CNTR0hStatus bits to indicate the value of the ESM_SoC Error-Counter. The device clears these bits when ESM_SOC_START bit is 0, or when the device resets the SoC. REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in . Return to the Summary Table. REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked REGISTER_LOCK Register (Offset = A1h) [Reset = 00h] REGISTER_LOCK is shown in and described in .Return to the Summary Table.Summary Table REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h REGISTER_LOCK Register 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED REGISTER_LOCK_STATUS R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED REGISTER_LOCK_STATUS RESERVEDREGISTER_LOCK_STATUS R/W-0h R/W-0h R/W-0hR/W-0h REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked REGISTER_LOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 REGISTER_LOCK_STATUS R/W 0h Unlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked 0REGISTER_LOCK_STATUSR/W0hUnlocking registers: write 0x9B to this address. Locking registers: write anything else than 0x9B to this address. Written 8 bit data to this address is not stored, only lock status can be read. REGISTER_LOCK_STATUS bit shows the lock status: 0h = Registers are unlocked 1h = Registers are locked 0h = Registers are unlocked 1h = Registers are locked MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in . Return to the Summary Table. MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h] MANUFACTURING_VER is shown in and described in .Return to the Summary Table.Summary Table MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h MANUFACTURING_VER Register 7 6 5 4 3 2 1 0 SILICON_REV R-0h 7 6 5 4 3 2 1 0 SILICON_REV R-0h 7 6 5 4 3 2 1 0 76543210 SILICON_REV SILICON_REV R-0h R-0h MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal MANUFACTURING_VER Register Field Descriptions Bit Field Type Reset Description 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal 7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal 7-0SILICON_REVR0hSILICON_REV[7:6] - Reserved SILICON_REV[5:3] - ALR SILICON_REV[2:0] - Metal CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in . Return to the Summary Table. CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h] CUSTOMER_NVM_ID_REG is shown in and described in .Return to the Summary Table.Summary Table CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h CUSTOMER_NVM_ID_REG Register 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h 7 6 5 4 3 2 1 0 CUSTOMER_NVM_ID R/W-0h 7 6 5 4 3 2 1 0 76543210 CUSTOMER_NVM_ID CUSTOMER_NVM_ID R/W-0h R/W-0h CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part CUSTOMER_NVM_ID_REG Register Field Descriptions Bit Field Type Reset Description 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part 7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part 7-0CUSTOMER_NVM_IDR/W0hCustomer defined value if customer programmed part Same value as in TI_NVM_ID register if TI programmed part SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in . Return to the Summary Table. SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h] SOFT_REBOOT_REG is shown in and described in .Return to the Summary Table.Summary Table SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h SOFT_REBOOT_REG Register 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h 7 6 5 4 3 2 1 0 RESERVED SOFT_REBOOT R/W-0h R/WSelfClrF-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SOFT_REBOOT RESERVEDSOFT_REBOOT R/W-0h R/WSelfClrF-0h R/W-0hR/WSelfClrF-0h SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. SOFT_REBOOT_REG Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot. This bit is automatically cleared. 0SOFT_REBOOTR/WSelfClrF0hWrite 1 to request a soft reboot. This bit is automatically cleared. RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in . Return to the Summary Table. RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_SECONDS Register (Offset = B5h) [Reset = 00h] RTC_SECONDS is shown in and described in .Return to the Summary Table.Summary Table RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h RTC_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED SECOND_1 SECOND_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED SECOND_1 SECOND_0 RESERVEDSECOND_1SECOND_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) RTC_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5) 6-4SECOND_1R/W0hSecond digit of seconds (range is 0 up to 5) 3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9) 3-0SECOND_0R/W0hFirst digit of seconds (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in . Return to the Summary Table. RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_MINUTES Register (Offset = B6h) [Reset = 00h] RTC_MINUTES is shown in and described in .Return to the Summary Table.Summary Table RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h RTC_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED MINUTE_1 MINUTE_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED MINUTE_1 MINUTE_0 RESERVEDMINUTE_1MINUTE_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) RTC_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5) 6-4MINUTE_1R/W0hSecond digit of minutes (range is 0 up to 5) 3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9) 3-0MINUTE_0R/W0hFirst digit of minutes (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in . Return to the Summary Table. RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_HOURS Register (Offset = B7h) [Reset = 00h] RTC_HOURS is shown in and described in .Return to the Summary Table.Summary Table RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h RTC_HOURS Register 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 PM_NAM RESERVED HOUR_1 HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 PM_NAM RESERVED HOUR_1 HOUR_0 PM_NAMRESERVEDHOUR_1HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) RTC_HOURS Register Field Descriptions Bit Field Type Reset Description 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) 7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 7PM_NAMR/W0hOnly used in PM_AM mode (otherwise it is set to 0) 0h = AM 1h = PM 0h = AM 1h = PM 6 RESERVED R/W 0h 6RESERVEDR/W0h 5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2) 5-4HOUR_1R/W0hSecond digit of hours(range is 0 up to 2) 3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9) 3-0HOUR_0R/W0hFirst digit of hours (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in . Return to the Summary Table. RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_DAYS Register (Offset = B8h) [Reset = 00h] RTC_DAYS is shown in and described in .Return to the Summary Table.Summary Table RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h RTC_DAYS Register 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED DAY_1 DAY_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED DAY_1 DAY_0 RESERVEDDAY_1DAY_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) RTC_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3) 5-4DAY_1R/W0hSecond digit of days (range is 0 up to 3) 3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9) 3-0DAY_0R/W0hFirst digit of days (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in . 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RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_MONTHS Register (Offset = B9h) [Reset = 00h] RTC_MONTHS is shown in and described in .Return to the Summary Table.Summary Table RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h RTC_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED MONTH_1 MONTH_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED MONTH_1 MONTH_0 RESERVEDMONTH_1MONTH_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) RTC_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1) 4MONTH_1R/W0hSecond digit of months (range is 0 up to 1) 3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9) 3-0MONTH_0R/W0hFirst digit of months (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in . 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RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_YEARS Register (Offset = BAh) [Reset = 00h] RTC_YEARS is shown in and described in .Return to the Summary Table.Summary Table RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h RTC_YEARS Register 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 YEAR_1 YEAR_0 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 YEAR_1 YEAR_0 YEAR_1YEAR_0 R/W-0h R/W-0h R/W-0hR/W-0h RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) RTC_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) 7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9) 7-4YEAR_1R/W0hSecond digit of years (range is 0 up to 9) 3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9) 3-0YEAR_0R/W0hFirst digit of years (range is 0 up to 9) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in . 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RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) RTC_WEEKS Register (Offset = BBh) [Reset = 00h] RTC_WEEKS is shown in and described in .Return to the Summary Table.Summary Table RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h RTC_WEEKS Register 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED WEEK R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED WEEK RESERVEDWEEK R/W-0h R/W-0h R/W-0hR/W-0h RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) RTC_WEEKS Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R/W 0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) 7-3 RESERVED R/W 0h 7-3RESERVEDR/W0h 2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6) 2-0WEEKR/W0hFirst digit of day of the week (range is 0 up to 6) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in . 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ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_SECONDS Register (Offset = BCh) [Reset = 00h] ALARM_SECONDS is shown in and described in .Return to the Summary Table.Summary Table ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h ALARM_SECONDS Register 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ALR_SECOND_1 ALR_SECOND_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ALR_SECOND_1 ALR_SECOND_0 RESERVEDALR_SECOND_1ALR_SECOND_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) ALARM_SECONDS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5) 6-4ALR_SECOND_1R/W0hSecond digit of alarm programmation for seconds (range is 0 up to 5) 3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9) 3-0ALR_SECOND_0R/W0hFirst digit of alarm programmation for seconds (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in . 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ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_MINUTES Register (Offset = BDh) [Reset = 00h] ALARM_MINUTES is shown in and described in .Return to the Summary Table.Summary Table ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h ALARM_MINUTES Register 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ALR_MINUTE_1 ALR_MINUTE_0 RESERVEDALR_MINUTE_1ALR_MINUTE_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) ALARM_MINUTES Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5) 6-4ALR_MINUTE_1R/W0hSecond digit of alarm programmation for minutes (range is 0 up to 5) 3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9) 3-0ALR_MINUTE_0R/W0hFirst digit of alarm programmation for minutes (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in . 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ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_HOURS Register (Offset = BEh) [Reset = 00h] ALARM_HOURS is shown in and described in .Return to the Summary Table.Summary Table ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h ALARM_HOURS Register 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0 ALR_PM_NAMRESERVEDALR_HOUR_1ALR_HOUR_0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) ALARM_HOURS Register Field Descriptions Bit Field Type Reset Description 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 6 RESERVED R/W 0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) 7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 7ALR_PM_NAMR/W0hOnly used in PM_AM mode for alarm programmation (otherwise it is set to 0) 0h = AM 1h = PM 0h = AM 1h = PM 6 RESERVED R/W 0h 6RESERVEDR/W0h 5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2) 5-4ALR_HOUR_1R/W0hSecond digit of alarm programmation for hours(range is 0 up to 2) 3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9) 3-0ALR_HOUR_0R/W0hFirst digit of alarm programmation for hours (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in . 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ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_DAYS Register (Offset = BFh) [Reset = 00h] ALARM_DAYS is shown in and described in .Return to the Summary Table.Summary Table ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h ALARM_DAYS Register 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ALR_DAY_1 ALR_DAY_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ALR_DAY_1 ALR_DAY_0 RESERVEDALR_DAY_1ALR_DAY_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) ALARM_DAYS Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R/W 0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) 7-6 RESERVED R/W 0h 7-6RESERVEDR/W0h 5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3) 5-4ALR_DAY_1R/W0hSecond digit of alarm programmation for days (range is 0 up to 3) 3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9) 3-0ALR_DAY_0R/W0hFirst digit of alarm programmation for days (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in . 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ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_MONTHS Register (Offset = C0h) [Reset = 00h] ALARM_MONTHS is shown in and described in .Return to the Summary Table.Summary Table ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h ALARM_MONTHS Register 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED ALR_MONTH_1 ALR_MONTH_0 R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED ALR_MONTH_1 ALR_MONTH_0 RESERVEDALR_MONTH_1ALR_MONTH_0 R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0h ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) ALARM_MONTHS Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 RESERVED R/W 0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) 7-5 RESERVED R/W 0h 7-5RESERVEDR/W0h 4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1) 4ALR_MONTH_1R/W0hSecond digit of alarm programmation for months (range is 0 up to 1) 3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9) 3-0ALR_MONTH_0R/W0hFirst digit of alarm programmation for months (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in . Return to the Summary Table. ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) ALARM_YEARS Register (Offset = C1h) [Reset = 00h] ALARM_YEARS is shown in and described in .Return to the Summary Table.Summary Table ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h ALARM_YEARS Register 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 ALR_YEAR_1 ALR_YEAR_0 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 ALR_YEAR_1 ALR_YEAR_0 ALR_YEAR_1ALR_YEAR_0 R/W-0h R/W-0h R/W-0hR/W-0h ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) ALARM_YEARS Register Field Descriptions Bit Field Type Reset Description 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) 7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9) 7-4ALR_YEAR_1R/W0hSecond digit of alarm programmation for years (range is 0 up to 9) 3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9) 3-0ALR_YEAR_0R/W0hFirst digit of alarm programmation for years (range is 0 up to 9) RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in . Return to the Summary Table. RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h] RTC_CTRL_1 is shown in and described in .Return to the Summary Table.Summary Table RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_1 Register 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RTC_V_OPT GET_TIME SET_32_COUNTER RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC RTC_V_OPTGET_TIMESET_32_COUNTERRESERVEDMODE_12_24AUTO_COMPROUND_30SSTOP_RTC R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running RTC_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running 7 RTC_V_OPT R/W 0h RTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 7RTC_V_OPTR/W0hRTC date / time register selection: 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 0h = Read access directly to dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEAR, RTC_WEEKS) 1h = Read access to static shadowed registers: (see GET_TIME bit). 6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 6GET_TIMER/W0hWhen writing a 1 into this register, the content of the dynamic registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1) Note: Shadowed registers, linked to the GET_TIME feature, are a parallel set of calendar static registers, at the same I2C addresses as the dynamic registers. Note: The GET_TIME feature loads the RTC counter in the shadow registers and make the content of the shadow registers available and stable for reading. Note: The GET_TIME bit has to be set to 0 and again to 1 to get a new timing value. Note: If the time reading is done without GET_TIME, the read value comes directly from the RTC counter and software has to manage the counter change during the reading. Time reading remains always at the same address, with or without using the GET_TIME feature. 5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 5SET_32_COUNTERR/W0hNote: This bit must only be used when the RTC is frozen. 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 0h = No action 1h = Set the 32kHz counter with RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value 4 RESERVED R/W 0h 4RESERVEDR/W0h 3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 3MODE_12_24R/W0hNote: It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode. 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 0h = 24 hours mode 1h = 12 hours mode (PM-AM mode) 2 AUTO_COMP R/W 0h AUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 2AUTO_COMPR/W0hAUTO_COMP 0h = No auto compensation 1h = Auto compensation enabled 0h = No auto compensation 1h = Auto compensation enabled 1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 1ROUND_30SR/W0hNote: This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller reads one until the rounding to the closest minute is performed at the next second. 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0h = No update 1h = When a one is written, the time is rounded to the closest minute 0 STOP_RTC R/W 0h STOP_RTC 0h = RTC is frozen 1h = RTC is running 0STOP_RTCR/W0hSTOP_RTC 0h = RTC is frozen 1h = RTC is running 0h = RTC is frozen 1h = RTC is running RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in . Return to the Summary Table. RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h] RTC_CTRL_2 is shown in and described in .Return to the Summary Table.Summary Table RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h RTC_CTRL_2 Register 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 FIRST_STARTUP_DONE STARTUP_DEST FAST_BIST LP_STANDBY_SEL XTAL_SEL XTAL_EN FIRST_STARTUP_DONESTARTUP_DEST FAST_BIST FAST_BISTLP_STANDBY_SELXTAL_SELXTAL_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled 7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 7FIRST_STARTUP_DONER/W0hThis bit controls if pre-configured NVM defaults are loaded to RTC domain reg bits during NVM read 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 0h = pre-configured NVM defaults are loaded to RTC domain bits 1h = pre-configured NVM defaults are not loaded to RTC domain bits 6-5 STARTUP_DEST R/W 0h FSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 6-5STARTUP_DESTR/W0hFSM start-up destination select. (Default from NVM memory) 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL 1h = Reserved 2h = MCU_ONLY 3h = ACTIVE 4 FAST_BIST R/W 0h FAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 4FAST_BISTR/W0hFAST_BIST (Default from NVM memory) 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 0h = Logic and analog BIST is run at BOOT BIST. 1h = Only analog BIST is run at BOOT BIST. 3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 3LP_STANDBY_SELR/W0hControl to enter low power standby state: (Default from NVM memory) 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 0h = LDOINT is enabled in standby state. 1h = Low power standby state is used as standby state (LDOINT is disabled). 2-1 XTAL_SEL R/W 0h Crystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 2-1XTAL_SELR/W0hCrystal oscillator type select (Default from NVM memory) 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0h = 6 pF 1h = 9 pF 2h = 12.5 pF 3h = Reserved 0 XTAL_EN R/W 0h Crystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled 0XTAL_ENR/W0hCrystal oscillator enable. (Default from NVM memory) 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled 0h = Crystal oscillator is disabled 1h = Crystal oscillator is enabled RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in . Return to the Summary Table. RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_STATUS Register (Offset = C4h) [Reset = 80h] RTC_STATUS is shown in and described in .Return to the Summary Table.Summary Table RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h RTC_STATUS Register 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h 7 6 5 4 3 2 1 0 POWER_UP ALARM TIMER RESERVED RUN RESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 POWER_UP ALARM TIMER RESERVED RUN RESERVED POWER_UPALARMTIMERRESERVEDRUNRESERVED R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h R/W1C-1hR/W1C-0hR/W1C-0hR/W-0hR-0hR/W-0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h RTC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h 7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 7POWER_UPR/W1C1hIndicates that a reset occurred (bit cleared to 0 by writing 1) and that RTC data are not valid anymore. Note: POWER_UP is set by a reset, is cleared by writing one in this bit. Note: The POWER_UP (RTC_STATUS) and RESET_STATUS (RTC_RESET_STATUS) register bits indicate the same information. 6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by writing 1). 6ALARMR/W1C0hIndicates that an alarm interrupt has been generated (bit clear by writing 1). 5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by writing 1). 5TIMERR/W1C0hIndicates that an timer interrupt has been generated (bit clear by writing 1). 4-2 RESERVED R/W 0h 4-2RESERVEDR/W0h 1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 1RUNR0hNote: This bit shows the real state of the RTC, indeed because of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz clock, the action of this bit is delayed. 0h = RTC is frozen 1h = RTC is running 0h = RTC is frozen 1h = RTC is running 0 RESERVED R/W 0h 0RESERVEDR/W0h RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in . Return to the Summary Table. RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h] RTC_INTERRUPTS is shown in and described in .Return to the Summary Table.Summary Table RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h RTC_INTERRUPTS Register 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED IT_ALARM IT_TIMER EVERY R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED IT_ALARM IT_TIMER EVERY RESERVEDIT_ALARMIT_TIMEREVERY R/W-0h R/W-0h R/W-0h R/W-0h R/W-0hR/W-0hR/W-0hR/W-0h RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_INTERRUPTS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 RESERVED R/W 0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day 7-4 RESERVED R/W 0h 7-4RESERVEDR/W0h 3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 3IT_ALARMR/W0hEnable one interrupt when the alarm value is reached (TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES, ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS, ALARM_YEARS) by the TC registers NOTE: To prevent mis-firing of the ALARM interrupt, set the IT_ALARM = 0 prior to configuring the ALARM registers 0h = interrupt disabled 1h = interrupt enabled 0h = interrupt disabled 1h = interrupt enabled 2 IT_TIMER R/W 0h Enable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 2IT_TIMERR/W0hEnable periodic interrupt NOTE: To prevent mis-firing of the TIMER interrupt, set the IT_TIMER = 0 prior to configuring the periodic time value 0h = interrupt disabled 1h = interrupt enabled 0h = interrupt disabled 1h = interrupt enabled 1-0 EVERY R/W 0h Interrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day 1-0EVERYR/W0hInterrupt period 0h = every second 1h = every minute 2h = every hour 3h = every day 0h = every second 1h = every minute 2h = every hour 3h = every day RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in . Return to the Summary Table. RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h] RTC_COMP_LSB is shown in and described in .Return to the Summary Table.Summary Table RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h RTC_COMP_LSB Register 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h 7 6 5 4 3 2 1 0 COMP_LSB_RTC R/W-0h 7 6 5 4 3 2 1 0 76543210 COMP_LSB_RTC COMP_LSB_RTC R/W-0h R/W-0h RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_LSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] 7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] 7-0COMP_LSB_RTCR/W0hThis register contains the number of 32kHz periods to be added into the 32kHz counter every hour [LSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in . Return to the Summary Table. RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h] RTC_COMP_MSB is shown in and described in .Return to the Summary Table.Summary Table RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h RTC_COMP_MSB Register 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h 7 6 5 4 3 2 1 0 COMP_MSB_RTC R/W-0h 7 6 5 4 3 2 1 0 76543210 COMP_MSB_RTC COMP_MSB_RTC R/W-0h R/W-0h RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_COMP_MSB Register Field Descriptions Bit Field Type Reset Description 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] 7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] 7-0COMP_MSB_RTCR/W0hThis register contains the number of 32kHz periods to be added into the 32kHz counter every hour [MSB] RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in . Return to the Summary Table. RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h] RTC_RESET_STATUS is shown in and described in .Return to the Summary Table.Summary Table RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h RTC_RESET_STATUS Register 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED RESET_STATUS_RTC R/W-0h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED RESET_STATUS_RTC RESERVEDRESET_STATUS_RTC R/W-0h R/W-0h R/W-0hR/W-0h RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. RTC_RESET_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-1 RESERVED R/W 0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. 7-1 RESERVED R/W 0h 7-1RESERVEDR/W0h 0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. 0RESET_STATUS_RTCR/W0hThis bit can only be set to one and is cleared when a manual reset or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR level) occur. If this bit is reset it means that the RTC has lost its configuration. Note: The RESET_STATUS (RTC_RESET_STATUS) and POWER_UP (RTC_STATUS) register bits indicate the same information. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h] SCRATCH_PAD_REG_1 is shown in and described in .Return to the Summary Table.Summary Table SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h SCRATCH_PAD_REG_1 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h 7 6 5 4 3 2 1 0 SCRATCH_PAD_1 R/W-0h 7 6 5 4 3 2 1 0 76543210 SCRATCH_PAD_1 SCRATCH_PAD_1 R/W-0h R/W-0h SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0SCRATCH_PAD_1R/W0hScratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h] SCRATCH_PAD_REG_2 is shown in and described in .Return to the Summary Table.Summary Table SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h SCRATCH_PAD_REG_2 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h 7 6 5 4 3 2 1 0 SCRATCH_PAD_2 R/W-0h 7 6 5 4 3 2 1 0 76543210 SCRATCH_PAD_2 SCRATCH_PAD_2 R/W-0h R/W-0h SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0SCRATCH_PAD_2R/W0hScratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h] SCRATCH_PAD_REG_3 is shown in and described in .Return to the Summary Table.Summary Table SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h SCRATCH_PAD_REG_3 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h 7 6 5 4 3 2 1 0 SCRATCH_PAD_3 R/W-0h 7 6 5 4 3 2 1 0 76543210 SCRATCH_PAD_3 SCRATCH_PAD_3 R/W-0h R/W-0h SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0SCRATCH_PAD_3R/W0hScratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in . Return to the Summary Table. SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h] SCRATCH_PAD_REG_4 is shown in and described in .Return to the Summary Table.Summary Table SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h SCRATCH_PAD_REG_4 Register 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h 7 6 5 4 3 2 1 0 SCRATCH_PAD_4 R/W-0h 7 6 5 4 3 2 1 0 76543210 SCRATCH_PAD_4 SCRATCH_PAD_4 R/W-0h R/W-0h SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. SCRATCH_PAD_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. 7-0SCRATCH_PAD_4R/W0hScratchpad for temporary data storage. The register is reset only when VRTC is disabled. The data is maintained when VINT regulator is disabled, for example during LP_STANDBY state. PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h] PFSM_DELAY_REG_1 is shown in and described in .Return to the Summary Table.Summary Table PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h PFSM_DELAY_REG_1 Register 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 PFSM_DELAY1 R/W-0h 7 6 5 4 3 2 1 0 76543210 PFSM_DELAY1 PFSM_DELAY1 R/W-0h R/W-0h PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_1 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0PFSM_DELAY1R/W0hGeneric delay1 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h] PFSM_DELAY_REG_2 is shown in and described in .Return to the Summary Table.Summary Table PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h PFSM_DELAY_REG_2 Register 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 PFSM_DELAY2 R/W-0h 7 6 5 4 3 2 1 0 76543210 PFSM_DELAY2 PFSM_DELAY2 R/W-0h R/W-0h PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_2 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0PFSM_DELAY2R/W0hGeneric delay2 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h] PFSM_DELAY_REG_3 is shown in and described in .Return to the Summary Table.Summary Table PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h PFSM_DELAY_REG_3 Register 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h 7 6 5 4 3 2 1 0 PFSM_DELAY3 R/W-0h 7 6 5 4 3 2 1 0 76543210 PFSM_DELAY3 PFSM_DELAY3 R/W-0h R/W-0h PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_3 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0PFSM_DELAY3R/W0hGeneric delay3 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in . Return to the Summary Table. PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h] PFSM_DELAY_REG_4 is shown in and described in .Return to the Summary Table.Summary Table PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h PFSM_DELAY_REG_4 Register 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h 7 6 5 4 3 2 1 0 PFSM_DELAY4 R/W-0h 7 6 5 4 3 2 1 0 76543210 PFSM_DELAY4 PFSM_DELAY4 R/W-0h R/W-0h PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) PFSM_DELAY_REG_4 Register Field Descriptions Bit Field Type Reset Description 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) 7-0PFSM_DELAY4R/W0hGeneric delay4 for PFSM use. The step size is defined by PFSM_DELAY_STEP bits. (Default from NVM memory) WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in . Return to the Summary Table. WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h] WD_ANSWER_REG is shown in and described in .Return to the Summary Table.Summary Table WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h WD_ANSWER_REG Register 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h 7 6 5 4 3 2 1 0 WD_ANSWER R/W-0h 7 6 5 4 3 2 1 0 76543210 WD_ANSWER WD_ANSWER R/W-0h R/W-0h WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_ANSWER_REG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. 7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. 7-0WD_ANSWERR/W0hMCU answer byte. The MCU must write the expected reference Answer-x into this register. Each watchdog question requires four answer bytes: - Three answer bytes (Answer-3, Answer-2, Answer-1) must be written in Window-1. - The fourth (final) answer-byte (Answer-0) must be written in Window-2. The number of written answer bytes is tracked with the WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT register. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in . Return to the Summary Table. WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h] WD_QUESTION_ANSW_CNT is shown in and described in .Return to the Summary Table.Summary Table WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h WD_QUESTION_ANSW_CNT Register 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h 7 6 5 4 3 2 1 0 RESERVED WD_ANSW_CNT WD_QUESTION R-0h R-3h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED WD_ANSW_CNT WD_QUESTION RESERVEDWD_ANSW_CNTWD_QUESTION R-0h R-3h R-0h R-0hR-3hR-0h WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_QUESTION_ANSW_CNT Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RESERVED R 0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. 7-6 RESERVED R 0h 7-6RESERVEDR0h 5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 5-4WD_ANSW_CNTR3hCurrent, received watchdog-answer count state. These bits only apply for Watchdog in Q&A mode. 3-0 WD_QUESTION R 0h Watchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. 3-0WD_QUESTIONR0hWatchdog question. The MCU must read (or calculate ) the current watchdog question value to generate correct answers. These bits only apply for Watchdog in Q&A mode. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in . Return to the Summary Table. WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh] WD_WIN1_CFG is shown in and described in .Return to the Summary Table.Summary Table WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh WD_WIN1_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh 7 6 5 4 3 2 1 0 RESERVED WD_WIN1 R/W-0h R/W-7Fh 7 6 5 4 3 2 1 0 76543210 RESERVED WD_WIN1 RESERVEDWD_WIN1 R/W-0h R/W-7Fh R/W-0hR/W-7Fh WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN1_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. 6-0WD_WIN1R/W7FhThese bits are for programming the duration of Watchdog Window-1 (see Watchdoc chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in . Return to the Summary Table. WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh] WD_WIN2_CFG is shown in and described in .Return to the Summary Table.Summary Table WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh WD_WIN2_CFG Register 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh 7 6 5 4 3 2 1 0 RESERVED WD_WIN2 R/W-0h R/W-7Fh 7 6 5 4 3 2 1 0 76543210 RESERVED WD_WIN2 RESERVEDWD_WIN2 R/W-0h R/W-7Fh R/W-0hR/W-7Fh WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_WIN2_CFG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R/W 0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. 7 RESERVED R/W 0h 7RESERVEDR/W0h 6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. 6-0WD_WIN2R/W7FhThese bits are for programming the duration of Watchdog Window-2 (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in . Return to the Summary Table. WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh] WD_LONGWIN_CFG is shown in and described in .Return to the Summary Table.Summary Table WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh WD_LONGWIN_CFG Register 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh 7 6 5 4 3 2 1 0 WD_LONGWIN R/W-FFh 7 6 5 4 3 2 1 0 76543210 WD_LONGWIN WD_LONGWIN R/W-FFh R/W-FFh WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_LONGWIN_CFG Register Field Descriptions Bit Field Type Reset Description 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 7-0WD_LONGWINR/WFFhThese bits are for programming the duration of Watchdog Long Window (see Watchdog chapter). These bits can be only be written when the watchdog is in the Long Window. (Default from NVM memory) WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in . Return to the Summary Table. WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_MODE_REG Register (Offset = 406h) [Reset = 02h] WD_MODE_REG is shown in and described in .Return to the Summary Table.Summary Table WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h WD_MODE_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h 7 6 5 4 3 2 1 0 76543210 RESERVED WD_PWRHOLD WD_MODE_SELECT WD_RETURN_LONGWIN RESERVEDWD_PWRHOLD WD_MODE_SELECT WD_MODE_SELECTWD_RETURN_LONGWIN R/W-0h R/W-0h R/W-1h R/W-0h R/W-0hR/W-0h R/W-1h R/W-1hR/W-0h WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_MODE_REG Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-3 RESERVED R/W 0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. 7-3 RESERVED R/W 0h 7-3RESERVEDR/W0h 2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 2WD_PWRHOLDR/W0hDevice sets WD_PWRHOLD if hardware condition on pin DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see Watchdog chapter). MCU can write this bit to 1. MCU needs to clear this bit to get out of the Long Window: 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 0h = watchdog goes out of the Long Window and starts the first watchdog-sequence when the configured Long Window time-interval elapses 1h = watchdog stays in Long Window 1 WD_MODE_SELECT R/W 1h Watchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 1WD_MODE_SELECTR/W1hWatchdog mode-select: MCU can set this to required value only when watchdog is in the Long Window. 0h = Trigger Mode 1h = Q&A mode. 0h = Trigger Mode 1h = Q&A mode. 0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. 0WD_RETURN_LONGWINR/W0hMCU can set this bit to put the watchdog from operating back to the Long Window (see Watchdog chapter): 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. 0h = Watchdog continues operating 1h = Watchdog returns to Long-Window after completion of the current watchdog-sequence. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in . Return to the Summary Table. WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah] WD_QA_CFG is shown in and described in .Return to the Summary Table.Summary Table WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah WD_QA_CFG Register 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah 7 6 5 4 3 2 1 0 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah 7 6 5 4 3 2 1 0 76543210 WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED WD_QA_FDBKWD_QA_LFSRWD_QUESTION_SEED R/W-0h R/W-0h R/W-Ah R/W-0hR/W-0hR/W-Ah WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_QA_CFG Register Field Descriptions Bit Field Type Reset Description 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. 7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 7-6WD_QA_FDBKR/W0hFeedback configuration bits for the watchdog question. These bits control the sequence of the generated questions and respective reference answers (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 5-4WD_QA_LFSRR/W0hLFSR-equation configuration bits for the watchdog question (see Watchdog chapter). These bits are only used for the watchdog in Q&A mode. These bits can be only be written when the watchdog is in the Long Window. 3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. 3-0WD_QUESTION_SEEDR/WAhThe watchdog question-seed value (see Watchdog chapter). The MCU updates the question-seed value to generate a set of new questions. These bits can be only be written when the watchdog is in the Long Window. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in . Return to the Summary Table. WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h] WD_ERR_STATUS is shown in and described in .Return to the Summary Table.Summary Table WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h WD_ERR_STATUS Register 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h 7 6 5 4 3 2 1 0 76543210 WD_RST_INT WD_FAIL_INT WD_ANSW_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_TRIG_EARLY WD_TIMEOUT WD_LONGWIN_TIMEOUT_INT WD_RST_INTWD_FAIL_INT WD_ANSW_ERR WD_ANSW_ERR WD_SEQ_ERR WD_SEQ_ERR WD_ANSW_EARLY WD_ANSW_EARLYWD_TRIG_EARLYWD_TIMEOUTWD_LONGWIN_TIMEOUT_INT R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0hR/W1C-0hR/W1C-0hR/W1C-0h WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_ERR_STATUS Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. 7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 7WD_RST_INTR/W1C0hLatched status bit to indicate that the device went through warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). Write 1 to clear. 6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 6WD_FAIL_INTR/W1C0hLatched status bit to indicate that the watchdog has cleared the ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. Write 1 to clear. 5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 5WD_ANSW_ERRR/W1C0hLatched status bit to indicate that the watchdog has detected an incorrect answer-byte. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 4WD_SEQ_ERRR/W1C0hLatched status bit to indicate that the watchdog has detected an incorrect sequence of the answer-bytes. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 3WD_ANSW_EARLYR/W1C0hLatched status bit to indicate that the watchdog has received the final answer-byte in Window-1. Write 1 to clear. This bit only applies for Watchdog in Q&A mode. 2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 2WD_TRIG_EARLYR/W1C0hLatched status bit to indicate that the watchdog has received the watchdog-trigger in Window-1. Write 1 to clear. This bit only applies for Watchdog in Trigger mode. 1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 1WD_TIMEOUTR/W1C0hLatched status bit to indicate that the watchdog has detected a time-out event in the started watchdog sequence. Write 1 to clear. 0 WD_LONGWIN_TIMEOUT_INT R/W1C 0h Latched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. 0WD_LONGWIN_TIMEOUT_INTR/W1C0hLatched status bit to indicate that device went through warm reset due to elapse of Long Window time-interval. Write 1 to clear interrupt. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in . Return to the Summary Table. WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_THR_CFG Register (Offset = 409h) [Reset = FFh] WD_THR_CFG is shown in and described in .Return to the Summary Table.Summary Table WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h WD_THR_CFG Register 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h 7 6 5 4 3 2 1 0 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h 7 6 5 4 3 2 1 0 76543210 WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH WD_RST_ENWD_ENWD_FAIL_THWD_RST_TH R/W-1h R/W-1h R/W-7h R/W-7h R/W-1hR/W-1hR/W-7hR/W-7h WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_THR_CFG Register Field Descriptions Bit Field Type Reset Description 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. 7 WD_RST_EN R/W 1h Watchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 7WD_RST_ENR/W1hWatchdog reset configuration bit: This bit can be only be written when the watchdog is in the Long Window. 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]) 1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). 6 WD_EN R/W 1h Watchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 6WD_ENR/W1hWatchdog enable configuration bit: This bit can be only be written when the watchdog is in the Long Window. (Default from NVM memory) 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all other interrupt status bits are cleared 1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if: - watchdog is out of the Long Window - WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0] - WD_FIRST_OK=1 - all other interrupt status bits are cleared. 5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 5-3WD_FAIL_THR/W7hConfiguration bits for the 1st threshold of the watchdog fail counter: Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]. These bits can be only be written when the watchdog is in the Long Window. 2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. 2-0WD_RST_THR/W7hConfiguration bits for the 2nd threshold of the watchdog fail counter: Device goes through warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0]). These bits can be only be written when the watchdog is in the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in . Return to the Summary Table. WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h] WD_FAIL_CNT_REG is shown in and described in .Return to the Summary Table.Summary Table WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h WD_FAIL_CNT_REG Register 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h 7 6 5 4 3 2 1 0 76543210 RESERVED WD_BAD_EVENT WD_FIRST_OK RESERVED WD_FAIL_CNT RESERVEDWD_BAD_EVENTWD_FIRST_OKRESERVEDWD_FAIL_CNT R-0h R-0h R-1h R-0h R-0h R-0hR-0hR-1hR-0hR-0h WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. WD_FAIL_CNT_REG Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 RESERVED R 0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. 7 RESERVED R 0h 7RESERVEDR0h 6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 6WD_BAD_EVENTR0hStatus bit to indicate that the watchdog has detected a bad event in the current watchdog sequence. The device clears this bit at the end of the watchdog sequence. 5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 5WD_FIRST_OKR1hStatus bit to indicate that the watchdog has detected a good event. The device clears this bit when the watchdog goes to the Long Window. 4 RESERVED R 0h 4RESERVEDR0h 3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. 3-0WD_FAIL_CNTR0hStatus bits to indicate the value of the Watchdog Fail Counter. The device clears these bits when the watchdog goes to the Long Window. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More generic topics and some examples are outlined here. To help with new designs, a variety of tools and documents are available in the product folder. Some examples are: Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operation GUI to communicate with the PMIC Schematic and layout checklist Typical Application The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing, the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs used in the system as well as the external components used with it. The following section provides a generic case. For specific cases, refer to the relevant user's guide based on the orderable part number. Powering a Processor In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents. Example Power Map Design Requirements The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise Detailed Design Procedure Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) Application Curves BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V Power Supply Recommendations The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Layout Layout Guidelines A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below: Ground connection of capacitor at VOUT_LDOVINT pin Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software. Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers A more complete list of layout recommendations can be found in the Schematic and layout checklist. Layout Example A 20220110 Updated Layout Example figureyes Example PMIC Layout This example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Application Information The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More generic topics and some examples are outlined here. To help with new designs, a variety of tools and documents are available in the product folder. Some examples are: Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operation GUI to communicate with the PMIC Schematic and layout checklist Application Information The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More generic topics and some examples are outlined here. To help with new designs, a variety of tools and documents are available in the product folder. Some examples are: Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operation GUI to communicate with the PMIC Schematic and layout checklist The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More generic topics and some examples are outlined here. To help with new designs, a variety of tools and documents are available in the product folder. Some examples are: Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operation GUI to communicate with the PMIC Schematic and layout checklist The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More generic topics and some examples are outlined here. TPS6593-Q1 product folder TPS6593-Q1 product folderTPS6593-Q1To help with new designs, a variety of tools and documents are available in the product folder. Some examples are: Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operation GUI to communicate with the PMIC Schematic and layout checklist Evaluation module and user guide which allow testing of various orderable part numbers, including multi-PMIC operationGUI to communicate with the PMIC Schematic and layout checklist Schematic and layout checklist Typical Application The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing, the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs used in the system as well as the external components used with it. The following section provides a generic case. For specific cases, refer to the relevant user's guide based on the orderable part number. Powering a Processor In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents. Example Power Map Design Requirements The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise Detailed Design Procedure Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) Application Curves BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V Typical Application The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing, the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs used in the system as well as the external components used with it. The following section provides a generic case. For specific cases, refer to the relevant user's guide based on the orderable part number. The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing, the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs used in the system as well as the external components used with it. The following section provides a generic case. For specific cases, refer to the relevant user's guide based on the orderable part number. The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing, the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs used in the system as well as the external components used with it. The following section provides a generic case. For specific cases, refer to the relevant user's guide based on the orderable part number. Powering a Processor In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents. Example Power Map Design Requirements The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise Detailed Design Procedure Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) Powering a Processor In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents. Example Power Map In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents. Example Power Map In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1 buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents.+1 Example Power Map Example Power Map Design Requirements The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise Design Requirements The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise The design requirements for the sample processor in are outlined below: VDD CORE rail requires 0.8 V, 5 A MCU rail requires 0.85 V, 2 A CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise VDD CORE rail requires 0.8 V, 5 AMCU rail requires 0.85 V, 2 ACPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage ScalingLPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitiveVDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra low noise Detailed Design Procedure Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) Detailed Design Procedure Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance. Using this configuration information, components can be chosen to use with the PMIC. Based on the above requirements, the PMIC has been configured with the connections outlined in . BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has better noise performance.Using this configuration information, components can be chosen to use with the PMIC. VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — VCCA The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Recommended VCCA Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION COMPONENTMANUFACTURERPART NUMBERVALUEEIA SIZE CODESIZE (mm)USED for VALIDATION Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes CapacitorMurataGCM155C71A474KE360.47 µF, 10 V, X7R04021.0 × 0.5Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 — CapacitorTDKCGA2B3X7S1A474K050BB0.47 µF, 10 V, X7R04021.0 × 0.5— Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Internal LDOs The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization. The recommended components are shown below. Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Recommended Internal LDO Components COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION COMPONENT MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) USED for VALIDATION COMPONENTMANUFACTURERPART NUMBERVALUEEIA SIZE CODESIZE (mm)USED for VALIDATION Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — Capacitor Murata GCM188R70J225KE22 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — CapacitorMurataGCM188R70J225KE222.2 µF, 6.3 V, X7R06031.6 × 0.8— Capacitor TDK CGA3E1X7S1C225M080AC 2.2 µF, 6.3 V, X7R 0603 1.6 × 0.8 — CapacitorTDKCGA3E1X7S1C225M080AC2.2 µF, 6.3 V, X7R06031.6 × 0.8— Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Crystal Oscillator A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible. CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact. Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and OSC32KOUT pins, a simplified oscillator schematic is shown in to determine what external load capacitors are needed for the crystal. Crystal Oscillator Component Selection Crystal Oscillator Component SelectionCIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around 1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To achieve the required load capacitance (CL) for the oscillator, is used. This equation assumes that the crystal series capacitance is negligible.IN1IN2PCB1PCB2LCL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2))LL1PCB1IN1L2PCB2IN2L1PCB1IN1L2PCB2IN2Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor values typically available results in the following general capacitor recommendations. If more precise matching is desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance. Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has the opposite impact.L1L2L1LPCBIN Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 Approximate Crystal Oscillator Load Capacitors Crystal CL (pF) Component CL1 = CL2 (pF) 6 0 9 6 12.5 12.5 Crystal CL (pF) Component CL1 = CL2 (pF) Crystal CL (pF) Component CL1 = CL2 (pF) Crystal CL (pF)LComponent CL1 = CL2 (pF)L1L2 6 0 9 6 12.5 12.5 6 0 60 9 6 96 12.5 12.5 12.512.5The recommended components using a 9-pF oscillator as an example are in . If an alternate load capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above. Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Recommended Crystal Oscillator Components for 9-pF Crystal Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation ComponentMANUFACTURERPART NUMBERVALUEEIA size codeSIZE (mm)Used for Validation Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes CapacitorMurataGCM155R71C104JA55D100-nF, 16-V, X7R04021.0 x 0.5Yes Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 - CapacitorTDKCGA2B1X7R1C104K050BC100-nF, 16-V, X7R04021.0 x 0.5- Crystal NDK NX3215SD-32.768K-STD-MUS-6 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 Yes CrystalNDKNX3215SD-32.768K-STD-MUS-632.768-kHz, ±20 ppm, 9-pF3.2 x 1.5 x 0.9Yes Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 ppm, 9-pF 3.2 x 1.5 x 0.9 - CrystalAbraconABS07AIG-32.768kHz-9-T32.768-kHz, ±20 ppm, 9-pF3.2 x 1.5 x 0.9- Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 Yes CapacitorMurataGCM1555C1H6R0CA166-pF, 50-V, C0G/NP004021.0 x 0.5Yes Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, C0G/NP0 0402 1.0 x 0.5 - CapacitorTDKCGA2B2C0G1H060D050BA6-pF, 50-V, C0G/NP004021.0 x 0.5- Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Buck Input Capacitors For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement. Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22-µF, 10-V capacitor is recommended. See #GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 for the recommended input capacitors, and the for more information about component placement.#GUID-D8184B9D-5ED1-4F76-9309-A1795E87DDBE/SLVSE827556-1 Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - Recommended Buck Input Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURERPART NUMBERVALUEEIA size codeSIZE (mm)Used for Validation TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes TDKCGA4J1X7S1C106K125AC10 µF, 16 V, X7R08052.0 × 1.25 × 1.25Yes Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 - MurataGCM21BR71A106KE2210 µF, 10 V, X7R08052.0 × 1.25 × 1.25- Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Buck Output Capacitors A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes A 20220110 Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes A20220110Updated PDN example figure, and updated the table with the Local and POL Capacitors used for Buck Use Case Validationyes yes The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. To achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution. Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant. is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. Power input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. The buck converters have seven potential NVM configurations which can impact the output capacitor selection. Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below. The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter. It is recommended to place all large capacitors near the inductor. See for more information about component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. ESRESRTo achieve better ripple and transient performance, additional high pass filter caps are recommended to compensate for the parasitic impedance due to board routing and provide faster transient response to a load step. These caps are placed close to the point of load and are also the input capacitors of the load. These capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps are recommended, as their high performance can help reduce the total number of capacitors required which simplifies board layout design and saves board area. They also help to reduce the total cost of the solution.Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased time constant.OUT is an example power distribution network (PDN) of local and POL caps at the output of a buck for optimal ripple and transient performance. lists the local and POL capacitors used to validate the buck transient and ripple performance specified in the parametric table for each of the seven configurations. lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the desired requirements as these are provided as guidelines. Example Power Distribution Network (PDN) of Local and POL Capacitors Example Power Distribution Network (PDN) of Local and POL Capacitors Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 Local and POL Capacitors used for Buck Use Case Validation Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) Configuration COUT L CL / phase RPCB per phase LPCB per phase CPOL1 (total) CPOL2 (total) ConfigurationCOUT OUTLCL / phaseLRPCB per phase PCBLPCB per phase PCBCPOL1 (total)POL1CPOL2 (total)POL2 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Low Load Step, Single Phase with low COUT OUTOUT Low Low 470 nH 470 nH 22 uF x 1 22 uF x 18 mΩ2.5 nH 1 uF x 1 1 uF x 1 4.4 MHz VOUT Less than 1.9 V, Multiphase Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Less than 1.9 V, MultiphaseOUTLow220 nH47 µF × 28 mΩ2.5 nH10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 High220 nH47 µF × 48 mΩ2.5 nH10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 4.4 MHz VOUT Less than 1.9 V, Single Phase with high COUT OUTOUTLow220 nH47 µF × 18 mΩ2.5 nH10 µF × 4 High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2 High220 nH47 µF × 48 mΩ2.5 nH10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2 4.4 MHz VOUT Less than 1.9 V, Single Phase with low COUT OUTOUTLow220 nH22 µF × 18 mΩ2.5 nH10 µF × 2 High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4 High220 nH47 µF × 18 mΩ2.5 nH10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V) Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only (VIN Greater than 4.5 V)OUTINLow470 nH47 µF × 127 mΩ6 nH10 µF × 4 High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2 High470 nH47 µF × 227 mΩ6 nH10 µF × 2 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase OnlyOUTINLow1000 nH47 µF × 38 mΩ2.5 nH10 µF × 4 High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1 High1000 nH47 µF × 38 mΩ2.5 nH10 µF × 4680 µF × 1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single PhaseOUTLow470 nH47 µF × 34.1 mΩ1.3 nH10 µF × 4 High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1 High470 nH47 µF × 34.1 mΩ1.3 nH10 µF × 4680 µF × 1 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2 2.2 MHz Full VOUT and Full VIN Range, Single Phase OnlyOUTINLow1000 nH47 µF × 34.1 mΩ1.3 nH10 µF × 2 High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2 High1000 nH100 µF × 44.1 mΩ1.3 nH10 µF × 2 DDR VTT Termination, 2.2 MHz Single Phase Only - 470 nH 22 µF × 1 27 mΩ 6 nH 10 µF × 1 + 22 µF x 1 DDR VTT Termination, 2.2 MHz Single Phase Only-470 nH22 µF × 127 mΩ6 nH10 µF × 1 + 22 µF x 1 RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases. RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total resistance is divided by the number of phases.PCBLPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative paths. For multi-phase outputs the total inductance is divided by the number of phases.PCBPower input and output wiring parasitic resistance and inductance must be minimized. Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Recommended Buck Converter Output Capacitor Components MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation MANUFACTURERPART NUMBERVALUEEIA Size CodeSIZE (mm)Used for Validation Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Murata NFM15HC105D0G 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes MurataNFM15HC105D0G 1 µF, 4 V, X7S04021.0 × 0.5Yes TDK YFF18AC0J105M 1 µF, 6.3 V 0603 1.6 × 0.8 - TDKYFF18AC0J105M 1 µF, 6.3 V06031.6 × 0.8- Murata NFM18HC106D0G 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes MurataNFM18HC106D0G 10 µF, 4 V, X7S06031.6 × 0.8Yes TDK YFF18AC0G475M 4.7 µF, 6.3 V 0603 1.6 × 0.8 - TDKYFF18AC0G475M 4.7 µF, 6.3 V06031.6 × 0.8- Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes MurataGCM31CR71A226KE0222 µF, 10 V, X7R12063.2 × 1.6Yes Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - MurataGCM21BD7CGA5L1X7R0J226MT0J226M22 µF, 6.3 V, X7T08052.0 × 1.25 × 1.25- TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 - TDKCGA5L1X7R0J226MT22 µF, 6.3 V, X7R12063.2 × 1.6- TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 - TDKCGA4J1X7T0J226MT22 µF, 6.3 V, X7T08052.0 × 1.25 × 1.25- Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes MurataGCM32ER70J476ME1947 µF, 6.3 V, X7R12103.2 × 2.5Yes Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 - MurataGCM31CD70G476M47 µF, 4 V, X7T12063.2 × 1.6- TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 - TDKCGA6P1X7S1A476MT47 µF, 10 V, X7S12103.2 × 2.5- TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 - TDKCGA5L1X7T0G476MT47 µF, 4 V, X7T12063.2 × 1.6- Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes MurataGCM32ED70G107MEC4100 µF, 4 V, X7S12103.2 × 2.5Yes TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 - TDKCGA6P1X7T0G107MT100 µF, 4 V, X7T12103.2 × 2.5- Kemet T510X687K006ATA023 680 µF, 6.3 V 2917 7.4 × 5.0 Yes KemetT510X687K006ATA023 680 µF, 6.3 V29177.4 × 5.0Yes Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes Murata Murata GCM188D70E226ME36D GCM188D70E226ME36D 22uF, 2.5 V, X7T 22uF, 2.5 V, X7T 0603 06031.6 × 0.8 Yes Yes Low ESL 3-terminal cap. Dependent on availability; may switch to 470 µF. Low ESL 3-terminal cap.Dependent on availability; may switch to 470 µF. Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - Buck Inductors Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance. Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - Inductor must be chosen based on the buck configuration. See for the appropriate nominal inductance.Recommended inductors based on these requirements are shown below. Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - Recommended Buck Converter Inductors MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation MANUFACTURERPART NUMBERVALUESIZE (mm)Used for Validation TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDKTFM322512ALMA1R0MTAA1000 nH, 4 A Max, 150 °C3.2 × 2.5 × 1.2Yes Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 - MurataDFE322520FD-1R0M=P21000 nH, 4.1 A Max, 125 °C3.2 x 2.5 x 2.0- TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes TDKTFM322512ALMAR47MTAA470 nH, 5.3 A Max, 150 °C3.2 × 2.5 × 1.2Yes TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 - TDKTFM252012ALMAR47MTAA470 nH, 4.9 A Max, 150 °C2.5 x 2.0 x 1.2- Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes MurataDFE2HCAHR47MJ0470 nH, 4.5 A Max, 150 °C2.5 × 2.0 × 1.2 Yes Yes TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes TDKTFM322512ALMAR22MTAA220 nH, 7.6 A Max, 150 °C3.2 x 2.5 x 1.2Yes TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 - TDKTFM201610ALMAR24MTAA220 nH, 5 A Max, 150 °C2.0 x 1.6 x 1.2- Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 - MurataDFE2MCAHR24MJ0240 nH, 4.2 A Max, 150 °C2.0 x 1.6 x 1.2- LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors. Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins as possible. See the for more information about component placement. See #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 for the recommended input capacitors.#GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSE827556-40 Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - Recommended LDO Input Capacitors GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD.html#unique_178_Connect_42_SLVSCO4X-8939-40 #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSCO4X-8939-40 #GUID-FA0C0FA4-C85A-4C5D-A11A-1142E4976CAD/SLVSCO4X-8939-40 MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURERPART NUMBERVALUEEIA size codeSIZE (mm)Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes TDKCGA3E1X7S1C225M080AC2.2-µF, 16-V, X7S06031.6 x 0.8Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 - MurataGCM188R70J225KE222.2-µF, 16-V, X7R06031.6 x 0.8- Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — LDO Output Capacitors All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output. Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system must be evaluated for stability. See #GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 for the specific part number of the recommended output capacitors. For BOM optimization purposes, the same capacitor part number was used for LDO input and LDO output.#GUID-5DEE2FDB-B5C8-4642-976B-0018064C6782/SLVSE827556-41 Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — Recommended LDO Output Capacitors MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation MANUFACTURERPART NUMBERVALUEEIA size codeSIZE (mm)Used for Validation TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes TDKCGA3E1X7S1C225M080AC2.2-µF, 16-V, X7S06031.6 × 0.8Yes Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 — MurataGCM188R70J225KE222.2-µF, 16-V, X7R06031.6 × 0.8— Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) Digital Signal Connections A 20220110 Updated the recommendations for the Digital Signal Connections yes A 20220110 Updated the recommendations for the Digital Signal Connections yes A 20220110 Updated the recommendations for the Digital Signal Connections yes A20220110Updated the recommendations for the Digital Signal Connections yes yes The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors. Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF) The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See #GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 for the recommended bypass capacitors.#GUID-D533A277-82EE-4900-906B-2670DBA45A75/SLVSE827556-03 Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - Recommended VIO_IN Capacitor Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation Component MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation ComponentMANUFACTURERPART NUMBERVALUEEIA size codeSIZE (mm)Used for Validation Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes CapacitorMurataGCM155C71A474KE360.47 µF, 10 V, X7S04021.0 x 0.5Yes Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 - CapacitorTDKCGA2B3X7S1A474K050BB0.47 µF, 10 V, X7S04021.0 x 0.5-For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF)22b Application Curves BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V Application Curves BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase BUCK Efficiency at 3.3 V or 5 V Input Voltage VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VVOUT_Bn = 1.8 V VOUT_BnFsw = 2.2 MHz4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1.8 V VOUT_Bn4-Phase BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 VPVIN_BnVVOUT_Bn = 1.8 VVOUT_BnAuto Mode BUCK Efficiency in Varied Phase Configuration, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode BUCK Efficiency in Varied Phase Configuration, 5 V InputData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 VPVIN_BnVVOUT_Bn = 1.8 VVOUT_BnAuto Mode BUCK Efficiency with different VOUT_Bn, 3.3 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 3.3 V InputData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode OUT_Bn VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode VPVIN_Bn = 3.3 V PVIN_BnSingle-PhaseForced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V Input Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode BUCK Efficiency with different VOUT_Bn, 5 V InputData valid for all bucks up to IOUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode OUT_Bn VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode VPVIN_Bn = 5 V PVIN_BnSingle-PhaseForced-PWM Mode BUCK Efficiency at different T_A, Auto Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Auto ModeAData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnSingle-Phase BUCK Efficiency at different T_A, Forced-PWM Mode Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase BUCK Efficiency at different T_A, Forced-PWM ModeAData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnSingle-Phase Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Temperature Drift, Forced-PWM Mode, Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 3.3 V Input VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase Buck Load Regulation with 5 V Input VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn4-Phase Buck Load Regulation, with Fsw = 2.2 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 2.2 MHzData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnAuto Mode Buck Load Regulation, with Fsw = 4.4 MHz Data valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Load Regulation, with Fsw = 4.4 MHzData valid for all bucks up to IOUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode OUT_Bn VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnAuto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 2.2 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnAuto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode Buck Line Regulation, with Fsw = 4.4 MHz VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnAuto Mode Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - Single Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 10 mALOAD Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 2-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 10 mALOAD Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 3-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 10 mALOAD Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Buck Output Ripple - 4-Phase, Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 10 mALOAD Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz, Forced-PWM Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PWM mode to PFM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 2.2 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Buck Transient from PFM mode to PWM mode, 4.4 MHz, Single Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_BnILOAD = 200 mALOAD Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto ModeILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto ModeILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 2.2 MHz, Forced-PWM ModeILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 4-Phase, 4.4 MHz, Forced-PWM ModeILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto ModeILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto ModeILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 2.2 MHz, Forced-PWM ModeILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 3-Phase, 4.4 MHz, Forced-PWM ModeILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto ModeILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto ModeILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 2.2 MHz, Forced-PWM ModeILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - 2-Phase, 4.4 MHz, Forced-PWM ModeILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck4, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Auto ModeILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck4, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Auto ModeILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 2.2 MHz, Forced-PWM ModeILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck4, 4.4 MHz, Forced-PWM ModeILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck5, 2.2 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Auto ModeILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck5, 4.4 MHz, Auto Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Auto ModeILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 2.2 MHz, Forced-PWM ModeILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM Mode ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Buck Load Step Transient - Buck5, 4.4 MHz, Forced-PWM ModeILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V LOADRF VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V PVIN_BnVVOUT_Bn = 1 VVOUT_Bn LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V LDO1/2/3 Load Regulation, Vout = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 VIN(LDOn)VOUT(LDOn) = 1.8 VOUT(LDOn) LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V LDO1/2/3 Load Regulation, Vout = 3 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V VIN(LDOn) = 3.3 VIN(LDOn)VOUT(LDOn) = 3.0 VOUT(LDOn) LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA LDO1/2/3 Line Regulation over Temperature, Vout = 0.8 V VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 0.8 VOUT(LDOn)IOUT(LDOn) = 500 mA OUT(LDOn) LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA LDO1/2/3 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA VOUT(LDOn) = 1.8 VOUT(LDOn)IOUT(LDOn) = 50 mA OUT(LDOn) LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 3.3 V in Bypass Mode to 1.8 V Linear Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 VIN(LDOn)IOUT(LDOn) = 50 mA OUT(LDOn) LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA LDO1/2/3 Transition from 1.8 V in Linear Mode to 3.3 V in Bypass Mode VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 VIN(LDOn)IOUT(LDOn) = 50 mA OUT(LDOn) LDO1/2/3 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LDO1/2/3 Load Step TransientILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V LOADRF VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V VIN(LDOn) = 3.3 VIN(LDOn)VOUT(LDOn) = 1 VOUT(LDOn) LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V LDO4 Load Regulation, Vout = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V VIN(LDO4) = 3.3 VIN(LDO4)VOUT(LDO4) = 1.8 VOUT(LDO4) LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V LDO4 Load Regulation, Vout = 3 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VIN(LDO4) = 3.3 VIN(LDO4)VOUT(LDO4) = 3.0 VOUT(LDO4) LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA LDO4 Line Regulation over Temperature, Vout = 1.8 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA VOUT(LDO4) = 1.8 VOUT(LDO4)IOUT(LDO4) = 300 mA OUT(LDO4) LDO4 Load Step Transient ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V LDO4 Load Step TransientILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V LOADRF VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V VIN(LDO4) = 3.3 VIN(LDO4)VOUT(LDO4) = = 1 VOUT(LDO4) Power Supply Recommendations The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Power Supply Recommendations The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Layout Layout Guidelines A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below: Ground connection of capacitor at VOUT_LDOVINT pin Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software. Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers A more complete list of layout recommendations can be found in the Schematic and layout checklist. Layout Example A 20220110 Updated Layout Example figureyes Example PMIC Layout This example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways. Layout Layout Guidelines A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below: Ground connection of capacitor at VOUT_LDOVINT pin Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software. Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers A more complete list of layout recommendations can be found in the Schematic and layout checklist. Layout Guidelines A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes A 20220110 Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes A20220110Updated Layout Guidelines with respect to output capacitor on VOUT_LDOVINT pinyes yes The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below: Ground connection of capacitor at VOUT_LDOVINT pin Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software. Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers A more complete list of layout recommendations can be found in the Schematic and layout checklist. The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below: Ground connection of capacitor at VOUT_LDOVINT pin Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software. Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers A more complete list of layout recommendations can be found in the Schematic and layout checklist. The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results.TPS6593-Q1 With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane.ININThe output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop.OUTInput for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin.If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback.2PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx.For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below:TPS6593-Q1 Ground connection of capacitor at VOUT_LDOVINT pin Ground connection of capacitor at VOUT_LDOVINT pin Ground connection of capacitor at VOUT_LDOVINT pinDue to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.θJAθJBJOverall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers: 0.5oz for signal layers at least 1.5oz for top layer and other plane layers 0.5oz for signal layers at least 1.5oz for top layer and other plane layers 0.5oz for signal layersat least 1.5oz for top layer and other plane layersA more complete list of layout recommendations can be found in the Schematic and layout checklist.Schematic and layout checklist Layout Example A 20220110 Updated Layout Example figureyes Example PMIC Layout This example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways. Layout Example A 20220110 Updated Layout Example figureyes A 20220110 Updated Layout Example figureyes A 20220110 Updated Layout Example figureyes A20220110Updated Layout Example figureyes yes Example PMIC Layout This example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways. Example PMIC Layout This example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways. Example PMIC Layout Example PMIC LayoutThis example shows a top and bottom layout of the key power components and the crystal oscillator based on the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways.EVM design files Device and Documentation Support Device Support Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. Device Nomenclature The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and definitions, see the TI glossary . ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter APE Application Processor Engine AVS Adaptive Voltage Scaling DVS Dynamic Voltage Scaling GPIO General-Purpose Input and Output LDO Low-Dropout voltage linear regulator PM Power Management PMIC Power-Management Integrated Circuit PSRR Power Supply Rejection Ratio RTC Real-Time Clock NA Not Applicable NVM Non-Volatile Memory ESR Equivalent Series Resistance DCR DC Resistance of an inductor PDN Power Delivery Network PMU Power Management Unit PFM Pulse Frequency Modulation PWM Pulse Width Modulation EMC Electromagnetic Compatibility PLL Phase Locked Loop SPI Serial Peripheral Interface SPMI System Power Management Interface I2C Inter-Integrated Circuit PFSM Pre-configured Finite State Machine UV Undervoltage OV Overvoltage POR Power On Reset UVLO Undervoltage Lockout OVP Overvoltage Protection EPC Embedded Power Controller FSD First Supply Detection ESM Error Signal Monitor MCU Micro Controller Unit SoC System on Chip BIST Built-In Self-Test LBIST Logic Built-In Self-Test CRC Cyclic Redundancy Check VMON Voltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) Documentation Support Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support Device Support Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. Device Support Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. Device Nomenclature The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and definitions, see the TI glossary . ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter APE Application Processor Engine AVS Adaptive Voltage Scaling DVS Dynamic Voltage Scaling GPIO General-Purpose Input and Output LDO Low-Dropout voltage linear regulator PM Power Management PMIC Power-Management Integrated Circuit PSRR Power Supply Rejection Ratio RTC Real-Time Clock NA Not Applicable NVM Non-Volatile Memory ESR Equivalent Series Resistance DCR DC Resistance of an inductor PDN Power Delivery Network PMU Power Management Unit PFM Pulse Frequency Modulation PWM Pulse Width Modulation EMC Electromagnetic Compatibility PLL Phase Locked Loop SPI Serial Peripheral Interface SPMI System Power Management Interface I2C Inter-Integrated Circuit PFSM Pre-configured Finite State Machine UV Undervoltage OV Overvoltage POR Power On Reset UVLO Undervoltage Lockout OVP Overvoltage Protection EPC Embedded Power Controller FSD First Supply Detection ESM Error Signal Monitor MCU Micro Controller Unit SoC System on Chip BIST Built-In Self-Test LBIST Logic Built-In Self-Test CRC Cyclic Redundancy Check VMON Voltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) Device Nomenclature The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and definitions, see the TI glossary . ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter APE Application Processor Engine AVS Adaptive Voltage Scaling DVS Dynamic Voltage Scaling GPIO General-Purpose Input and Output LDO Low-Dropout voltage linear regulator PM Power Management PMIC Power-Management Integrated Circuit PSRR Power Supply Rejection Ratio RTC Real-Time Clock NA Not Applicable NVM Non-Volatile Memory ESR Equivalent Series Resistance DCR DC Resistance of an inductor PDN Power Delivery Network PMU Power Management Unit PFM Pulse Frequency Modulation PWM Pulse Width Modulation EMC Electromagnetic Compatibility PLL Phase Locked Loop SPI Serial Peripheral Interface SPMI System Power Management Interface I2C Inter-Integrated Circuit PFSM Pre-configured Finite State Machine UV Undervoltage OV Overvoltage POR Power On Reset UVLO Undervoltage Lockout OVP Overvoltage Protection EPC Embedded Power Controller FSD First Supply Detection ESM Error Signal Monitor MCU Micro Controller Unit SoC System on Chip BIST Built-In Self-Test LBIST Logic Built-In Self-Test CRC Cyclic Redundancy Check VMON Voltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and definitions, see the TI glossary . ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter APE Application Processor Engine AVS Adaptive Voltage Scaling DVS Dynamic Voltage Scaling GPIO General-Purpose Input and Output LDO Low-Dropout voltage linear regulator PM Power Management PMIC Power-Management Integrated Circuit PSRR Power Supply Rejection Ratio RTC Real-Time Clock NA Not Applicable NVM Non-Volatile Memory ESR Equivalent Series Resistance DCR DC Resistance of an inductor PDN Power Delivery Network PMU Power Management Unit PFM Pulse Frequency Modulation PWM Pulse Width Modulation EMC Electromagnetic Compatibility PLL Phase Locked Loop SPI Serial Peripheral Interface SPMI System Power Management Interface I2C Inter-Integrated Circuit PFSM Pre-configured Finite State Machine UV Undervoltage OV Overvoltage POR Power On Reset UVLO Undervoltage Lockout OVP Overvoltage Protection EPC Embedded Power Controller FSD First Supply Detection ESM Error Signal Monitor MCU Micro Controller Unit SoC System on Chip BIST Built-In Self-Test LBIST Logic Built-In Self-Test CRC Cyclic Redundancy Check VMON Voltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and definitions, see the TI glossary . TI glossary TI glossary ADC Analog-to-Digital Converter DAC Digital-to-Analog Converter APE Application Processor Engine AVS Adaptive Voltage Scaling DVS Dynamic Voltage Scaling GPIO General-Purpose Input and Output LDO Low-Dropout voltage linear regulator PM Power Management PMIC Power-Management Integrated Circuit PSRR Power Supply Rejection Ratio RTC Real-Time Clock NA Not Applicable NVM Non-Volatile Memory ESR Equivalent Series Resistance DCR DC Resistance of an inductor PDN Power Delivery Network PMU Power Management Unit PFM Pulse Frequency Modulation PWM Pulse Width Modulation EMC Electromagnetic Compatibility PLL Phase Locked Loop SPI Serial Peripheral Interface SPMI System Power Management Interface I2C Inter-Integrated Circuit PFSM Pre-configured Finite State Machine UV Undervoltage OV Overvoltage POR Power On Reset UVLO Undervoltage Lockout OVP Overvoltage Protection EPC Embedded Power Controller FSD First Supply Detection ESM Error Signal Monitor MCU Micro Controller Unit SoC System on Chip BIST Built-In Self-Test LBIST Logic Built-In Self-Test CRC Cyclic Redundancy Check VMON Voltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) ADC Analog-to-Digital Converter ADCAnalog-to-Digital Converter DAC Digital-to-Analog Converter DACDigital-to-Analog Converter APE Application Processor Engine APEApplication Processor Engine AVS Adaptive Voltage Scaling AVSAdaptive Voltage Scaling DVS Dynamic Voltage Scaling DVSDynamic Voltage Scaling GPIO General-Purpose Input and Output GPIOGeneral-Purpose Input and Output LDO Low-Dropout voltage linear regulator LDOLow-Dropout voltage linear regulator PM Power Management PMPower Management PMIC Power-Management Integrated Circuit PMICPower-Management Integrated Circuit PSRR Power Supply Rejection Ratio PSRRPower Supply Rejection Ratio RTC Real-Time Clock RTCReal-Time Clock NA Not Applicable NANot Applicable NVM Non-Volatile Memory NVMNon-Volatile Memory ESR Equivalent Series Resistance ESREquivalent Series Resistance DCR DC Resistance of an inductor DCRDC Resistance of an inductor PDN Power Delivery Network PDNPower Delivery Network PMU Power Management Unit PMUPower Management Unit PFM Pulse Frequency Modulation PFMPulse Frequency Modulation PWM Pulse Width Modulation PWMPulse Width Modulation EMC Electromagnetic Compatibility EMCElectromagnetic Compatibility PLL Phase Locked Loop PLLPhase Locked Loop SPI Serial Peripheral Interface SPISerial Peripheral Interface SPMI System Power Management Interface SPMISystem Power Management Interface I2C Inter-Integrated Circuit I2C2Inter-Integrated Circuit PFSM Pre-configured Finite State Machine PFSMPre-configured Finite State Machine UV Undervoltage UVUndervoltage OV Overvoltage OVOvervoltage POR Power On Reset PORPower On Reset UVLO Undervoltage Lockout UVLOUndervoltage Lockout OVP Overvoltage Protection OVPOvervoltage Protection EPC Embedded Power Controller EPCEmbedded Power Controller FSD First Supply Detection FSDFirst Supply Detection ESM Error Signal Monitor ESMError Signal Monitor MCU Micro Controller Unit MCUMicro Controller Unit SoC System on Chip SoCSystem on Chip BIST Built-In Self-Test BISTBuilt-In Self-Test LBIST Logic Built-In Self-Test LBISTLogic Built-In Self-Test CRC Cyclic Redundancy Check CRCCyclic Redundancy Check VMON Voltage Monitor VMONVoltage Monitor PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range) PGOODPower Good (signal which indicates that the monitored power supply rail(s) is (are) in range) Documentation Support Documentation Support Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.Alert me Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 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If BUCK3 and/or BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay time for the BUCK3 respectively BUCK4 Voltage Monitors.
• For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active after the corresponding LDOn_VMON_EN bit is set it 601..606μs.