SLVSE83B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1.     5
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad.

GUID-20211208-SS0I-FB5F-Q86Z-77DFHTWQBHJD-low.svg Figure 6-1 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View)
Table 6-1 Pin Attributes
PIN I/O DESCRIPTION CONNECTION IF NOT USED
NAME NO.
STEP-DOWN CONVERTERS (BUCKs)
FB_B1 22 I Output voltage-sense (feedback) input for BUCK1 or differential voltage-sense (feedback) positive input for BUCK12/123/1234 in multi-phase configuration. Ground
FB_B2 21 I Output voltage-sense (feedback) input for BUCK2 or differential voltage-sense (feedback) negative input for BUCK12/123/1234 in multi-phase configuration. Ground
FB_B3 49 I Output voltage-sense (feedback) input for BUCK3 or differential voltage-sense (feedback) positive input for BUCK34 in dual-phase configuration. Ground
FB_B4 50 I Output voltage-sense (feedback) input for BUCK4 or differential voltage-sense (feedback) negative input for BUCK34 in dual-phase configuration. Ground
FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground
PVIN_B1 26 I Power input for BUCK1 VCCA
PVIN_B2 17 I Power input for BUCK2 VCCA
PVIN_B3 45 I Power input for BUCK3 VCCA
PVIN_B4 54 I Power input for BUCK4 VCCA
PVIN_B5 35 I Power input for BUCK5 VCCA
SW_B1 27 O Switch node of BUCK1 Floating
SW_B1 28 O Switch node of BUCK1 Floating
SW_B2 15 O Switch node of BUCK2 Floating
SW_B2 16 O Switch node of BUCK2 Floating
SW_B3 43 O Switch node of BUCK3 Floating
SW_B3 44 O Switch node of BUCK3 Floating
SW_B4 55 O Switch node of BUCK4 Floating
SW_B4 56 O Switch node of BUCK4 Floating
SW_B5 34 O Switch node of BUCK5 Floating
LOW-DROPOUT REGULATORS
PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA
PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA
PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA
VOUT_LDO1 13 O LDO1 output voltage Floating
VOUT_LDO2 11 O LDO2 output voltage Floating
VOUT_LDO3 9 O LDO3 output voltage Floating
VOUT_LDO4 7 O LDO4 output voltage Floating
LOW-DROPOUT REGULATORS (INTERNAL)
VOUT_LDOVINT 2 O LDOVINT output for connecting to the filtering capacitor. Not for external loading. —
VOUT_LDOVRTC 3 O LDOVRTC output for connecting to the filtering capacitor. Not for external loading. —
CRYSTAL OSCILLATOR
OSC32KCAP 40 O Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC through an internal 100 Ω resistor. Floating
OSC32KIN 38 I 32-KHz crystal oscillator input Ground
OSC32KOUT 39 O 32-KHz crystal oscillator output Floating
SYSTEM CONTROL
AMUXOUT 1 O Buffered bandgap output Floating
EN_DRV 29 O Enable Drive output pin to indicate the device entering safe state (set low when ENABLE_DRV bit is '0'). Floating
GPIO1 32 I/O Primary function: General-purpose input(1) and output
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial clock (external pull-up). Ground
I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground
O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO2 33 I/O Primary function: General-purpose input(1) and output
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I/O Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial bidirectional data (external pull-up). Ground
O Alternative function: SDO_SPI, which is the SPI output data signal. Floating
I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO3 46 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I Alternative function: nERR_SoC, which is the system error count down input signal from the SoC (Active Low). Floating
O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground
GPIO4 47 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of processing a wake-up request for the device to go to higher power states while the device is in LP STANDBY state. They can also be used as regular WKUP1 or WKUP2 pins while the device is in mission states. Ground
GPIO5 23 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I/O Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial interface clock signal. The SCLK_SPMI is an output pin for the SPMI controller device, and an input pin for the SPMI peripheral device. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO6 24 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I/O Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial interface bidirectional data signal. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO7 18 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I Alternative function: nERR_MCU, which is the system error count down input signal from the MCU (Active Low). Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO8 41 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
O Alternative function: SYNCCLKOUT, which is a clock output synchronized to the switching clock signals for the bucks in the device. Floating
I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating
O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO9 19 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
O Alternative function: PGOOD, which is the indication signal for valid regulator output voltages and currents Floating
O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating
I Alternative function: DISABLE_WDOG, which is the input to disable the watchdog monitoring function. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO10 42 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I Alternative function: SYNCCLKIN, which is the external switching clock input for BUCK. Floating
O Alternative function: SYNCCLKOUT, which is the internal fallback switching clock for BUCK. Floating
O Alternative function: CLK32KOUT, which is the output of the 32 KHz crystal oscillator clock. Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GPIO11 53 I/O Primary function: General-purpose input(1) and output.
When configured as an output pin, it can be included as part of the power sequencer output signal to enable an external regulator.		 Input: Ground
Output: Floating
I Alternative function: TRIG_WDOG, which is the watchdog trigger input signal for Watchdog Trigger mode. Ground
O Alternative function: nRSTOUT_SoC, which is the SoC reset or power on output (Active Low). Floating
I Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request signals for the device to go to lower power states (Active Low). Ground
I Alternative function: WKUP1 or WKUP2, which are the wake-up request signals for the device to go to higher power states. Ground
GND 52 — Analog ground —
nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating
nPWRON/ENABLE 20 I NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the device, with configurable polarity Floating
I NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press pin to power up the device Ground
nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating
SCL_I2C1/SCK_SPI 31 I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground
I If I2C is the default interface: CLK_SPI - SPI clock signal Ground
SDA_I2C1/SDI_SPI 30 I/O If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data (external pullup) Ground
I If I2C is the default interface: SDI_SPI - SPI input data signal Ground
POWER SUPPLIES AND REFERENCE GROUNDS
GND 51 I Analog ground —
PGND/ThermalPad — — Power Ground, which is also the thermal pad of the package. Connect to PCB ground planes with multiple vias. —
REFGND1 5 — System reference ground —
REFGND2 6 — System reference ground —
VBACKUP 36 I Backup power source input pin Ground
VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks —
VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage —
(1) Default option before NVM settings are loaded into the device.