SLVSE83B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1.     5
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Digital Signal Descriptions

Table 6-2 Signal Descriptions
SIGNAL NAME I/O Threshold Level INPUT TYPE SELECTION OUTPUT TYPE SELECTION Internal PU/PD(2) RECOMMENDED EXTERNAL PU/PD(2) Control Register Bits
Power Domain DEGLITCH TIME(5) Power Domain Push-pull/Open-drain(4)
nPWRON
(Selectable function of nPWRON/ENABLE pin)(1)		 Input VIL(VCCA),
VIH(VCCA)		 VRTC 50 ms 400 kΩ PU to VCCA None NPWRON_SEL
ENABLE
(Selectable function of nPWRON/ENABLE pin)(1)		 Input VIL(VCCA),
VIH(VCCA)		 VRTC 8 µs 400 kΩ SPU to VCCA, or
400 kΩ SPD to GND		 None NPWRON_SEL
ENABLE_POL
ENABLE_DEGLITCH_EN
ENABLE_PU_PD_EN
ENABLE_PU_SEL
EN_DRV Output VOL(EN_DRV) VCCA/
PVIN_B1		 PP 10 kΩ High-side to VCCA None ENABLE_DRV
SCL_I2C1
(Selectable function of SCL_I2C1/SCK_SPI pin)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT High-speed mode:
10 ns
All other modes:
50 ns		 None PU to VIO I2C or SPI selection from NVM-configuration (6)
I2C1_HS
SDA_I2C1
(Selectable function of SDA_I2C1/SDI_SPI pin)(1)		 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO)_20mA		 VINT High-speed mode:
10 ns
All other modes:
50 ns		 VIO OD None PU to VIO I2C or SPI selection from NVM-configuration(6)
I2C1_HS
SCL_I2C2
(Selectable function of GPIO1)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT High-speed mode:
10 ns
All other modes:
50 ns		 None PU to VIO I2C or SPI selection from NVM-configuration(6)
I2C2_HS
GPIO1_SEL
SDA_I2C2
(Selectable function of GPIO2)(1)		 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO)_20mA		 VINT High-speed mode:
10 ns
All other modes:
50 ns		 VIO OD None PU to VIO I2C or SPI selection from NVM-configuration(6)
I2C2_HS
GPIO2_SEL
SCK_SPI
(Selectable function of SCL_I2C1/SCK_SPI pin)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT None None None I2C or SPI selection from NVM-configuration(6)
SDI_SPI
(Selectable function of SDA_I2C1/SDI_SPI pin)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT None None None I2C or SPI selection from NVM-configuration(6)
CS_SPI
(Selectable function of GPIO1)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT None None None I2C or SPI selection from NVM-configuration(6)
GPIO1_SEL
SDO_SPI
(Selectable function of GPIO2)(1)		 Output VOL(VIO)_20mA,
VOH(VIO)		 VIO PP(3) / HiZ None None I2C or SPI selection from NVM-configuration(6)
GPIO2_SEL
SCLK_SPMI
(Configurable function of GPIO5)(1)		 Output for SPMI controller device, input for SPMI peripheral device VIL(DIG),
VIH(DIG),
VOL(DIG)_20mA,
VOH(DIG)		 VINT None VINT PP 400 kΩ PD to GND None NVM-configuration(6)
GPIO5_SEL
GPIO5_PU_PD_EN
SDATA_SPMI
(Configurable function of GPIO6)(1)		 Input/output VIL(DIG),
VIH(DIG),
VOL(DIG)_20mA,
VOH(DIG)		 VINT None VINT PP / HiZ 400 kΩ PD to GND None NVM-configuration(6)
GPIO6_SEL
GPIO6_PU_PD_EN
nINT Output VOL(nINT) VCCA OD None PU to VCCA
nRSTOUT Output VOL(nRSTOUT) VCCA/
VIO		 PP(3) or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain
(driven low if no VINT)		 NRSTOUT_OD
nRSTOUT_SoC
(Configurable function of GPIO1 and GPIO11)(1)		 Output VOL(nRSTOUT) VCCA/
VIO		 PP(3) or OD 10 kΩ Pull-Up to VIO if configured as Push-Pull PU to VIO if Open-drain
(driven low if no VINT)		 GPIO1_SEL
GPIO1_OD
GPIO11_SEL
GPIO11_OD
PGOOD
(Configurable function of GPIO9)(1)		 Output VOL(VIO),
VOH(VIO)		 VIO PP(3) or OD None PU to VIO if Open-drain GPIO9_SEL
GPIO9_OD
PGOOD_POL
PGOOD_WINDOW
PGOOD_SEL_x
nERR_MCU
(Configurable function of GPIO7)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT 8 µs 400 kΩ PD to GND None GPIO7_SEL
nERR_SoC
(Configurable function of GPIO3)(1)		 Input VIL(DIG),
VIH(DIG)		 VRTC 15 µs 400 kΩ PD to GND None GPIO3_SEL
DISABLE_WDOG
(Configurable function of GPIO8 and GPIO9)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT 30 µs 400 kΩ PD to GND PU to VIO GPIO8_SEL
GPIO9_SEL
TRIG_WDOG
(Configurable function of GPIO2 and GPIO11)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL
GPIO2_PU_PD_EN
GPIO11_SEL
GPIO11_PU_PD_EN
nSLEEP1
(Configurable function of all GPIO pins)(1)		 Input VIL(DIG),
VIH(DIG)		 GPIO3 or 4:
VRTC
other GPIOs:
VINT		 8 µs GPIO3 or 4:
400 kΩ SPU to VRTC
GPIO5 or 6:
400 kΩ SPU to VINT
all other GPIOs:
400 kΩ SPU to VIO		 None GPIOn_SEL
GPIOn_PU_PD_EN
NSLEEP1B
nSLEEP2
(Configurable function of all GPIO pins)(1)		 Input VIL(DIG),
VIH(DIG)		 GPIO3 or 4:
VRTC
other GPIOs:
VINT		 8 µs GPIO3 or 4:
400 kΩ SPU to VRTC
GPIO5 or 6:
400 kΩ SPU to VINT
all other GPIOs:
400 kΩ SPU to VIO		 None GPIOn_SEL
GPIOn_PU_PD_EN
NSLEEP2B
WKUP1
(Configurable function of all GPIO pins except GPIO3 and GPIO4)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT 8 µs GPIO5 or 6:
400 kΩ SPU to VINT or
400 kΩ SPD to GND
all other GPIOs:
400 kΩ SPU to VIO or
400 kΩ SPD to GND		 None GPIOn_SEL
GPIOn_DEGLITCH_EN
GPIOn_PU_PD_EN
GPIOn_PU_SEL
WKUP2
(Configurable function of all GPIO pins except GPIO3 and GPIO4)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT 8 µs GPIO5 or 6:
400 kΩ SPU to VINT or
400 kΩ SPD to GND
all other GPIOs:
400 kΩ SPU to VIO or
400 kΩ SPD to GND		 None GPIOn_SEL
GPIOn_DEGLITCH_EN
GPIOn_PU_PD_EN
GPIOn_PU_SEL
LP_WKUP1
(Configurable function of GPIO3 and GPIO4)(1)		 Input VIL(DIG),
VIH(DIG)		 VRTC 8 µs,
no deglitch in LP_STANDBY state		 400 kΩ SPU to VRTC, or
400 kΩ SPD to GND		 None GPIO3,4_SEL
GPIO3,4_DEGLITCH_EN
GPIO3,4_PU_PD_EN
GPIO3,4_PU_SEL
LP_WKUP2
(Configurable function of GPIO3 and GPIO4)(1)		 Input VIL(DIG),
VIH(DIG)		 VRTC 8 µs,
no deglitch in LP_STANDBY state		 400 kΩ SPU to VRTC, or
400 kΩ SPD to GND		 None GPIO3,4_SEL
GPIO3,4_DEGLITCH_EN
GPIO3,4_PU_PD_EN
GPIO3,4_PU_SEL
GPIO1 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO)_20mA,
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO1_DIR
Input:
GPIO1_DEGLITCH_EN
GPIO1_PU_PD_EN
GPIO1_PU_SEL
Output:
GPIO1_OD
GPIO2 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO)_20mA,
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO2_DIR
Input:
GPIO2_DEGLITCH_EN
GPIO2_PU_PD_EN
GPIO2_PU_SEL
Output:
GPIO2_OD
GPIO3 Input/output VIL(DIG),
VIH(DIG),
VOL(DIG),
VOH(DIG)		 VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO3_DIR
Input:
GPIO3_DEGLITCH_EN
GPIO3_PU_PD_EN
GPIO3_PU_SEL
Output:
GPIO3_OD
GPIO4 Input/output VIL(DIG),
VIH(DIG),
VOL(DIG),
VOH(DIG)		 VRTC 8 µs VINT PP or OD 400 kΩ SPU to VINT, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO4_DIR
Input:
GPIO4_DEGLITCH_EN
GPIO4_PU_PD_EN
GPIO4_PU_SEL
Output:
GPIO4_OD
GPIO5 Input/output VIL(DIG),
VIH(DIG),
VOL(DIG)_20mA,
VOH(DIG)		 VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO5_DIR
Input:
GPIO5_DEGLITCH_EN
GPIO5_PU_PD_EN
GPIO5_PU_SEL
Output:
GPIO5_OD
GPIO6 Input/output VIL(DIG),
VIH(DIG),
VOL(DIG)_20mA,
VOH(DIG)		 VINT 8 µs VINT PP or OD 400 kΩ SPU to VINT, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO6_DIR
Input:
GPIO6_DEGLITCH_EN
GPIO6_PU_PD_EN
GPIO6_PU_SEL
Output:
GPIO6_OD
GPIO7 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO),
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO7_DIR
Input:
GPIO7_DEGLITCH_EN
GPIO7_PU_PD_EN
GPIO7_PU_SEL
Output:
GPIO7_OD
GPIO8 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO),
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO8_DIR
Input:
GPIO8_DEGLITCH_EN
GPIO8_PU_PD_EN
GPIO8_PU_SEL
Output:
GPIO8_OD
GPIO9 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO),
VOH(VIO)		 VINT 8 µs VIO P(3)P or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO9_DIR
Input:
GPIO9_DEGLITCH_EN
GPIO9_PU_PD_EN
GPIO9_PU_SEL
Output:
GPIO9_OD
GPIO10 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO),
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO10_DIR
Input:
GPIO10_DEGLITCH_EN
GPIO10_PU_PD_EN
GPIO10_PU_SEL
Output:
GPIO10_OD
GPIO11 Input/output VIL(DIG),
VIH(DIG),
VOL(VIO),
VOH(VIO)		 VINT 8 µs VIO PP(3) or OD 400 kΩ SPU to VIO, or
400 kΩ SPD to GND		 PU to VIO
if Open-drain		 GPIO11_DIR
Input:
GPIO11_DEGLITCH_EN
GPIO11_PU_PD_EN
GPIO11_PU_SEL
Output:
GPIO11_OD
SYNCCLKIN
(Configurable function of GPIO10)(1)		 Input VIL(DIG),
VIH(DIG)		 VINT None 400 kΩ SPD to GND None GPIO10_SEL
GPIO10_PU_PD_EN
SYNCCLKOUT
(Configurable function of GPIO8, GPIO9, and GPIO10)(1)		 Output VOL(VIO),
VOH(VIO)		 VIO PP(3) None None GPIO8_SEL
GPIO9_SEL
GPIO10_SEL
CLK32KOUT
(Configurable function of GPIO3, GPIO4, GPIO8, and GPIO10)(1)		 Output GPIO3 or 4:
VOL(DIG),
VOH(DIG)
GPIO8 or 10:
VOL(VIO),
VOH(VIO)		 GPIO3 or 4:
VRTC
GPIO8 or 10:
VIO		 PP(3) None None GPIO3_SEL
GPIO4_SEL
GPIO8_SEL
GPIO10_SEL
(1) Configurable function through NVM register setting.
(2) PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown.
(3) When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell.
(4) PP = Push-pull, OD = Open-drain.
(5) Deglitch time is only applicable when option is enabled.
(6) NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation.