SLVSE83B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2 pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal.
A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level transition reverses the sleep request in the example PFSM from Figure 8-39. When a NSLEEPn signal transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state. When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power state.
The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2 signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1.
When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1 input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if NSLEEP2 is 0.
The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. Table 8-20 shows how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to control the power state of the device.
The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP SLEEP/S2R states.
Table 8-20 shows the corresponding state assignment based on the state of the NSLEEPn and their corresponding mask signals using the example PFSM from Figure 8-39.
| Current State | NSLEEP1 | NSLEEP2 | NSLEEP1 MASK | NSLEEP2 MASK | Trigger to FSM | Next State | |
|---|---|---|---|---|---|---|---|
| DEEP SLEEP/S2R | 0 | 0 → 1 | 0 | 0 | TRIGGER B | MCU ONLY | |
| DEEP SLEEP/S2R | 0 → 1 | 0 → 1 | 0 | 0 | TRIGGER A | ACTIVE | |
| DEEP SLEEP/S2R | Don't care | 0 → 1 | 1 | 0 | TRIGGER A | ACTIVE | |
| DEEP SLEEP/S2R or MCU ONLY |
0 → 1 | Don't care | 0 | 1 | TRIGGER A | ACTIVE | |
| MCU ONLY | 0 → 1 | 1 | 0 | 0 | TRIGGER A | ACTIVE | |
| MCU ONLY | 0 | 1 → 0 | 0 | 0 | TRIGGER D | DEEP SLEEP or S2R | |
| MCU ONLY | Don't care | 1 → 0 | 1 | 0 | TRIGGER D | DEEP SLEEP or S2R | |
| ACTIVE | 1 → 0 | 1 | 0 | 0 | TRIGGER B | MCU ONLY | |
| ACTIVE | 1 → 0 | 1 → 0 | 0 | 0 | TRIGGER D | DEEP SLEEP or S2R | |
| ACTIVE | Don't care | 1 → 0 | 1 | 0 | TRIGGER D | DEEP SLEEP or S2R | |
| ACTIVE | 1 → 0 | Don't care | 0 | 1 | TRIGGER B | MCU ONLY | |