SLVSE83B December   2020  – September 2023 TPS6593-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1.     5
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1. 6.1 Digital Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)
    6. 7.6  Low Noise Low Drop-Out Regulator (LDO4)
    7. 7.7  Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)
    8. 7.8  BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators
    9. 7.9  Reference Generator (BandGap)
    10. 7.10 Monitoring Functions
    11. 7.11 Clocks, Oscillators, and PLL
    12. 7.12 Thermal Monitoring and Shutdown
    13. 7.13 System Control Thresholds
    14. 7.14 Current Consumption
    15. 7.15 Backup Battery Charger
    16. 7.16 Digital Input Signal Parameters
    17. 7.17 Digital Output Signal Parameters
    18. 7.18 I/O Pullup and Pulldown Resistance
    19. 7.19 I2C Interface
    20. 7.20 Serial Peripheral Interface (SPI)
    21. 7.21 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  System Supply Voltage Monitor
      2. 8.3.2  Power Resources (Bucks and LDOs)
        1. 8.3.2.1 Buck Regulators
          1. 8.3.2.1.1  BUCK Regulator Overview
          2. 8.3.2.1.2  Multi-Phase Operation and Phase-Adding or Shedding
          3. 8.3.2.1.3  Transition Between PWM and PFM Modes
          4. 8.3.2.1.4  Multi-Phase BUCK Regulator Configurations
          5. 8.3.2.1.5  Spread-Spectrum Mode
          6. 8.3.2.1.6  Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          7. 8.3.2.1.7  BUCK Output Voltage Setting
          8. 8.3.2.1.8  BUCK Regulator Current Limit
          9. 8.3.2.1.9  SW_Bx Short-to-Ground Detection
          10. 8.3.2.1.10 Sync Clock Functionality
          11.        49
        2. 8.3.2.2 Low Dropout Regulators (LDOs)
          1. 8.3.2.2.1 LDOVINT
          2. 8.3.2.2.2 LDOVRTC
          3. 8.3.2.2.3 LDO1, LDO2, and LDO3
          4. 8.3.2.2.4 Low-Noise LDO (LDO4)
      3. 8.3.3  Output Voltage Monitor and PGOOD Generation
      4. 8.3.4  Thermal Monitoring
        1. 8.3.4.1 Thermal Warning Function
        2. 8.3.4.2 Thermal Shutdown
      5. 8.3.5  Backup Supply Power-Path
      6. 8.3.6  General-Purpose I/Os (GPIO Pins)
      7. 8.3.7  nINT, EN_DRV, and nRSTOUT Pins
      8. 8.3.8  Interrupts
      9. 8.3.9  RTC
        1. 8.3.9.1 General Description
        2. 8.3.9.2 Time Calendar Registers
          1. 8.3.9.2.1 TC Registers Read Access
          2. 8.3.9.2.2 TC Registers Write Access
        3. 8.3.9.3 RTC Alarm
        4. 8.3.9.4 RTC Interrupts
        5. 8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
      10. 8.3.10 Watchdog (WDOG)
        1. 8.3.10.1 Watchdog Fail Counter and Status
        2. 8.3.10.2 Watchdog Start-Up and Configuration
        3. 8.3.10.3 MCU to Watchdog Synchronization
        4. 8.3.10.4 Watchdog Disable Function
        5. 8.3.10.5 Watchdog Sequence
        6. 8.3.10.6 Watchdog Trigger Mode
        7. 8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       79
        9. 8.3.10.8 Watchdog Question-Answer Mode
          1. 8.3.10.8.1 Watchdog Q&A Related Definitions
          2. 8.3.10.8.2 Question Generation
          3. 8.3.10.8.3 Answer Comparison
            1. 8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 8.3.10.8.3.2 Watchdog Sequence Events and Status Updates
            3. 8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios
      11. 8.3.11 Error Signal Monitor (ESM)
        1. 8.3.11.1 ESM Error-Handling Procedure
          1. 8.3.11.1.1 Level Mode
          2.        90
          3. 8.3.11.1.2 PWM Mode
            1. 8.3.11.1.2.1 Good-Events and Bad-Events
            2. 8.3.11.1.2.2 ESM Error-Counter
            3. 8.3.11.1.2.3 ESM Start-Up in PWM Mode
            4. 8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
            5.         96
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device State Machine
        1. 8.4.1.1 Fixed Device Power FSM
          1. 8.4.1.1.1 Register Resets and NVM Read at INIT State
        2. 8.4.1.2 Pre-Configurable Mission States
          1. 8.4.1.2.1 PFSM Commands
            1. 8.4.1.2.1.1  REG_WRITE_IMM Command
            2. 8.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 8.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 8.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 8.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 8.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 8.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 8.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 8.4.1.2.1.9  SREG_READ_REG Command
            10. 8.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 8.4.1.2.1.11 WAIT Command
            12. 8.4.1.2.1.12 DELAY_IMM Command
            13. 8.4.1.2.1.13 DELAY_SREG Command
            14. 8.4.1.2.1.14 TRIG_SET Command
            15. 8.4.1.2.1.15 TRIG_MASK Command
            16. 8.4.1.2.1.16 END Command
          2. 8.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 8.4.1.2.3 Mission State Configuration
          4. 8.4.1.2.4 Pre-Configured Hardware Transitions
            1. 8.4.1.2.4.1 ON Requests
            2. 8.4.1.2.4.2 OFF Requests
            3. 8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 8.4.1.2.4.4 WKUP1 and WKUP2 Functions
            5. 8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
        3. 8.4.1.3 Error Handling Operations
          1. 8.4.1.3.1 Power Rail Output Error
          2. 8.4.1.3.2 Catastrophic Error
          3. 8.4.1.3.3 Watchdog (WDOG) Error
          4. 8.4.1.3.4 Warnings
        4. 8.4.1.4 Device Start-up Timing
        5. 8.4.1.5 Power Sequences
        6. 8.4.1.6 First Supply Detection
        7. 8.4.1.7 Register Power Domains and Reset Levels
      2. 8.4.2 Multi-PMIC Synchronization
        1. 8.4.2.1 SPMI Interface System Setup
        2. 8.4.2.2 Transmission Protocol and CRC
          1. 8.4.2.2.1 Operation with Transmission Errors
          2. 8.4.2.2.2 Transmitted Information
        3. 8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 8.4.2.4 SPMI-BIST Overview
          1. 8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 8.4.2.4.2 Periodic Checking of the SPMI
          3. 8.4.2.4.3 SPMI Message Priorities
    5. 8.5 Control Interfaces
      1. 8.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.5.2 I2C-Compatible Interface
        1. 8.5.2.1 Data Validity
        2. 8.5.2.2 Start and Stop Conditions
        3. 8.5.2.3 Transferring Data
        4. 8.5.2.4 Auto-Increment Feature
      3. 8.5.3 Serial Peripheral Interface (SPI)
    6. 8.6 Configurable Registers
      1. 8.6.1 Register Page Partitioning
      2. 8.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.6.3 CRC Protection for User Registers
      4. 8.6.4 Register Write Protection
        1. 8.6.4.1 Watchdog and ESM Configuration Registers
        2. 8.6.4.2 User Registers
    7. 8.7 Register Maps
      1. 8.7.1 TPS6593-Q1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Powering a Processor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VCCA
          2. 9.2.1.2.2 Internal LDOs
          3. 9.2.1.2.3 Crystal Oscillator
          4. 9.2.1.2.4 Buck Input Capacitors
          5. 9.2.1.2.5 Buck Output Capacitors
          6. 9.2.1.2.6 Buck Inductors
          7. 9.2.1.2.7 LDO Input Capacitors
          8. 9.2.1.2.8 LDO Output Capacitors
          9. 9.2.1.2.9 Digital Signal Connections
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Device Nomenclature
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.4.1.2.2 Configuration Memory Organization and Sequence Execution

The configuration memory is loaded from NVM into an SRAM. Figure 8-38 shows an example configuration memory with only two configured sequences.

GUID-B0F11E19-21EE-4FEB-84B5-5DDEDCBC6B53-low.gif Figure 8-38 Configuration Memory Script Example

As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to an internal lookup table that contains the starting address associated with each trigger in the configuration memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state transitions. The signal source of each trigger is listed under Table 8-15.

When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address associated with the highest priority unmasked trigger, and starts executing commands until it hits an END command. The last commands before END statement is generally the TRIG_MASK command, which directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located at the lowest trigger IDs.

The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced immediately, which involves branching from the current sequence of commands to reach a new target destination. The non-immediate triggers are accumulated and serviced in the order of priority through the execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for each trigger can be arranged to produce the desired PFSM behavior.

The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of triggers to be enabled with a single command. Through the definition of the active triggers after each sequence execution the TRIG_MASK command can be conceptualized as establishing a power state.

The above sequence of waiting for triggers and executing the sequence associated with an activated trigger is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The fixed device power FSM takes over control from the execution engine each time an event occurs that requires a transition from the MISSION state of the PMIC to a fixed device state.

Table 8-15 PFSM Trigger Selections
Trigger Name Trigger Source
IMMEDIATE_SHUTDOWN An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and the intended action for the activated trigger is to immediate shutdown the device.
MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01').
ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'.
FORCE_STANDBY nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL = '00'.
SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST.
ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT.
WD_ERROR An event that causes WD_RST_INT.
SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10').
ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT
A NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under Section 8.4.1.2.4.3.
WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1.
SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'.
B NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions can be found under Section 8.4.1.2.4.3.
WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2.
SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'.
C NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under Section 8.4.1.2.4.3.
D NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions can be found under Section 8.4.1.2.4.3.
SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'.
SU_X A valid On-Request detection when STARTUP_DEST = '01'.
WAIT_TIMEOUT PFSM WAIT command condition timed out. More information regarding the WAIT command can be found under Section 8.4.1.2.1.11.
GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO.
GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO.
GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO.
GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO.
GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO.
GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO.
GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO.
GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO.
GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO.
GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO.
GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO.
I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS)
I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS)
I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS)
I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS)
I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS)
I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS)
I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS)
I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS)
SREG0_0 Input detection of bit 0 in PFSM storage register R0
SREG0_1 Input detection of bit 1 in PFSM storage register R0
SREG0_2 Input detection of bit 2 in PFSM storage register R0
SREG0_3 Input detection of bit 3 in PFSM storage register R0
SREG0_4 Input detection of bit 4 in PFSM storage register R0
SREG0_5 Input detection of bit 5 in PFSM storage register R0
SREG0_6 Input detection of bit 6 in PFSM storage register R0
SREG0_7 Input detection of bit 7 in PFSM storage register R0
0 Always '0'
1 Always '1'