The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important. Good power supply results only occur when care is given to correct design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results.

With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators are stable and maintain correct voltage and current regulation across its intended operating voltage and current range.

1. Place C_IN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the V_IN trace wide and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of C_OUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. This output filter must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VCCA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the processor. If the processor does not support remote voltage sensing, then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I²C. Avoid capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. If series resistors are used for load current measurement, place them after connection of the voltage feedback.
5. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx.

For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than 2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See illustration below:

Figure 9-69 Ground connection of capacitor at VOUT_LDOVINT pin

Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced junction-to-ambient (R_θJA) and junction-to-board (R_θJB) thermal resistances and thereby reduces the device junction temperature, T_J. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.

Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following weights for the Copper layers:

• 0.5oz for signal layers
• at least 1.5oz for top layer and other plane layers

A more complete list of layout recommendations can be found in the Schematic and layout checklist.