SBVS436B june   2022  – august 2023 TPS7A15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Active Overshoot Pulldown Circuitry
      3. 7.3.3 Global Undervoltage Lockout (UVLO)
      4. 7.3.4 Enable Input
      5. 7.3.5 Internal Foldback Current Limit
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input, Output, and Bias Capacitor Requirements
      3. 8.1.3  Dropout Voltage
      4. 8.1.4  Behavior During Transition From Dropout Into Regulation
      5. 8.1.5  Device Enable Sequencing Requirement
      6. 8.1.6  Load Transient Response
      7. 8.1.7  Undervoltage Lockout Circuit Operation
      8. 8.1.8  Power Dissipation (PD)
      9. 8.1.9  Estimating Junction Temperature
      10. 8.1.10 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-E1B466F2-F464-4925-8471-EE4A262157B1-low.svgFigure 5-1 YCK Package,6-Pin WCSP, 0.35-mm Pitch(Top View)
Table 5-1 Pin Functions: YCK Package
PINTYPEDESCRIPTION
NO.NAME
A1OUTOutputRegulated output pin. A 1-µF or greater capacitance is required from OUT to ground for stability. For best transient response, use a 2.2-µF or larger ceramic capacitor from OUT to GND. Place the output capacitor as close to OUT as possible.
A2INInputInput pin. A 0.75-µF or greater capacitance is required from IN to ground for stability. For good transient response, use a 2.2-µF or larger ceramic capacitor from IN to GND. Place the input capacitor as close to input of the device as possible.
B1SENSEInputSENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT and the load.
B2ENInputEnable pin. Driving this pin to logic high enables the low-dropout regulator (LDO). Driving this pin to logic low disables the LDO. If enable functionality is not required, this pin must be connected to IN or BIAS.
C1GND—Ground pin. This pin must be connected to ground.
C2BIASInputBIAS pin. This pin enables the use of low-input voltage, low-output voltage (LILO) conditions. For best performance, use a 0.1-µF or larger ceramic capacitor from BIAS to GND. Place the bias capacitor as close to BIAS as possible.
GUID-20230522-SS0I-HVPN-DWHL-G1FKQNG7W4KS-low.svgFigure 5-2 DRV Package,6-Pin WSON With Exposed Thermal Pad(Top View)
Table 5-2 Pin Functions: DRV Package
PINTYPEDESCRIPTION
NO.NAME
4BIASInputBIAS pin. This pin enables the use of LILO conditions. For best performance, use a 0.1-µF or larger ceramic capacitor from BIAS to GND. Place the bias capacitor as close to BIAS as possible.
3ENInputEnable pin. Driving this pin to logic high enables the LDO. Driving this pin to logic low disables the LDO. If enable functionality is not required, this pin must be connected to IN or BIAS.
5GND—Ground pin. This pin must be connected to ground.
6INInputInput pin. A 0.75-µF or greater capacitance is required from IN to ground for stability. For good transient response, use a 2.2-µF or larger ceramic capacitor from IN to GND. Place the input capacitor as close to input of the device as possible.
1OUTOutputRegulated output pin. A 1-µF or greater capacitance is required from OUT to ground for stability. For best transient response, use a 2.2-µF or larger ceramic capacitor from OUT to GND. Place the output capacitor as close to OUT as possible.
2SENSEInputSENSE input. This pin is a feedback input to the regulator for SENSE connections. Connecting SENSE to the load helps eliminate voltage errors resulting from trace resistance between OUT and the load.
Thermal Pad—The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance.