SBVS436B june   2022  – august 2023 TPS7A15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Active Overshoot Pulldown Circuitry
      3. 7.3.3 Global Undervoltage Lockout (UVLO)
      4. 7.3.4 Enable Input
      5. 7.3.5 Internal Foldback Current Limit
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input, Output, and Bias Capacitor Requirements
      3. 8.1.3  Dropout Voltage
      4. 8.1.4  Behavior During Transition From Dropout Into Regulation
      5. 8.1.5  Device Enable Sequencing Requirement
      6. 8.1.6  Load Transient Response
      7. 8.1.7  Undervoltage Lockout Circuit Operation
      8. 8.1.8  Power Dissipation (PD)
      9. 8.1.9  Estimating Junction Temperature
      10. 8.1.10 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) TPS7A15 UNIT
DRV (WSON) YCK (DSBGA)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance(2) 75.7 148.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.1 1.3 °C/W
RθJB Junction-to-board thermal resistance 35.0 42.1 °C/W
ψJT Junction-to-top characterization parameter 4.0 0.5 °C/W
ψJB Junction-to-board characterization parameter 35.0 42.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 19.7 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) For information about how to improve junction-to-ambient thermal resistance, see the An empirical analysis of the impact of board layout on LDO thermal performance application note.