SBVS233B January   2016  – June 2021 TPS7A84

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Low-Noise, High-PSRR Output
      2. 7.3.2  Integrated Resistance Network (ANY-OUT)
      3. 7.3.3  Bias Rail
      4. 7.3.4  Power-Good Function
      5. 7.3.5  Programmable Soft-Start
      6. 7.3.6  Internal Current Limit (ILIM)
      7. 7.3.7  Enable
      8. 7.3.8  Active Discharge Circuit
      9. 7.3.9  Undervoltage Lockout (UVLO)
      10. 7.3.10 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 1.1 V ≤ VIN < 1.4 V
      2. 7.4.2 Operation with 1.4 V ≤ VIN ≤ 6.5 V
      3. 7.4.3 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input and Output Capacitor Requirements (CIN and COUT)
      3. 8.1.3  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      4. 8.1.4  Feed-Forward Capacitor (CFF)
      5. 8.1.5  Soft-Start and In-Rush Current
      6. 8.1.6  Optimizing Noise and PSRR
      7. 8.1.7  Charge Pump Noise
      8. 8.1.8  ANY-OUT Programmable Output Voltage
      9. 8.1.9  ANY-OUT Operation
      10. 8.1.10 Increasing ANY-OUT Resolution for LILO Conditions
      11. 8.1.11 Current Sharing
      12. 8.1.12 Adjustable Operation
      13. 8.1.13 Sequencing Requirements
        1. 8.1.13.1 Sequencing with a Power-Good DC-DC Converter Pin
        2. 8.1.13.2 Sequencing with a Microcontroller (MCU)
      14. 8.1.14 Power-Good Operation
      15. 8.1.15 Undervoltage Lockout (UVLO) Operation
      16. 8.1.16 Dropout Voltage (VDO)
      17. 8.1.17 Behavior when Transitioning from Dropout into Regulation
      18. 8.1.18 Load Transient Response
      19. 8.1.19 Negatively-Biased Output
      20. 8.1.20 Reverse Current Protection
      21. 8.1.21 Power Dissipation (PD)
      22. 8.1.22 Estimating Junction Temperature
      23. 8.1.23 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application for a 5.0-V Rail
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.21 Power Dissipation (PD)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can be calculated using Equation 9:

Equation 9. PD = (VIN – VOUT) × IOUT

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A84 allows for maximum efficiency across a wide range of output voltages.

The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 10. The equation is rearranged for output current in Equation 11.

Equation 10. TJ = TA + (RθJA × PD)
Equation 11. IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]

Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Section 6.5 table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.