SLVSD43C May 2015 – February 2019 TPS7B68-Q1
PRODUCTION DATA.
The power-good delay period is a function of the value set by an external capacitor on the DELAY pin before turning the PG pin high. Connecting an external capacitor from this pin to GND sets the power-good delay period. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and Equation 2 determines the power-good delay period:
where
NOTE:
V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST).If the DELAY pin is open, the default delay time is t(DLY_FIX).