SLVSI35A September   2024  – December 2024 TPS7C84-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.2 Feedforward Capacitor

Connect a feedforward capacitor (CFF) between the OUT pin and the FB pin. CFF improves transient, noise, and PSRR performance. If a higher capacitance CFF is used, the start-up time increases. For a detailed description of the CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

As shown in Figure 7-3, poor layout practices and using long traces at the FB pin results in the formation of a parasitic capacitor (CFB).

TPS7C84-Q1 Formation of a Parasitic Capacitor at the FB Pin Figure 7-3 Formation of a Parasitic Capacitor at the FB Pin

CFB, along with the feedback resistors R1 and R2 potentially results in the formation of an uncompensated pole in the transfer function of the loop gain. A CFB value as small as 6pF potentially causes the parasitic pole frequency, given by Equation 8, to fall within the LDO bandwidth and result in instability.

Equation 8. fP= 12×π×CFB×R1∥R2

Adding a feedforward capacitor (CFF) creates a zero in the loop gain transfer function that compensates for the parasitic pole created by CFB. Figure 7-4 shows this compensation. Equation 9 and Equation 10 calculate the pole and zero frequencies.

TPS7C84-Q1 A Feedforward Capacitor Compensates the Effects of the Parasitic Capacitor Figure 7-4 A Feedforward Capacitor Compensates the Effects of the Parasitic Capacitor
Equation 9. fP= 12×π×R1∥R2×CFF+CFB
Equation 10. fZ= 12×π×CFF×R1

The CFF value that makes fP equal to fZ depends on the values of CFB and the feedback resistors used in the application. This CFF value also results in a pole-zero cancellation. Alternatively, if the feedforward capacitor is selected so that CFF ≫ CFB, then the pole and zero frequencies from Equation 9 and Equation 10 are related as:

Equation 11. fpfz ≅ 1+ R1R2 = VOUTVFB

In most applications, particularly where a 3.3V or 5V VOUT is generated, this ratio is not very large. Thus implying that the frequencies are located close to each other and therefore the parasitic pole is compensated. A CFF value of approximately 100pF ≤ CFF ≤ 10nF typically helps prevent instability caused by the parasitic capacitance on the feedback node. This CFF range helps even for large VOUT values, where this ratio is potentially as large as 20.