SLVSD81A January   2016  – February 2017 TPS7H1101-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start
      2. 8.3.2 Power Good (PG)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable/Disable
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Adjustable Output Voltage (Feedback Circuit)
        2. 9.2.2.2 PCL
        3. 9.2.2.3 High-Side Current Sense
        4. 9.2.2.4 Current Foldback
        5. 9.2.2.5 Transient Response
        6. 9.2.2.6 Current Sharing
        7. 9.2.2.7 Compensation
        8. 9.2.2.8 Output Noise
        9. 9.2.2.9 Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • For best performance, all traces should be as short as possible, and no longer than 5 cm.
  • Use wide traces for IN, Out and GND to minimize the parasitic electrical effects.
  • Place the output capacitors (COUT) as close as possible to the OUT pin of the device.

11.2 Layout Example

TPS7H1101-SP layout_ex_LVSAS4.gif Figure 27. PCB Layout Example