SLVSD81A January   2016  – February 2017 TPS7H1101-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start
      2. 8.3.2 Power Good (PG)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable/Disable
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Stability
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Adjustable Output Voltage (Feedback Circuit)
        2. 9.2.2.2 PCL
        3. 9.2.2.3 High-Side Current Sense
        4. 9.2.2.4 Current Foldback
        5. 9.2.2.5 Transient Response
        6. 9.2.2.6 Current Sharing
        7. 9.2.2.7 Compensation
        8. 9.2.2.8 Output Noise
        9. 9.2.2.9 Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

HKR Package
16-Pin CFP
Bottom View
TPS7H1101-SP po_hkr_lvsas4.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
SS 1 O Soft-start terminal. Connecting an external capacitor slows down the output voltage ramp rate after enable event. The soft-start terminal can be used to disable the device as described in theSoft Start section.
EN 2 I Enable terminal. Driving this terminal to logic high enables the device; driving the terminal to logic low disables the device. VIN voltage must be greater than 3.5 V when using the EN pin. For VIN < 3.5 V, enable terminal cannot be used to disable the device.
TI recommends to connect the enable terminal to VIN.
VIN 3 I Unregulated supply voltage. TI recommends to connect an input capacitor as a good analog circuit practice.
4
5
6
PCL 7 O Programmable current limit. A resistor to GND sets the overcurrent limit activation point.
The range of resistor that can be used on the PCL terminal to GND is 8.2 kΩ to 160 kΩ.
GND 8 — Ground/thermal pad.(1)
PG/OC 9 O Power Good terminal. PG is an open-drain output to indicate the output voltage reaches 90% of target. PG terminal is also used as indicator when an overcurrent condition is activated. PG pin should have a pull-up resistor to the VOUT pin.
CS 10 O Current sense terminal. Resistor connected from CS to VIN. CS terminal indicates voltage proportional to output current.
CS terminal low: Foldback current limit disabled
CS terminal high: Foldback current limit enabled
VOUT 11 O Regulated output.
12
13
14
COMP 15 I Internal compensation point for error amplifier.
FB 16 I The output voltage feedback input through voltage dividers. See Adjustable Output Voltage (Feedback Circuit) section.
(1) Thermal pad must be connected to GND.