SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Options Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Capacitance

The TPS7H1111 is optimized for a single tantalum output capacitor of 220 μF or two 100 μF capacitors. The complete range of acceptable capacitance, ESR, and ESL are specified in the Recommended Operating Conditions. Make note to verify the selected capacitors meet the requirements across all operating conditions. Additionally, a single 0.1 μF ceramic capacitor can be included. Place the one or more tantalum capacitors near the output of the TPS7H1111 and place the ceramic capacitor near the point of load.

ESR (equivalent series resistance) is an important parasitic element to take into account that varies significantly across frequency for capacitors. ESR values for tantalum capacitors are generally given at 100 kHz, and the values in the Recommended Operating Conditions table approximately correspond to values at 100 kHz. However, in reality the ESR at the loop crossover frequency is primarily what affects the stability of the TPS7H1111 control loop. The loop crossover frequency can be higher or lower than 100 kHz. Therefore, the range of ESR values can be considered a good guideline, but additional verification of stability is prudent.

Also note that the capacitance, ESR, and ESL requirements are for the entire bulk capacitance. If 2x100 μF capacitors each with 40 mΩ ESR and 2 nH ESL are used, the resulting capacitance is 200 μF with 20 mΩ ESR and 1 nH ESL. The single ceramic capacitor should not be taken into account when considering these ESR and ESL requirements.

Ceramic capacitors larger than 0.1 µF are generally not allowed due to their lower resonance frequency. This lower resonance frequency is likely within the loop bandwidth of the TPS7H1111 regulator (which can be nearly 10 MHz). Therefore, the low resonance point, combined with the low ESR, negatively impacts the loop bandwidth and device stability. The lower bandwidth negatively affects PSRR, therefore negating any potential benefit of additional ceramic capacitance.

However, if ceramic capacitors above 0.1 µF must be used, it is recommended the ceramic capacitor has a resonance frequency one to two decades above the loop bandwidth. Alternatively additional series resistance can be added to increase the ESR. This prevents a strong resonance point.

TI has measured gain and phase margin of various space grade capacitors to demonstrate good stability margin. See Section 9.3 for additional information.

When capacitors other than the standard bulk capacitance and a single 0.1 µF capacitor are utilized, it is recommended to simulate the capacitors and complete system. It is also suggested to create a Bode plot and perform load steps on the actual system to verify sufficient stability margin.