SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.9 Current Sharing

The TPS7H1111 supports paralleling multiple devices in order to increase the output current or spread heat dissipation. While a single device is capable of outputting 1.5 A of current, two devices are capable of outputting slightly less than 3 A. This is because each device will not source exactly 50% of the current. The mismatch in current between the two devices is due to differences in the error amplifier offset, VOS, of each device. Mismatch due to differences in the reference current, ISET, is removed by tying the SS_SET nets together. This is shown in a simplified schematic in Figure 8-8.

Note that an RSET resistance of half the normal value should be used since there is now 200 μA (typ) of current through the resistor. Furthermore, two CSS capacitors should be utilized (or one of twice the normal value) in order to ensure equivalent start-up time. Finally, each device should have its normal output capacitance. When paralleling two devices, this results in twice the capacitance on VOUT(final) when compared with a single device. The output capacitors in Figure 8-8 are placed after the ballast resistor (closest to the load). This placement adds some effective ESR to the capacitors as seen by the TPS7H1111 control loop. It is also acceptable to add the capacitors before the ballast resistors directly at the OUT pins, but this may result in a slightly larger voltage drop during a load step due to the ballast resistor being placed between the output capacitors and the load.

To calculate the mismatch first between two devices, the total output current, IOUT, the set output voltage, VSS_SET, the offset voltage of each device, VOS, and the ballast resistor, Rballast, must be known. The ballast resistor may be selected to meet the desired current matching requirements; however, it should be noted that the larger the ballast resistor , the worse the load regulation will be due to IR drops across the ballast resistor. Then, the combined output voltage, VOUT(final), must be calculated as shown in Equation 9. This is the voltage that will be seen at the load.

Equation 9. VOUT(final) = [(VSS_SET + VOS1) + (VSS_SET + VOS2) – IOUT × Rballast] / 2

Next the current in each device is calculated using Equation 10 and Equation 11

Equation 10. IOUT1 = (VSS_SET + VOS1 – VOUT(final)) / Rballast
Equation 11. IOUT2 = (VSS_SET + VOS2 – VOUT(final)) / Rballast

This calculated current can be compared to the ideal current through each device, IOUT(total) / 2.

GUID-20201112-CA0I-JXQW-FJRX-RLXDDPWTQWLM-low.svg Figure 8-8 Current Sharing Simplified Schematic

Ideally the offset of each device would be measured to determine the exact current sourced by each device. As this is generally infeasible, it is often tempting to use the worst case offset shown in the Electrical Characteristics. This would result in setting VOS1 to the maximum specified VOS and VOS2 to the minimum specified VOS. However, this may result in an overly pessimistic mismatch. To aid in analysis, histograms of multiple measured units of offset data are provided in Figure 6-47, Figure 6-48, and Figure 6-49. Additionally, measurements have shown better than calculated results as described in Section 9.2.2.

A simplified diagram showing current sharing and the source of error is given in Figure 8-9.

GUID-20230106-SS0I-JMXT-LGLG-GVQVCTW85PMN-low.svg Figure 8-9 Current Sharing Simplified Schematic