SLVSFT8 Data sheet

SLVSFT8F February 2023 – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

PWP|28

Thermal pad, mechanical data (Package|Pins)

PWP|28
- PPTD290A

Orderable Information

6.7 Typical Characteristics

V_IN = 2.5 V, V_OUT = 1.8 V, V_BIAS = 5 V, I_OUT = 1 A, C_OUT = 2 × 100 µF, C_SS = 4.7 µF, R_REF = 12.0 kΩ, R_BIAS = 10 Ω, C_BIAS = 4.7 µF, T_A = 25°C, unless otherwise noted, integrated noise reported with 10-Hz to 100-kHz bandwidth.

V_BIAS = 5 V

Figure 6-1 PSRR vs Frequency (Common Configurations)

V_IN = V_OUT + V_DO	V_OUT = 1.8 V	V_BIAS = V_OUT + 1.6 V

Figure 6-3 PSRR vs Frequency Across Dropout

V_IN = V_OUT + 0.8 V		V_BIAS = V_IN + 1.6 V

Figure 6-5 PSRR vs Frequency Across Output Voltage

See Table 9-4 for capacitor part numbers utilized.

Figure 6-7 PSRR vs Frequency Across Output Capacitors

Figure 6-9 PSRR vs Frequency Across Bias Supply

R_BIAS = 0 Ω		C_BIAS = 0 µF

Figure 6-11 PSRR vs Frequency With V_IN = V_BIAS

R_BIAS = 10 Ω

Figure 6-13 PSRR_BIAS vs Frequency Across Bias Voltage With RC

Figure 6-15 Output Noise vs Frequency Across C_SS (Noise Spectral Density)

See Table 9-4 for capacitor part numbers utilized.

Figure 6-17 Output Noise vs Frequency Across Output Capacitor (Noise Spectral Density)

V_OUT = V_IN – 0.8 V

Figure 6-19 Output Noise vs Frequency Across Input Voltage (Noise Spectral Density)

V_BIAS = 12 V

Figure 6-2 PSRR vs Frequency (Common Configurations)

Figure 6-4 PSRR vs Frequency Across Output Current

V_OUT = V_IN – 0.8 V		V_BIAS = V_OUT + 1.6 V

Figure 6-6 PSRR vs Frequency Across Input Voltage

Figure 6-8 PSRR vs Frequency Across Soft Start Capacitance

I_OUT = 500 mA

Figure 6-10 PSRR vs Frequency Across Temperature

R_BIAS = 0 Ω

Figure 6-12 PSRR_BIAS vs Frequency Across Bias Voltage Without RC

I_OUT = 500 mA

Figure 6-14 PSRR_BIAS vs Frequency Across Temperature

Figure 6-16 Output Noise vs Frequency Across Output Current (Noise Spectral Density)

V_IN = V_OUT + 0.8 V

Figure 6-18 Output Noise vs Frequency Across Output Voltage (Noise Spectral Density)

C_OUT = 2 × 100 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
I_OUT = 0 A: Phase Margin = 83°, Gain Margin = 29 dB
I_OUT = 1.5 A: Phase Margin = 99°, Gain Margin = 19 dB

Figure 6-20 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 2 × 100 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
I_OUT = 0 A: Phase Margin = 61°, Gain Margin = 27 dB
I_OUT = 1.5 A: Phase Margin = 99°, Gain Margin = 12 dB

Figure 6-22 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 1 × 220 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
I_OUT = 0 A: Phase Margin = 71°, Gain Margin = 30 dB
I_OUT = 1.5 A: Phase Margin = 91°, Gain Margin = 14 dB

Figure 6-24 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 1 × 220 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
I_OUT = 0 A: Phase Margin = 72°, Gain Margin = 19 dB
I_OUT = 1.5 A: Phase Margin = 66°, Gain Margin = 8 dB

Figure 6-26 Gain and Phase vs Frequency (Bode Plot)

Figure 6-28 Dropout Voltage vs Temperature

Figure 6-30 Dropout Voltage vs Temperature Without Separate V_BIAS

I_OUT = 0 A

Figure 6-32 Quiescent Current vs Temperature

I_OUT = 1.5 A

Figure 6-34 Ground Current vs Temperature

V_EN = 0 V

Figure 6-36 Shutdown Current vs Temperature

Figure 6-38 SET Pin Current vs Temperature

Figure 6-40 Offset Voltage vs Current

V_EN = 7 V	V_IN = 7 V	V_BIAS = 14 V

Figure 6-42 Enable Leakage Current vs Temperature

V_IN = 0.85 V	V_BIAS = 2.2 V	I_OUT = 1 mA
I_PG = 2 mA

Figure 6-44 PG Pin Output Low vs Temperature

I_OUT = 0 mA

Figure 6-46 SS_SET Pin Current During Startup vs Temperature

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-48 Output Offset Voltage Distribution at T_A = 25°C

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-50 I_SET Current Distribution at T_A = –55°C

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-52 I_SET Current Distribution at T_A = 125°C

0.85 V ≤ V_IN ≤ 7 V, 1 mA ≤ I_OUT ≤ 1.5 A, 2.2 V ≤ V_BIAS ≤ 14 V, P_D ≤ 4 W

Figure 6-54 Output Voltage Accuracy Distribution at T_A = 25°C

Slew Rate = 10.1 A/µs

Figure 6-56 Load Step: 1 mA to 1.5 A

Slew Rate = 0.9 A/µs

Figure 6-58 Load Step: 1 mA to 1.5 A

Slew Rate = 8.5 A/µs	I_OUT is only the stepped current, parallel 0.5 A load not shown

Figure 6-60 Load Step: 0.5 A to 1.5 A

Slew Rate = 20.2 V/ms		V_OUT = 0.4 V

Figure 6-62 Line Step: 1.8 V to 5 V With I_OUT = 1.5 A

Slew Rate = 84.0 V/ms		V_OUT = 0.4 V

Figure 6-64 Line Step: 1.8 V to 5 V With I_OUT = 1 mA

Figure 6-66 Startup Waveform

C_OUT = 2 × 100 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 19 dB

Figure 6-21 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 2 × 100 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 13 dB

Figure 6-23 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 1 × 220 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 98°, Gain Margin = 14 dB

Figure 6-25 Gain and Phase vs Frequency (Bode Plot)

C_OUT = 1 × 220 μF + 0.1 μF. See Table 9-4 for capacitors utilized and information on ceramic and plastic package differences.
Phase Margin = 94°, Gain Margin = 9 dB

Figure 6-27 Gain and Phase vs Frequency (Bode Plot)

V_IN = 5 V		V_BIAS = V_IN + 1.6 V

Figure 6-29 Dropout Voltage vs Current

Figure 6-31 Dropout Voltage vs Current Without Separate V_BIAS

I_OUT = 0 A

Figure 6-33 Bias Current vs Temperature

I_OUT = 1.5 A

Figure 6-35 Bias Current vs Temperature

V_EN = 0 V

Figure 6-37 Bias Shutdown Current vs Temperature

I_OUT = 1 mA

Figure 6-39 Offset Voltage vs Temperature

Figure 6-41 Output Voltage vs Temperature

V_{FB_PG} = 6 V	V_IN = 7 V	V_BIAS = 14 V
I_OUT = 1 mA

Figure 6-43 FB_PG Pin Leakage Current vs Temperature

V_IN = 7 V	V_BIAS = 14 V	I_OUT = 1 mA
V_PG = 7 V

Figure 6-45 PG Pin Leakage vs Temperature

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-47 Output Offset Voltage Distribution at T_A = –55°C

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-49 Output Offset Voltage Distribution at T_A = 125°C

0.85 V ≤ V_IN ≤ 7 V, 2.2 V ≤ V_BIAS ≤ 14 V, I_OUT = 1 mA

Figure 6-51 I_SET Current Distribution at T_A = 25°C

0.85 V ≤ V_IN ≤ 7 V, 1 mA ≤ I_OUT ≤ 1.5 A, 2.2 V ≤ V_BIAS ≤ 14 V, P_D ≤ 4 W

Figure 6-53 Output Voltage Accuracy Distribution at T_A = –55°C

0.85 V ≤ V_IN ≤ 7 V, 1 mA ≤ I_OUT ≤ 1.5 A, 2.2 V ≤ V_BIAS ≤ 14 V, P_D ≤ 4 W

Figure 6-55 Output Voltage Accuracy Distribution at T_A = 125°C

Slew Rate = 13.1 A/µs

Figure 6-57 Load Step: 1.5 A to 1 mA

Slew Rate = 1.0 A/µs

Figure 6-59 Load Step: 1.5 A to 1 mA

Slew Rate = 8.1 A/µs	I_OUT is only the stepped current, parallel 0.5 A load not shown

Figure 6-61 Load Step: 1.5 A to 0.5 A

Slew Rate = 144.8 V/ms		V_OUT = 0.4 V

Figure 6-63 Line Step: 5 V to 1.8 V With I_OUT = 1.5 A

Slew Rate = 85.1 V/ms		V_OUT = 0.4 V

Figure 6-65 Line Step: 5 V to 1.8 V With I_OUT = 1 mA