SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBL|14
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 Capacitors Tested

TI has tested various space grade capacitors and measured the control loop response of the TPS7H1111 system. The effects of different capacitors is clearly shown, but in all cases stability is demonstrated across the current range. The measured gain margin (GM) in decibels and phase margins (PM) in degrees is shown in Table 9-4. Results are taken with VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V at room temperature at the indicated current levels. The Bode plots themselves are shown in Figure 6-20 through Figure 6-27.

Table 9-4 Tested Space Grade Capacitors
Manufacturer Capacitance Part Numbers IOUT = 0 A IOUT = 1 A IOUT = 1.5 A
PM GM PM GM PM GM
Kemet 1x220 µF T540D227K010AH6710 71 30 98 14 91 14
Kemet 1x220 µF + 0.1 µF(1) T540D227K010AH6710 + C0603K104K3RML 72 19 94 9 66 8
AVX 2x100 µF TBME107K020LBLC9045 83 29 98 19 99 19
AVX 2x100 µF + 0.1 µF TBME107K020LBLC9045 + 300904102104KA 61 27 98 13 99 12
(1) Not recommended for the plastic package due to the lower gain margin.

The values reported above are for the ceramic package TPS7H1111-SP. The plastic package (TPS7H1111-SP and TPS7H1111-SEP) were found to have similar stability responses but with a approximately two decibel lower gain margin. Also note that gain margin decreases at high current and low temperature. Phase margin decreases at low current and high temperature.