SLVSFT8F February   2023  – December 2023 TPS7H1111-SEP , TPS7H1111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply
      2. 8.3.2  Output Voltage Configuration
      3. 8.3.3  Output Voltage Configuration with a Voltage Source
      4. 8.3.4  Enable
      5. 8.3.5  Soft Start and Noise Reduction
      6. 8.3.6  Configurable Power Good
      7. 8.3.7  Current Limit
      8. 8.3.8  Stability
        1. 8.3.8.1 Output Capacitance
        2. 8.3.8.2 Compensation
      9. 8.3.9  Current Sharing
      10. 8.3.10 PSRR
      11. 8.3.11 Noise
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application 1: Set Turn-On Threshold with EN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bias Supply
          2. 9.2.1.2.2 Output Voltage Configuration
          3. 9.2.1.2.3 Output Voltage Accuracy
          4. 9.2.1.2.4 Enable Threshold
          5. 9.2.1.2.5 Soft Start and Noise Reduction
          6. 9.2.1.2.6 Configurable Power Good
          7. 9.2.1.2.7 Current Limit
          8. 9.2.1.2.8 Output Capacitor and Ferrite Bead
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Application 2: Parallel Operation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing
        3. 9.2.2.3 Application Results
    3. 9.3 Capacitors Tested
    4. 9.4 TID Effects
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBL|14
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over 0.85 V ≤ VIN ≤ 7 V, VBIAS ≥ VOUT + 1.6 V (VIN ≤ VBIAS ≤ 14 V & VBIAS ≥ 2.2 V), VOUT (target) ≤ VIN – 1.6 V, IOUT = 1 mA, COUT = 220 µF(1), RREF = 12.0 kΩ, over operating temperature range (TA = –55°C to 125°C), typical values are at TA = 25°C, unless otherwise noted; includes RLAT at TA = 25°C if sub-group number is present for QML RHA and SEP devices(2)
PARAMETER TEST CONDITIONS SUB-GROUP(3) MIN TYP MAX UNIT
POWER SUPPLIES AND CURRENTS
VDO Dropout voltage with 
VBIAS ≥ VOUT + 1.6 V		 0.85 V ≤ VIN ≤ 7 V,
VOUT = 98.5% × VOUT(NOM)		 IOUT = 0.1 A 1, 2, 3 17 40 mV
IOUT = 0.5 A 1, 2, 3 75 150
IOUT = 1 A 1, 2, 3 110 280
IOUT = 1.5 A 1, 2, 3 215 430
VDO Dropout voltage with VBIAS = VIN 2.2 V ≤ VIN ≤ 7 V,
VOUT = 98.5% × VOUT(NOM)		 IOUT = 0.1 A 1, 2, 3 785 1100 mV
IOUT = 0.5 A 1, 2, 3 908 1150
IOUT = 1 A 1, 2, 3 1063 1250
IOUT = 1.5 A 1, 2, 3 1168 1400
ILIM Output current limit 2.5 V ≤ VIN ≤ 7 V
VOUT = 0.5 V,
VCLM = VIN		 TA = -55°C 3 1.8 1.95 2.1 A
TA = 25°C 1 1.75 1.85 2
TA = 125°C 2 1.7 1.8 1.95
ICLM(LKG) CLM input leakage current VCLM = 7 V 1, 2, 3 5 150 nA
IQ_IN Quiescent current VEN = 7 V, IOUT = 0 A
1, 2, 3

 19 27 mA
IQ_BIAS Bias current with no output load VEN = 7 V, IOUT = 0 A
1, 2, 3

 16 25
IIN_GND IIN – IOUT with full output load VEN = 7 V, IOUT = 1.5 A
1, 2, 3

 20 27 mA
IBIAS Bias current with full output load VEN = 7 V, IOUT = 1.5 A
1, 2, 3

 17 25
ISHDN Shutdown current VEN = 0 V, IOUT = 0 A, VOUT = 0 V
1, 2, 3

 20 350 µA
ISHDN_BIAS Shutdown bias current VEN = 0 V, IOUT = 0 A, VOUT = 0 V
1, 2, 3

 550 1000
ACCURACY
VACC Output voltage accuracy
 1 mA ≤ IOUT ≤ 1.5 A,
2.2 V ≤ VBIAS ≤ 14 V(4),
PD ≤ 4 W(5)		 –55°C ≤ TA ≤ 125°C 1, 2, 3 -1.3% 1.2%
TA = –55°C 3 -1.3% 0.5%
TA = 25°C 1 -0.7% 0.9%
TA = 25°C, post TID(6) 1 -0.7% 1.1%
TA = 125°C 2 -0.7% 1.2%
ISET SS_SET pin current to set VOUT
 –55°C ≤ TA ≤ 125°C
1, 2, 3

 98.8 99.9 101 µA
TA = –55°C 3 98.8 99.4 100.3
TA = 25°C 1 99.0 100 100.9
TA = 125°C 2 99.2 100.2 101
VOS Output offset voltage
(VOUT – VSS_SET)
 –55°C ≤ TA ≤ 125°C 1, 2, 3 –2 0.78 mV
TA = -55°C 3 –1.33 –0.2 0.78
TA = 25°C 1 –1.45 –0.25 0.76
TA = 25°C, post TID(6) 1 –1.45 1.5
TA = 125°C 2 –2 –0.5 0.7
VOUTtempco VOUT temperature coefficient TA from –55°C to 125°C 0.004% VOUT/
°C
TA from –55°C to –40°C 0.011%
TA from –40°C to 0°C 0.007%
TA from 0°C to 25°C 0.005%
TA from 25°C to 85°C 0.003%
TA from 85°C to 125°C 0.001%
VREF Reference voltage, ceramic package 1, 2, 3 1.191 1.206 1.220 V
VREF Reference voltage, plastic package 1, 2, 3 1.190 1.206 1.221
ΔVOUT/ΔVIN Line regulation, see Figure 7-1 0.85 V ≤ VIN ≤ 7 V, IOUT = 1 mA, VBIAS = 5 V, VOUT = 0.4 V 1, 2, 3 3 200 µV/V
ΔVOUT/ΔIOUT Load regulation, see Figure 7-2 1 mA ≤ IOUT ≤ 1.5 A, VBIAS = 5 V, VIN = 2.5 V, VOUT = 1.8 V 1, 2, 3 500 1000 µV/A
Current sharing error percentage Rballast = 5 mΩ,
TA = 25°C		 IOUT(TOTAL) = 1.2 A ±1%
IOUT(TOTAL) = 2.9 A ±0.1%
IOUTS(LKG) OUTS leakage current 1, 2, 3 20 200 nA
ENABLE
VEN(rising) Enable rising threshold (turn-on) 1, 2, 3 0.58 0.60 0.62 V
VEN(falling) Enable falling threshold (turn-off) 1, 2, 3 0.48 0.50 0.52
tEN(delay) EN propagation delay EN high to VOUT = 10 mV 9, 10, 11 90 500 µs
IEN(LKG) Enable input leakage current VEN = 7 V 1, 2, 3 3 150 nA
TSD(enter) Thermal shutdown enter 160 °C
TSD(exit) Thermal shutdown exit 130
POWER GOOD
VFB_PG(rising) Power good rising threshold 1, 2, 3
 290 306 313 mV
VFB_PG(HYS) Power good hysteresis 1, 2, 3 7 14 19
IFB_PG(LKG) FB_PG input leakage current VFB_PG = 6 V 1, 2, 3 9 150 nA
VPG(OL) Power good output low IPG(SINK) = 2 mA 1, 2, 3 113 200 mV
VIN(MIN_PG) Minimum VIN or VBIAS for valid PG (VPG < 0.5 V) IPG(sink) = 0.6 mA 1, 2, 3
 0.6 0.8 V
IPG(LKG) Power good leakage VPG = 7 V, VFB_PG > VFB_PG(rising threshold) 1, 2, 3
 0.1 2 µA
SOFT START
ISS_SET(start) SS_SET pin current during startup 1, 2, 3
 1.68 2.1 2.52 mA
tSS Soft-start time VIN = 2.5 V, VOUT = 1.8 V,
IOUT = 1 A, 
RFB_PG(top) = 44.2 kΩ, 
RFB_PG(bot) = 10 kΩ		 CSS = 2.2 µF 1.7 ms
CSS = 4.7 µF 3.7
CSS = 10 µF 7.8
NOISE AND PSRR
PSRR Power-supply rejection ratio VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V, IOUT = 1 A, CSS = 4.7 µF,
CBIAS = 4.7 µF,
RBIAS = 10 Ω		 fripple = 100 Hz 109 dB
fripple = 1 kHz 109
fripple = 10 kHz 90
fripple = 100 kHz 71
fripple = 1 MHz 66
fripple = 10 MHz 30
PSRRBIAS Power-supply rejection ratio,
VBIAS to VOUT		 VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V, IOUT = 1 A, CSS = 4.7 µF,
CBIAS = 4.7 µF,
RBIAS = 10 Ω		 fripple = 100 Hz 102 dB
fripple = 1 kHz 105
fripple = 10 kHz 87
fripple = 100 kHz 97
fripple = 1 MHz 118
fripple = 10 MHz 68
VN Output noise rms voltage
(Bandwidth from 10 Hz to 100 kHz)		 VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V, IOUT = 1 A CSS = 2.2 µF 1.73 µVRMS
CSS = 4.7 µF 1.71
CSS = 10 µF 1.69
eN Output noise voltage density VIN = 2.5 V, VOUT = 1.8 V, VBIAS = 5 V,
IOUT = 1 A, CSS = 4.7 µF		 f = 10 Hz 97 nV/√Hz
f = 100 Hz 11.2
f = 1 kHz 5.4
f = 10 kHz 5.6
f = 100 kHz 4.9
f = 1 MHz 1.6
f = 10 MHz 1.7
STABILITY
PM Phase margin VIN = 2.5 V, VOUT = 1.8 V, IOUT = 1.0 A,
COUT = 2x100 µF(7)		 98°
GM Gain margin 19 dB
(1) A single 220 µF tantalum capacitor is utilized
(2) See the 5962R21203 SMD for additional information on the QML RHA devices and see the V62/23602 VID for additional information on the SEP devices.
(3) The subgroups are only applicable for QML versions of the device; for subgroup definitions, see Section 6.6.
(4) Additionally, VBIAS ≥ VIN and VBIAS ≥ VOUT + 1.6 V.
(5) PD is the internal power dissipation. When PD exceeds 4 W, the current is lowered to avoid excessive local heating (due to tester limitations).
(6) TID = 100 krad(Si) for QMLV and QMLP parts and TID = 50 krad(Si) for SEP parts.
(7) See Section 9.3 for additional information.